27#include "mcci_bootloader_device_npm1300.h"
28#include "mcci_npm1300.h"
53McciBootloaderDeviceI2cBusStm32l0_t
56McciBootloaderDeviceI2cDeviceStm32l0_t
59McciBootloaderDeviceNpm1300_t *
87#define FUNCTION "McciBootloaderBoard_Catena5230_systemInit"
99 McciBootloaderDeviceI2cBusStm32l0_t *
const pI2cBus =
104 pI2cBus,
sizeof(*pI2cBus),
161 McciBootloaderDevice_NPM1300_createAndAttach(
162 &pI2cBus->I2cBusCast,
175 const static McciBootloaderDevice_NPM1300_Init_t pmicInitTable[] =
177 { MCCI_PMIC_NPM1300_REG_BCHGVTERM, 0x08 },
178 { MCCI_PMIC_NPM1300_REG_BCHGVTERMR, 0x08 },
179 { MCCI_PMIC_NPM1300_REG_BCHGDISABLESET, 0x02 },
180 { MCCI_PMIC_NPM1300_REG_BCHGDISABLECLR, 0x01 },
181 { MCCI_PMIC_NPM1300_REG_BCHGISETMSB, 0xC8 },
182 { MCCI_PMIC_NPM1300_REG_BCHGISETLSB, 0x00 },
183 { MCCI_PMIC_NPM1300_REG_BCHGDISABLESET, 0x02 },
184 { MCCI_PMIC_NPM1300_REG_BCHGENABLESET, 0x01 },
185 { MCCI_PMIC_NPM1300_REG_BUCKENASET_1, 0x01 },
186 { MCCI_PMIC_NPM1300_REG_BUCKNORMVOUT_1, 0x17 },
187 { MCCI_PMIC_NPM1300_REG_BUCKSWCTRLSEL, 0x01 },
188 { MCCI_PMIC_NPM1300_REG_BUCKENASET_2, 0x01 },
189 { MCCI_PMIC_NPM1300_REG_LDSWLDOSEL_1, 0x01 },
190 { MCCI_PMIC_NPM1300_REG_LDSWVOUTSEL_1, 0x17 },
191 { MCCI_PMIC_NPM1300_REG_LDSWLDOSEL_2, 0x00 },
192 { MCCI_PMIC_NPM1300_REG_TASKLDSWSET_1, 0x01 },
193 { MCCI_PMIC_NPM1300_REG_TASKLDSWCLR_2, 0x01 },
194 { MCCI_PMIC_NPM1300_REG_VBUSINILIMSTARTUP, 0x0F },
195 { MCCI_PMIC_NPM1300_REG_LEDDRVMODESEL_0, 0x01 },
196 { MCCI_PMIC_NPM1300_REG_LEDDRVMODESEL_1, 0x00 },
199 const McciBootloaderDeviceI2cResult_t result =
200 McciBootloaderDevice_NPM1300_initializeRegisters(
203 MCCIADK_LENOF(pmicInitTable)
206 if (result != McciBootloaderDeviceI2cResult_OK)
static uint32_t McciArm_putRegMasked(uint32_t reg, uint32_t maskVal, uint32_t modVal)
store to cm0plus register under mask
@ McciBootloaderError_PmicProbeFailed
failed to probe PMIC.
@ McciBootloaderError_PmicInitFailed
failed to initialize PMIC.
#define MCCI_BOOTLOADER_FIELD_SET_VALUE(fmask, val)
McciBootloaderPlatform_SystemInitFn_t McciBootloaderBoard_Catena1sj_systemInit
#define MCCI_BOOTLOADER_STM32L0_I2C_TIMINGR_100K
value for 100k ("standard mode")
const McciBootloaderDeviceI2cBusStm32l0_Config_t gk_McciBootloaderDeviceI2cBusStm32l0_Config_I2c2
global config for I2C2. Linker discards this if not used.
#define MCCI_BOOTLOADER_STM32L0_I2C_TIMINGR_1M
value for 1M ("fast mode plus")
#define MCCI_BOOTLOADER_STM32L0_I2C_TIMINGR_400K
value for 400k ("fast mode")
McciBootloaderDeviceI2cBus_t * McciBootloader_Stm32L0Interface_initI2cBus(void *pRamForBus, size_t sizeForBus, const McciBootloaderDeviceI2cBusStm32l0_Config_t *pConfig, uint32_t timingr100k, uint32_t timingr400k, uint32_t timingr1M)
Initialize an I2C bus controller driver on an STM32L0.
#define MCCI_STM32L0_GPIO_PUPD_P(p)
compute the mask for the mode bits for port bits 0..15
#define MCCI_STM32L0_REG_GPIOB
Section 9.4.12: GPIO register map (1K)
#define MCCI_STM32L0_GPIO_MODER
#define MCCI_STM32L0_GPIO_AFRx_P(p)
#define MCCI_STM32L0_GPIO_PUPD_PULLUP
#define MCCI_STM32L0_GPIO_OSPEEDR
#define MCCI_STM32L0_GPIO_OSPEED_P(p)
compute the mask for the mode bits for port bits 0..15
#define MCCI_STM32L0_GPIO_MODE_AF
#define MCCI_STM32L0_GPIO_OTYPE_OD
#define MCCI_STM32L0_GPIO_OTYPE_P(p)
compute the mask for the mode bits for port bits 0..15
#define MCCI_STM32L0_GPIO_OSPEED_MEDIUM
#define MCCI_STM32L0_GPIO_PUPDR
#define MCCI_STM32L0_GPIO_OTYPER
#define MCCI_STM32L0_GPIO_MODE_P(p)
compute the mask for the mode bits for port bits 0..15
#define MCCI_STM32L0_GPIO_AFSEL_P(p)
get AFRx mask for port bit p.
void McciBootloaderBoard_Catena5230_systemInit(void)
McciBootloaderDeviceNpm1300_t * g_McciBootloaderBoard_Catena5230_pNPM1300
McciBootloaderDeviceI2cBusStm32l0_t g_McciBootloaderBoard_Catena5230_i2cBus2
McciBootloaderDeviceI2cDeviceStm32l0_t g_McciBootloaderBoard_Catena5230_i2cDevice_NPM1300