MCCI Trusted Bootloader
Simple trusted bootloader and tools for small embedded systems
Data Structures | Macros | Functions
mcci_arm_cm0plus.h File Reference
#include "mcci_bootloader_bits.h"
#include <stdint.h>

Go to the source code of this file.

Data Structures

union  Mcci_CortexAppEntry_t
 application entry object More...
 
struct  Mcci_CortexAppEntryContents_t
 application entry contents More...
 
union  Mcci_CortexVectors_t
 Cortex M0 interrupt vector object. More...
 
struct  Mcci_CortexVectorsContents_t
 Cortex M0 interrupt vectors (low level view) More...
 

Macros

#define _mcci_arm_cm0plus_h_   /* prevent multiple includes */
 
#define MCCI_CM0PLUS_SCS_BASE   UINT32_C(0xE000E000)
 
CPU Special function registers
#define MCCI_CM0PLUS_SYSM_APSR   UINT32_C(0x00)
 Flags from previous instructions.
 
#define MCCI_CM0PLUS_SYSM_CONTROL   UINT32_C(0x14)
 control register
 
#define MCCI_CM0PLUS_SYSM_EAPSR   UINT32_C(0x02)
 Composite of EPSR and APSR.
 
#define MCCI_CM0PLUS_SYSM_EPSR   UINT32_C(0x06)
 Exception status register.
 
#define MCCI_CM0PLUS_SYSM_IAPSR   UINT32_C(0x01)
 Composite of IPSR and APSR.
 
#define MCCI_CM0PLUS_SYSM_IEPSR   UINT32_C(0x07)
 Composite of IPSR and EPSR.
 
#define MCCI_CM0PLUS_SYSM_IPSR   UINT32_C(0x05)
 Interrupt status register.
 
#define MCCI_CM0PLUS_SYSM_MSP   UINT32_C(0x08)
 Main stack pointer.
 
#define MCCI_CM0PLUS_SYSM_PRIMASK   UINT32_C(0x10)
 priority mask register
 
#define MCCI_CM0PLUS_SYSM_PSP   UINT32_C(0x09)
 Process stack pointer.
 
#define MCCI_CM0PLUS_SYSM_XPSR   UINT32_C(0x03)
 Composite of EPSR, IPSR and APSR.
 
PRIMASK special register fields
#define MCCI_CM0PLUS_SR_PRIMASK_DISABLE   (UINT32_C(1) << 0)
 the bit to disable interrupts
 
SYSTICK registers
#define MCCI_CM0PLUS_SYSTICK   UINT32_C(0xE000E010)
 
#define MCCI_CM0PLUS_SYSTICK_CALIB   (MCCI_CM0PLUS_SYSTICK + 0xC)
 
#define MCCI_CM0PLUS_SYSTICK_CSR   (MCCI_CM0PLUS_SYSTICK + 0x0)
 
#define MCCI_CM0PLUS_SYSTICK_CVR   (MCCI_CM0PLUS_SYSTICK + 0x8)
 
#define MCCI_CM0PLUS_SYSTICK_RVR   (MCCI_CM0PLUS_SYSTICK + 0x4)
 
NVIC registers
#define MCCI_CM0PLUS_NVIC   UINT32_C(0xE000E100)
 
#define MCCI_CM0PLUS_NVIC_ICER   (MCCI_CM0PLUS_NVIC + 0x080)
 
#define MCCI_CM0PLUS_NVIC_ICPR   (MCCI_CM0PLUS_NVIC + 0x180)
 
#define MCCI_CM0PLUS_NVIC_IP0   (MCCI_CM0PLUS_NVIC + 0x300)
 
#define MCCI_CM0PLUS_NVIC_IP1   (MCCI_CM0PLUS_NVIC + 0x304)
 
#define MCCI_CM0PLUS_NVIC_IP2   (MCCI_CM0PLUS_NVIC + 0x308)
 
#define MCCI_CM0PLUS_NVIC_IP3   (MCCI_CM0PLUS_NVIC + 0x30C)
 
#define MCCI_CM0PLUS_NVIC_IP4   (MCCI_CM0PLUS_NVIC + 0x310)
 
#define MCCI_CM0PLUS_NVIC_IP5   (MCCI_CM0PLUS_NVIC + 0x314)
 
#define MCCI_CM0PLUS_NVIC_IP6   (MCCI_CM0PLUS_NVIC + 0x318)
 
#define MCCI_CM0PLUS_NVIC_IP7   (MCCI_CM0PLUS_NVIC + 0x31C)
 
#define MCCI_CM0PLUS_NVIC_ISER   (MCCI_CM0PLUS_NVIC + 0x000)
 
#define MCCI_CM0PLUS_NVIC_ISPR   (MCCI_CM0PLUS_NVIC + 0x100)
 
SCB registers
#define MCCI_CM0PLUS_SCB   UINT32_C(0xE000ED00)
 
#define MCCI_CM0PLUS_SCB_AIRCR   (MCCI_CM0PLUS_SCB + 0x0C)
 
#define MCCI_CM0PLUS_SCB_CCR   (MCCI_CM0PLUS_SCB + 0x14)
 
#define MCCI_CM0PLUS_SCB_CPUID   (MCCI_CM0PLUS_SCB + 0x00)
 
#define MCCI_CM0PLUS_SCB_DFSR   (MCCI_CM0PLUS_SCB + 0x30)
 
#define MCCI_CM0PLUS_SCB_ICSR   (MCCI_CM0PLUS_SCB + 0x04)
 
#define MCCI_CM0PLUS_SCB_SCR   (MCCI_CM0PLUS_SCB + 0x10)
 
#define MCCI_CM0PLUS_SCB_SHCSR   (MCCI_CM0PLUS_SCB + 0x24)
 
#define MCCI_CM0PLUS_SCB_SHPR2   (MCCI_CM0PLUS_SCB + 0x1C)
 
#define MCCI_CM0PLUS_SCB_SHPR3   (MCCI_CM0PLUS_SCB + 0x20)
 
#define MCCI_CM0PLUS_SCB_VTOR   (MCCI_CM0PLUS_SCB + 0x08)
 
MPU registers
#define MCCI_CM0PLUS_MPU   UINT32_C(0xE000ED90)
 
#define MCCI_CM0PLUS_MPU_CTRL   (MCCI_CM0PLUS_MPU + 0x04)
 
#define MCCI_CM0PLUS_MPU_RASR   (MCCI_CM0PLUS_MPU + 0x10)
 
#define MCCI_CM0PLUS_MPU_RBAR   (MCCI_CM0PLUS_MPU + 0x0C)
 
#define MCCI_CM0PLUS_MPU_RNR   (MCCI_CM0PLUS_MPU + 0x08)
 
#define MCCI_CM0PLUS_MPU_TYPE   (MCCI_CM0PLUS_MPU + 0x00)
 
SYSTICK CSR bits
#define MCCI_CM0PLUS_SYSTICK_CSR_CLKSOURCE   (UINT32_C(1) << 2)
 use processor (not external) clock
 
#define MCCI_CM0PLUS_SYSTICK_CSR_COUNTFLAG   (UINT32_C(1) << 16)
 timer has counted to zero
 
#define MCCI_CM0PLUS_SYSTICK_CSR_ENABLE   (UINT32_C(1) << 0)
 enable counter
 
#define MCCI_CM0PLUS_SYSTICK_CSR_RSV17   UINT32_C(0xFFFE0000)
 reserved
 
#define MCCI_CM0PLUS_SYSTICK_CSR_RSV3   UINT32_C(0x0000FFF8)
 reserved
 
#define MCCI_CM0PLUS_SYSTICK_CSR_TICKINT   (UINT32_C(1) << 1)
 enable tick exception
 
SYSTICK RVR bits
#define MCCI_CM0PLUS_SYSTICK_RVR_RELOAD   UINT32_C(0x00FFFFFF)
 reload value
 
#define MCCI_CM0PLUS_SYSTICK_RVR_RSV24   UINT32_C(0xFF000000)
 reserved, zero
 
SYSTICK CVR bits
#define MCCI_CM0PLUS_SYSTICK_CVR_CURRENT   UINT32_C(0x00FFFFFF)
 current value
 
#define MCCI_CM0PLUS_SYSTICK_CVR_RSV24   UINT32_C(0xFF000000)
 reserved, read as zero
 
SYSTICK CALIB bits
#define MCCI_CM0PLUS_SYSTICK_CALIB_NOREF   (UINT32_C(1) << 31)
 reference clock is not implemented
 
#define MCCI_CM0PLUS_SYSTICK_CALIB_RSV24   (UINT32_C(0x3F) << 24)
 reserved, zero
 
#define MCCI_CM0PLUS_SYSTICK_CALIB_SKEW   (UINT32_C(1) << 30)
 10ms cal value is inexact
 
#define MCCI_CM0PLUS_SYSTICK_CALIB_TENMS   UINT32_C(0x00FFFFFF)
 if non-zero, use this as reload value for 10ms ticks
 
SCB CPUID fields
#define MCCI_CM0PLUS_SCB_CPUID_ARCHITECTURE   (UINT32_C(0xF) << 16)
 Architecture code.
 
#define MCCI_CM0PLUS_SCB_CPUID_IMPLEMENTER   (UINT32_C(0xFF) << 24)
 Implementer code.
 
#define MCCI_CM0PLUS_SCB_CPUID_PARTNO   (UINT32_C(0xFFF) << 4)
 Part number.
 
#define MCCI_CM0PLUS_SCB_CPUID_REVISION   (UINT32_C(0xF) << 0)
 Revision.
 
#define MCCI_CM0PLUS_SCB_CPUID_VARIANT   (UINT32_C(0xF) << 20)
 Variant code.
 
SCB ICSR fields
#define MCCI_CM0PLUS_SCB_ICSR_ISRPENDING   (UINT32_C(1) << 22)
 
#define MCCI_CM0PLUS_SCB_ICSR_ISRPREEMPT   (UINT32_C(1) << 23)
 
#define MCCI_CM0PLUS_SCB_ICSR_NMIPENDSET   (UINT32_C(1) << 31)
 
#define MCCI_CM0PLUS_SCB_ICSR_PENDSTCLR   (UINT32_C(1) << 26)
 
#define MCCI_CM0PLUS_SCB_ICSR_PENDSTSET   (UINT32_C(1) << 26)
 
#define MCCI_CM0PLUS_SCB_ICSR_PENDSVCLR   (UINT32_C(1) << 27)
 
#define MCCI_CM0PLUS_SCB_ICSR_PENDSVSET   (UINT32_C(1) << 28)
 
#define MCCI_CM0PLUS_SCB_ICSR_RSV24   (UINT32_C(1) << 24)
 
#define MCCI_CM0PLUS_SCB_ICSR_RSV29   (UINT32_C(3) << 29)
 
#define MCCI_CM0PLUS_SCB_ICSR_VECTACTIVE   (UINT32_C(0x1FF) << 0)
 
#define MCCI_CM0PLUS_SCB_ICSR_VECTPENDING   (UINT32_C(0x1FF) << 12)
 
SCB VTOR fields
#define MCCI_CM0PLUS_SCB_VTOR_TBLOFF   UINT32_C(0xFFFFFF00)
 
SCB AIRCR fields (Appplication Interrupt and Reset Control)
#define MCCI_CM0PLUS_SCB_AIRCR_ENDIANNESS   (UINT32_C(1) << 15)
 
#define MCCI_CM0PLUS_SCB_AIRCR_SYSRESETREQ   (UINT32_C(1) << 2)
 
#define MCCI_CM0PLUS_SCB_AIRCR_VECTCLRACTIVE   (UINT32_C(1) << 1)
 
#define MCCI_CM0PLUS_SCB_AIRCR_VECTKEY   (UINT32_C(0xFFFF) << 16)
 Vector key.
 
#define MCCI_CM0PLUS_SCB_AIRCR_VECTKEY_VALUE   (UINT32_C(0x05FA) << 16)
 Value to write to unlock regster.
 
SCB SCR fields
#define MCCI_CM0PLUS_SCB_SCR_SEVONPEND   (UINT32_C(1) << 4)
 
#define MCCI_CM0PLUS_SCB_SCR_SLEEPDEEP   (UINT32_C(1) << 2)
 
#define MCCI_CM0PLUS_SCB_SCR_SLEEPONEXIT   (UINT32_C(1) << 1)
 
SCB Configuration Control Register bits
#define MCCI_CM0PLUS_SCB_CCR_STKALIGN   (UINT32_C(1) << 9)
 
#define MCCI_CM0PLUS_SCB_CCR_UNALIGNED   (UINT32_C(1) << 3)
 
SCB System Handler Control and State Register bits
#define MCCI_CM0PLUS_SCB_SHCSR_SVCALLPENDED   (UINT32_C(1) << 15)
 

Functions

static uint32_t McciArm_getReg (uint32_t reg)
 read a 32-bit value from a cm0plus register
 
static uint32_t McciArm_putReg (uint32_t reg, uint32_t val)
 write a 32-bit value to a cm0plus register
 
static uint32_t McciArm_putRegAndOr (uint32_t reg, uint32_t andVal, uint32_t orVal)
 and/or 32-bit values to a cm0plus register
 
static uint32_t McciArm_putRegClear (uint32_t reg, uint32_t clearVal)
 clear out 32-bit values to a cm0plus register
 
static uint32_t McciArm_putRegClearSet (uint32_t reg, uint32_t clearVal, uint32_t setVal)
 clear and set 32-bit values to a cm0plus register
 
static uint32_t McciArm_putRegMasked (uint32_t reg, uint32_t maskVal, uint32_t modVal)
 store to cm0plus register under mask
 
static uint32_t McciArm_putRegOr (uint32_t reg, uint32_t orVal)
 or 32-bit values to a cm0plus register
 

SCB SHPR access

#define MCCI_CM0PLUS_PRI_INDEX_PENDSV   UINT32_C(14)
 priority of systick
 
#define MCCI_CM0PLUS_PRI_INDEX_SVC   UINT32_C(11)
 priority of systick
 
#define MCCI_CM0PLUS_PRI_INDEX_SYSTICK   UINT32_C(15)
 priority of systick
 
#define MCCI_CM0PLUS_SCB_SHPR_PRI   (UINT32_C(3) << 6)
 priority bits within a byte
 
static uint32_t McciCm0Plus_SCB_SHPR_getMask (uint32_t handlerIndex)
 return byte mask for a given handler index
 
static uint32_t McciCm0Plus_SCB_SHPR_getRegister (uint32_t handlerIndex)
 return register for a given handler index
 

Macro Definition Documentation

◆ _mcci_arm_cm0plus_h_

#define _mcci_arm_cm0plus_h_   /* prevent multiple includes */

Definition at line 23 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_MPU

#define MCCI_CM0PLUS_MPU   UINT32_C(0xE000ED90)

Definition at line 116 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_MPU_CTRL

#define MCCI_CM0PLUS_MPU_CTRL   (MCCI_CM0PLUS_MPU + 0x04)

Definition at line 118 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_MPU_RASR

#define MCCI_CM0PLUS_MPU_RASR   (MCCI_CM0PLUS_MPU + 0x10)

Definition at line 121 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_MPU_RBAR

#define MCCI_CM0PLUS_MPU_RBAR   (MCCI_CM0PLUS_MPU + 0x0C)

Definition at line 120 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_MPU_RNR

#define MCCI_CM0PLUS_MPU_RNR   (MCCI_CM0PLUS_MPU + 0x08)

Definition at line 119 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_MPU_TYPE

#define MCCI_CM0PLUS_MPU_TYPE   (MCCI_CM0PLUS_MPU + 0x00)

Definition at line 117 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_NVIC

#define MCCI_CM0PLUS_NVIC   UINT32_C(0xE000E100)

Definition at line 84 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_NVIC_ICER

#define MCCI_CM0PLUS_NVIC_ICER   (MCCI_CM0PLUS_NVIC + 0x080)

Definition at line 86 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_NVIC_ICPR

#define MCCI_CM0PLUS_NVIC_ICPR   (MCCI_CM0PLUS_NVIC + 0x180)

Definition at line 88 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_NVIC_IP0

#define MCCI_CM0PLUS_NVIC_IP0   (MCCI_CM0PLUS_NVIC + 0x300)

Definition at line 89 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_NVIC_IP1

#define MCCI_CM0PLUS_NVIC_IP1   (MCCI_CM0PLUS_NVIC + 0x304)

Definition at line 90 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_NVIC_IP2

#define MCCI_CM0PLUS_NVIC_IP2   (MCCI_CM0PLUS_NVIC + 0x308)

Definition at line 91 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_NVIC_IP3

#define MCCI_CM0PLUS_NVIC_IP3   (MCCI_CM0PLUS_NVIC + 0x30C)

Definition at line 92 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_NVIC_IP4

#define MCCI_CM0PLUS_NVIC_IP4   (MCCI_CM0PLUS_NVIC + 0x310)

Definition at line 93 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_NVIC_IP5

#define MCCI_CM0PLUS_NVIC_IP5   (MCCI_CM0PLUS_NVIC + 0x314)

Definition at line 94 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_NVIC_IP6

#define MCCI_CM0PLUS_NVIC_IP6   (MCCI_CM0PLUS_NVIC + 0x318)

Definition at line 95 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_NVIC_IP7

#define MCCI_CM0PLUS_NVIC_IP7   (MCCI_CM0PLUS_NVIC + 0x31C)

Definition at line 96 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_NVIC_ISER

#define MCCI_CM0PLUS_NVIC_ISER   (MCCI_CM0PLUS_NVIC + 0x000)

Definition at line 85 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_NVIC_ISPR

#define MCCI_CM0PLUS_NVIC_ISPR   (MCCI_CM0PLUS_NVIC + 0x100)

Definition at line 87 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_PRI_INDEX_PENDSV

#define MCCI_CM0PLUS_PRI_INDEX_PENDSV   UINT32_C(14)

priority of systick

Definition at line 218 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_PRI_INDEX_SVC

#define MCCI_CM0PLUS_PRI_INDEX_SVC   UINT32_C(11)

priority of systick

Definition at line 217 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_PRI_INDEX_SYSTICK

#define MCCI_CM0PLUS_PRI_INDEX_SYSTICK   UINT32_C(15)

priority of systick

Definition at line 219 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB

#define MCCI_CM0PLUS_SCB   UINT32_C(0xE000ED00)

Definition at line 101 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_AIRCR

#define MCCI_CM0PLUS_SCB_AIRCR   (MCCI_CM0PLUS_SCB + 0x0C)

Definition at line 105 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_AIRCR_ENDIANNESS

#define MCCI_CM0PLUS_SCB_AIRCR_ENDIANNESS   (UINT32_C(1) << 15)

Definition at line 195 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_AIRCR_SYSRESETREQ

#define MCCI_CM0PLUS_SCB_AIRCR_SYSRESETREQ   (UINT32_C(1) << 2)

Definition at line 196 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_AIRCR_VECTCLRACTIVE

#define MCCI_CM0PLUS_SCB_AIRCR_VECTCLRACTIVE   (UINT32_C(1) << 1)

Definition at line 197 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_AIRCR_VECTKEY

#define MCCI_CM0PLUS_SCB_AIRCR_VECTKEY   (UINT32_C(0xFFFF) << 16)

Vector key.

Definition at line 193 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_AIRCR_VECTKEY_VALUE

#define MCCI_CM0PLUS_SCB_AIRCR_VECTKEY_VALUE   (UINT32_C(0x05FA) << 16)

Value to write to unlock regster.

Definition at line 194 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_CCR

#define MCCI_CM0PLUS_SCB_CCR   (MCCI_CM0PLUS_SCB + 0x14)

Definition at line 107 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_CCR_STKALIGN

#define MCCI_CM0PLUS_SCB_CCR_STKALIGN   (UINT32_C(1) << 9)

Definition at line 209 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_CCR_UNALIGNED

#define MCCI_CM0PLUS_SCB_CCR_UNALIGNED   (UINT32_C(1) << 3)

Definition at line 210 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_CPUID

#define MCCI_CM0PLUS_SCB_CPUID   (MCCI_CM0PLUS_SCB + 0x00)

Definition at line 102 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_CPUID_ARCHITECTURE

#define MCCI_CM0PLUS_SCB_CPUID_ARCHITECTURE   (UINT32_C(0xF) << 16)

Architecture code.

Definition at line 166 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_CPUID_IMPLEMENTER

#define MCCI_CM0PLUS_SCB_CPUID_IMPLEMENTER   (UINT32_C(0xFF) << 24)

Implementer code.

Definition at line 164 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_CPUID_PARTNO

#define MCCI_CM0PLUS_SCB_CPUID_PARTNO   (UINT32_C(0xFFF) << 4)

Part number.

Definition at line 167 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_CPUID_REVISION

#define MCCI_CM0PLUS_SCB_CPUID_REVISION   (UINT32_C(0xF) << 0)

Revision.

Definition at line 168 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_CPUID_VARIANT

#define MCCI_CM0PLUS_SCB_CPUID_VARIANT   (UINT32_C(0xF) << 20)

Variant code.

Definition at line 165 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_DFSR

#define MCCI_CM0PLUS_SCB_DFSR   (MCCI_CM0PLUS_SCB + 0x30)

Definition at line 111 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_ICSR

#define MCCI_CM0PLUS_SCB_ICSR   (MCCI_CM0PLUS_SCB + 0x04)

Definition at line 103 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_ICSR_ISRPENDING

#define MCCI_CM0PLUS_SCB_ICSR_ISRPENDING   (UINT32_C(1) << 22)

Definition at line 181 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_ICSR_ISRPREEMPT

#define MCCI_CM0PLUS_SCB_ICSR_ISRPREEMPT   (UINT32_C(1) << 23)

Definition at line 180 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_ICSR_NMIPENDSET

#define MCCI_CM0PLUS_SCB_ICSR_NMIPENDSET   (UINT32_C(1) << 31)

Definition at line 173 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_ICSR_PENDSTCLR

#define MCCI_CM0PLUS_SCB_ICSR_PENDSTCLR   (UINT32_C(1) << 26)

Definition at line 178 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_ICSR_PENDSTSET

#define MCCI_CM0PLUS_SCB_ICSR_PENDSTSET   (UINT32_C(1) << 26)

Definition at line 177 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_ICSR_PENDSVCLR

#define MCCI_CM0PLUS_SCB_ICSR_PENDSVCLR   (UINT32_C(1) << 27)

Definition at line 176 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_ICSR_PENDSVSET

#define MCCI_CM0PLUS_SCB_ICSR_PENDSVSET   (UINT32_C(1) << 28)

Definition at line 175 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_ICSR_RSV24

#define MCCI_CM0PLUS_SCB_ICSR_RSV24   (UINT32_C(1) << 24)

Definition at line 179 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_ICSR_RSV29

#define MCCI_CM0PLUS_SCB_ICSR_RSV29   (UINT32_C(3) << 29)

Definition at line 174 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_ICSR_VECTACTIVE

#define MCCI_CM0PLUS_SCB_ICSR_VECTACTIVE   (UINT32_C(0x1FF) << 0)

Definition at line 183 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_ICSR_VECTPENDING

#define MCCI_CM0PLUS_SCB_ICSR_VECTPENDING   (UINT32_C(0x1FF) << 12)

Definition at line 182 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_SCR

#define MCCI_CM0PLUS_SCB_SCR   (MCCI_CM0PLUS_SCB + 0x10)

Definition at line 106 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_SCR_SEVONPEND

#define MCCI_CM0PLUS_SCB_SCR_SEVONPEND   (UINT32_C(1) << 4)

Definition at line 202 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_SCR_SLEEPDEEP

#define MCCI_CM0PLUS_SCB_SCR_SLEEPDEEP   (UINT32_C(1) << 2)

Definition at line 203 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_SCR_SLEEPONEXIT

#define MCCI_CM0PLUS_SCB_SCR_SLEEPONEXIT   (UINT32_C(1) << 1)

Definition at line 204 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_SHCSR

#define MCCI_CM0PLUS_SCB_SHCSR   (MCCI_CM0PLUS_SCB + 0x24)

Definition at line 110 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_SHCSR_SVCALLPENDED

#define MCCI_CM0PLUS_SCB_SHCSR_SVCALLPENDED   (UINT32_C(1) << 15)

Definition at line 244 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_SHPR2

#define MCCI_CM0PLUS_SCB_SHPR2   (MCCI_CM0PLUS_SCB + 0x1C)

Definition at line 108 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_SHPR3

#define MCCI_CM0PLUS_SCB_SHPR3   (MCCI_CM0PLUS_SCB + 0x20)

Definition at line 109 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_SHPR_PRI

#define MCCI_CM0PLUS_SCB_SHPR_PRI   (UINT32_C(3) << 6)

priority bits within a byte

Definition at line 215 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_VTOR

#define MCCI_CM0PLUS_SCB_VTOR   (MCCI_CM0PLUS_SCB + 0x08)

Definition at line 104 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCB_VTOR_TBLOFF

#define MCCI_CM0PLUS_SCB_VTOR_TBLOFF   UINT32_C(0xFFFFFF00)

Definition at line 188 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SCS_BASE

#define MCCI_CM0PLUS_SCS_BASE   UINT32_C(0xE000E000)

Definition at line 71 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SR_PRIMASK_DISABLE

#define MCCI_CM0PLUS_SR_PRIMASK_DISABLE   (UINT32_C(1) << 0)

the bit to disable interrupts

Definition at line 59 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSM_APSR

#define MCCI_CM0PLUS_SYSM_APSR   UINT32_C(0x00)

Flags from previous instructions.

Definition at line 45 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSM_CONTROL

#define MCCI_CM0PLUS_SYSM_CONTROL   UINT32_C(0x14)

control register

Definition at line 55 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSM_EAPSR

#define MCCI_CM0PLUS_SYSM_EAPSR   UINT32_C(0x02)

Composite of EPSR and APSR.

Definition at line 47 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSM_EPSR

#define MCCI_CM0PLUS_SYSM_EPSR   UINT32_C(0x06)

Exception status register.

Definition at line 50 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSM_IAPSR

#define MCCI_CM0PLUS_SYSM_IAPSR   UINT32_C(0x01)

Composite of IPSR and APSR.

Definition at line 46 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSM_IEPSR

#define MCCI_CM0PLUS_SYSM_IEPSR   UINT32_C(0x07)

Composite of IPSR and EPSR.

Definition at line 51 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSM_IPSR

#define MCCI_CM0PLUS_SYSM_IPSR   UINT32_C(0x05)

Interrupt status register.

Definition at line 49 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSM_MSP

#define MCCI_CM0PLUS_SYSM_MSP   UINT32_C(0x08)

Main stack pointer.

Definition at line 52 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSM_PRIMASK

#define MCCI_CM0PLUS_SYSM_PRIMASK   UINT32_C(0x10)

priority mask register

Definition at line 54 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSM_PSP

#define MCCI_CM0PLUS_SYSM_PSP   UINT32_C(0x09)

Process stack pointer.

Definition at line 53 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSM_XPSR

#define MCCI_CM0PLUS_SYSM_XPSR   UINT32_C(0x03)

Composite of EPSR, IPSR and APSR.

Definition at line 48 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSTICK

#define MCCI_CM0PLUS_SYSTICK   UINT32_C(0xE000E010)

Definition at line 75 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSTICK_CALIB

#define MCCI_CM0PLUS_SYSTICK_CALIB   (MCCI_CM0PLUS_SYSTICK + 0xC)

Definition at line 79 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSTICK_CALIB_NOREF

#define MCCI_CM0PLUS_SYSTICK_CALIB_NOREF   (UINT32_C(1) << 31)

reference clock is not implemented

Definition at line 154 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSTICK_CALIB_RSV24

#define MCCI_CM0PLUS_SYSTICK_CALIB_RSV24   (UINT32_C(0x3F) << 24)

reserved, zero

Definition at line 156 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSTICK_CALIB_SKEW

#define MCCI_CM0PLUS_SYSTICK_CALIB_SKEW   (UINT32_C(1) << 30)

10ms cal value is inexact

Definition at line 155 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSTICK_CALIB_TENMS

#define MCCI_CM0PLUS_SYSTICK_CALIB_TENMS   UINT32_C(0x00FFFFFF)

if non-zero, use this as reload value for 10ms ticks

Definition at line 157 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSTICK_CSR

#define MCCI_CM0PLUS_SYSTICK_CSR   (MCCI_CM0PLUS_SYSTICK + 0x0)

Definition at line 76 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSTICK_CSR_CLKSOURCE

#define MCCI_CM0PLUS_SYSTICK_CSR_CLKSOURCE   (UINT32_C(1) << 2)

use processor (not external) clock

Definition at line 135 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSTICK_CSR_COUNTFLAG

#define MCCI_CM0PLUS_SYSTICK_CSR_COUNTFLAG   (UINT32_C(1) << 16)

timer has counted to zero

Definition at line 133 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSTICK_CSR_ENABLE

#define MCCI_CM0PLUS_SYSTICK_CSR_ENABLE   (UINT32_C(1) << 0)

enable counter

Definition at line 137 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSTICK_CSR_RSV17

#define MCCI_CM0PLUS_SYSTICK_CSR_RSV17   UINT32_C(0xFFFE0000)

reserved

Definition at line 132 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSTICK_CSR_RSV3

#define MCCI_CM0PLUS_SYSTICK_CSR_RSV3   UINT32_C(0x0000FFF8)

reserved

Definition at line 134 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSTICK_CSR_TICKINT

#define MCCI_CM0PLUS_SYSTICK_CSR_TICKINT   (UINT32_C(1) << 1)

enable tick exception

Definition at line 136 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSTICK_CVR

#define MCCI_CM0PLUS_SYSTICK_CVR   (MCCI_CM0PLUS_SYSTICK + 0x8)

Definition at line 78 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSTICK_CVR_CURRENT

#define MCCI_CM0PLUS_SYSTICK_CVR_CURRENT   UINT32_C(0x00FFFFFF)

current value

Definition at line 149 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSTICK_CVR_RSV24

#define MCCI_CM0PLUS_SYSTICK_CVR_RSV24   UINT32_C(0xFF000000)

reserved, read as zero

Definition at line 148 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSTICK_RVR

#define MCCI_CM0PLUS_SYSTICK_RVR   (MCCI_CM0PLUS_SYSTICK + 0x4)

Definition at line 77 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSTICK_RVR_RELOAD

#define MCCI_CM0PLUS_SYSTICK_RVR_RELOAD   UINT32_C(0x00FFFFFF)

reload value

Definition at line 143 of file mcci_arm_cm0plus.h.

◆ MCCI_CM0PLUS_SYSTICK_RVR_RSV24

#define MCCI_CM0PLUS_SYSTICK_RVR_RSV24   UINT32_C(0xFF000000)

reserved, zero

Definition at line 142 of file mcci_arm_cm0plus.h.

Function Documentation

◆ McciArm_getReg()

static uint32_t McciArm_getReg ( uint32_t  reg)
inlinestatic

read a 32-bit value from a cm0plus register

Definition at line 265 of file mcci_arm_cm0plus.h.

Referenced by delayTick(), McciArm_putRegAndOr(), McciArm_putRegClear(), McciArm_putRegClearSet(), McciArm_putRegMasked(), McciArm_putRegOr(), McciBootloader_Stm32L0_prepareForLaunch(), McciBootloader_Stm32L0_programHalfPage(), McciBootloader_Stm32L0_systemFlashErase(), McciBootloader_Stm32L0_systemFlashWrite(), McciBootloader_Stm32L0_systemInit(), McciBootloaderBoard_CatenaAbz_delayMs(), McciBootloaderBoard_CatenaAbz_setUpdate(), and McciBootloaderBoard_CatenaAbz_spiTransfer().

◆ McciArm_putReg()

static uint32_t McciArm_putReg ( uint32_t  reg,
uint32_t  val 
)
inlinestatic

write a 32-bit value to a cm0plus register

Definition at line 256 of file mcci_arm_cm0plus.h.

Referenced by McciArm_putRegAndOr(), McciArm_putRegClear(), McciArm_putRegClearSet(), McciArm_putRegMasked(), McciArm_putRegOr(), McciBootloader_Stm32L0_prepareForLaunch(), McciBootloader_Stm32L0_programHalfPage(), McciBootloader_Stm32L0_systemFlashErase(), McciBootloader_Stm32L0_systemFlashWrite(), McciBootloader_Stm32L0_systemInit(), McciBootloaderBoard_CatenaAbz_clearLed(), McciBootloaderBoard_CatenaAbz_setLed(), McciBootloaderBoard_CatenaAbz_setUpdate(), McciBootloaderBoard_CatenaAbz_spiTransfer(), and McciBootloaderPlatform_startApp().

◆ McciArm_putRegAndOr()

static uint32_t McciArm_putRegAndOr ( uint32_t  reg,
uint32_t  andVal,
uint32_t  orVal 
)
inlinestatic

and/or 32-bit values to a cm0plus register

Definition at line 273 of file mcci_arm_cm0plus.h.

References McciArm_getReg(), and McciArm_putReg().

◆ McciArm_putRegClear()

static uint32_t McciArm_putRegClear ( uint32_t  reg,
uint32_t  clearVal 
)
inlinestatic

clear out 32-bit values to a cm0plus register

Definition at line 299 of file mcci_arm_cm0plus.h.

References McciArm_getReg(), and McciArm_putReg().

Referenced by McciBootloader_Stm32L0_prepareForLaunch(), McciBootloader_Stm32L0_programHalfPage(), McciBootloader_Stm32L0_systemFlashErase(), McciBootloader_Stm32L0_systemInit(), McciBootloaderBoard_CatenaAbz_spiInit(), and McciBootloaderBoard_CatenaAbz_spiTransfer().

◆ McciArm_putRegClearSet()

static uint32_t McciArm_putRegClearSet ( uint32_t  reg,
uint32_t  clearVal,
uint32_t  setVal 
)
inlinestatic

clear and set 32-bit values to a cm0plus register

Parameters
[in]regregister to be modified
[in]clearValmask of bits to be cleared (1 in mask clears bit in reg)
[in]setValmask of bits to be set
Note
this is subtly different than McciArm_putRegMasked, in that setVal is not modified by clearVal. Any bits set in setVal are unconditionally set in reg, whereas McciArm_putRegMasked only changes bits that are set in its maskVal parameter.
See also
McciArm_putRegMasked

Definition at line 326 of file mcci_arm_cm0plus.h.

References McciArm_getReg(), and McciArm_putReg().

◆ McciArm_putRegMasked()

static uint32_t McciArm_putRegMasked ( uint32_t  reg,
uint32_t  maskVal,
uint32_t  modVal 
)
inlinestatic

store to cm0plus register under mask

Parameters
[in]regregister to be modified
[in]maskValmask of bits to be modifed
[in]modValwhere maskVal is 1, provides values of bits
Note
this is subtly different than McciArm_putRegClearSet, in that any bits in ~maskVal are not changed, regardless of corresponding bits in modVal.
See also
McciArm_putRegClearSet
https://graphics.stanford.edu/~seander/bithacks.html#MaskedMerge

Definition at line 352 of file mcci_arm_cm0plus.h.

References McciArm_getReg(), and McciArm_putReg().

Referenced by McciBootloader_Stm32L0_prepareForLaunch(), McciBootloader_Stm32L0_systemInit(), McciBootloaderBoard_CatenaAbz_fail(), McciBootloaderBoard_CatenaAbz_spiInit(), and storagePowerOn().

◆ McciArm_putRegOr()

static uint32_t McciArm_putRegOr ( uint32_t  reg,
uint32_t  orVal 
)
inlinestatic

or 32-bit values to a cm0plus register

Definition at line 286 of file mcci_arm_cm0plus.h.

References McciArm_getReg(), and McciArm_putReg().

Referenced by McciBootloader_Stm32L0_prepareForLaunch(), McciBootloader_Stm32L0_programHalfPage(), McciBootloader_Stm32L0_systemFlashErase(), McciBootloader_Stm32L0_systemFlashWrite(), McciBootloader_Stm32L0_systemInit(), McciBootloaderBoard_CatenaAbz_setUpdate(), McciBootloaderBoard_CatenaAbz_spiInit(), McciBootloaderBoard_CatenaAbz_spiTransfer(), and storagePowerOn().

◆ McciCm0Plus_SCB_SHPR_getMask()

static uint32_t McciCm0Plus_SCB_SHPR_getMask ( uint32_t  handlerIndex)
inlinestatic

return byte mask for a given handler index

Definition at line 233 of file mcci_arm_cm0plus.h.

Referenced by McciBootloader_Stm32L0_systemInit().

◆ McciCm0Plus_SCB_SHPR_getRegister()

static uint32_t McciCm0Plus_SCB_SHPR_getRegister ( uint32_t  handlerIndex)
inlinestatic

return register for a given handler index

Definition at line 223 of file mcci_arm_cm0plus.h.

References MCCI_CM0PLUS_SCB_SHPR2.

Referenced by McciBootloader_Stm32L0_systemInit().