MCCI Trusted Bootloader
Simple trusted bootloader and tools for small embedded systems
mcci_stm32l0xx.h
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/*
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Module: mcci_stm32l0xx.h
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Function:
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Register definitions for STM32L0xx CPUs
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Copyright and License:
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This file copyright (C) 2021 by
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MCCI Corporation
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3520 Krums Corners Road
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Ithaca, NY 14850
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See accompanying LICENSE file for copyright and license information.
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Author:
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Terry Moore, MCCI Corporation March 2021
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*/
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#ifndef _mcci_stm32l0xx_h_
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#define _mcci_stm32l0xx_h_
/* prevent multiple includes */
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#pragma once
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#ifndef _mcci_bootloader_bits_h_
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# include "
mcci_bootloader_bits.h
"
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#endif
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#ifndef _mcci_arm_cm0plus_h_
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# include "
mcci_arm_cm0plus.h
"
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#endif
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#include <stdint.h>
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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/****************************************************************************\
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|
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| Register addresses
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|
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\****************************************************************************/
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/// \name STM32L0xx top-level address breakdown
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/// @{
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#define MCCI_STM32L0_MEMORY_FLASH UINT32_C(0x08000000)
///< Flash program memory (up to 192K)
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#define MCCI_STM32L0_MEMORY_EEPROM UINT32_C(0x08080000)
///< Data EEPROM (up to 6K)
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#define MCCI_STM32L0_MEMORY_SYSTEM UINT32_C(0x1FF00000)
///< System memory (8K)
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#define MCCI_STM32L0_OPTIONS_USER UINT32_C(0x1FF80000)
///< User option bytes (32)
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#define MCCI_STM32L0_OPTIONS_FACTORY UINT32_C(0x1FF80020)
///< Factory option bytes (96)
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#define MCCI_STM32L0_MEMORY_SRAM UINT32_C(0x20000000)
///< SRAM (up to 20K)
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#define MCCI_STM32L0_REG_TIMER2 UINT32_C(0x40000000)
///< Section 20.5: TIMx register map (1K)
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#define MCCI_STM32L0_REG_TIMER3 UINT32_C(0x40000400)
///< Section 20.5: TIMx register map (1K)
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#define MCCI_STM32L0_REG_TIMER6 UINT32_C(0x40001000)
///< Section 22.4.9: TIM6/7 register map (1K)
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#define MCCI_STM32L0_REG_TIMER7 UINT32_C(0x40001400)
///< Section 22.4.9: TIM6/7 register map (1K)
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#define MCCI_STM32L0_REG_RTC UINT32_C(0x40002800)
///< Section 26.7.21: RTC + BKUP register map (1K)
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#define MCCI_STM32L0_REG_WWDG UINT32_C(0x40002C00)
///< Section 25.4.4: WWDG register map (1K)
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#define MCCI_STM32L0_REG_IWDG UINT32_C(0x40003000)
///< Section 24.4.6: IWDG register map (1K)
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#define MCCI_STM32L0_REG_SPI2 UINT32_C(0x40003800)
///< Section 30.7.10: SPI register map (1K)
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#define MCCI_STM32L0_REG_USART2 UINT32_C(0x40004400)
///< Section 28.8.12: USART register map (1K)
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#define MCCI_STM32L0_REG_LPUART1 UINT32_C(0x40004800)
///< Section 29.7.10: LPUART register map (1K)
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#define MCCI_STM32L0_REG_USART4 UINT32_C(0x40004C00)
///< Section 28.8.12: USART register map (1K)
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#define MCCI_STM32L0_REG_USART5 UINT32_C(0x40005000)
///< Section 28.8.12: USART register map (1K)
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#define MCCI_STM32L0_REG_I2C1 UINT32_C(0x40005400)
///< Section 27.7.12: I2C register map (1K)
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#define MCCI_STM32L0_REG_I2C2 UINT32_C(0x40005800)
///< Section 27.7.12: I2C register map (1K)
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#define MCCI_STM32L0_REG_USB_FS UINT32_C(0x40005C00)
///< Section 31.6.3: USB register map (1K)
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#define MCCI_STM32L0_REG_USB_SRAM UINT32_C(0x40006000)
///< USB (SRAM 512x16bit) (2K)
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#define MCCI_STM32L0_REG_CRS UINT32_C(0x40006C00)
///< Section 8.6.5: CRS register map (1K)
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#define MCCI_STM32L0_REG_PWR UINT32_C(0x40007000)
///< Section 6.4.3: PWR register map (1K)
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#define MCCI_STM32L0_REG_DAC1 UINT32_C(0x40007400)
///< Section 15.10.15: DAC register map (1K)
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#define MCCI_STM32L0_REG_I2C3 UINT32_C(0x40007800)
///< Section 27.7.12: I2C register map (1K)
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#define MCCI_STM32L0_REG_LPTIM1 UINT32_C(0x40007C00)
///< Section 23.6.9: LPTIM register map (1K)
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#define MCCI_STM32L0_REG_SYSCFG_COMP UINT32_C(0x40010000)
///< Section 10.2.8: SYSCFG register map, Section 16.5.3: COMP register map (1K)
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#define MCCI_STM32L0_REG_EXTI UINT32_C(0x40010400)
///< Section 13.5.7: EXTI register map (1K)
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#define MCCI_STM32L0_REG_TIM21 UINT32_C(0x40010800)
///< Section 21.4.16: TIM21/22 register map (1K)
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#define MCCI_STM32L0_REG_TIM22 UINT32_C(0x40011400)
///< Section 21.4.16: TIM21/22 register map (1K)
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#define MCCI_STM32L0_REG_FIREWALL UINT32_C(0x40011C00)
///< Section 5.4.8: Firewall register map (1K)
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#define MCCI_STM32L0_REG_ADC1 UINT32_C(0x40012400)
///< Section 14.12.12: ADC register map (1K)
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#define MCCI_STM32L0_REG_SPI1 UINT32_C(0x40013000)
///< Section 30.7.10: SPI register map (1K)
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#define MCCI_STM32L0_REG_USART1 UINT32_C(0x40013800)
///< Section 28.8.12: USART register map (1K)
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#define MCCI_STM32L0_REG_DBG UINT32_C(0x40015800)
///< Section 32.10: DBG register map (1K)
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#define MCCI_STM32L0_REG_DMA1 UINT32_C(0x40020000)
///< Section 11.4.8: DMA register map (1K)
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#define MCCI_STM32L0_REG_RCC UINT32_C(0x40021000)
///< Section 7.3.22: RCC register map (1K)
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#define MCCI_STM32L0_REG_FLASH UINT32_C(0x40022000)
///< Section 3.7.11: Flash register map (1K)
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#define MCCI_STM32L0_REG_CRC UINT32_C(0x40023000)
///< Section 4.4.6: CRC register map (1K)
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#define MCCI_STM32L0_REG_TSC UINT32_C(0x40024000)
///< Section 17.6.11: TSC register map (1K)
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#define MCCI_STM32L0_REG_RNG UINT32_C(0x40025000)
///< Section 19.8.4: RNG register map (1K)
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#define MCCI_STM32L0_REG_AES UINT32_C(0x40026000)
///< Section 18.12.13: AES register map (1K)
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#define MCCI_STM32L0_REG_GPIOA UINT32_C(0x50000000)
///< Section 9.4.12: GPIO register map (1K)
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#define MCCI_STM32L0_REG_GPIOB UINT32_C(0x50000400)
///< Section 9.4.12: GPIO register map (1K)
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#define MCCI_STM32L0_REG_GPIOC UINT32_C(0x50000800)
///< Section 9.4.12: GPIO register map (1K)
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#define MCCI_STM32L0_REG_GPIOD UINT32_C(0x50000C00)
///< Section 9.4.12: GPIO register map (1K)
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#define MCCI_STM32L0_REG_GPIOE UINT32_C(0x50001000)
///< Section 9.4.12: GPIO register map (1K)
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#define MCCI_STM32L0_REG_GPIOH UINT32_C(0x50001C00)
///< Section 9.4.12: GPIO register map (1K)
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/// @}
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/****************************************************************************\
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| Option bytes, etc
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\****************************************************************************/
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/// \name User option bytes
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/// @{
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#define MCCI_STM32L0_OPTIONS_USER_FLASH_OPTR_LOW (MCCI_STM32L0_OPTIONS_USER + 0x00)
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#define MCCI_STM32L0_OPTIONS_USER_FLASH_OPTR_HIGH (MCCI_STM32L0_OPTIONS_USER + 0x04)
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#define MCCI_STM32L0_OPTIONS_USER_FLASH_WRPROT1_LOW (MCCI_STM32L0_OPTIONS_USER + 0x08)
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#define MCCI_STM32L0_OPTIONS_USER_FLASH_WRPROT1_HIGH (MCCI_STM32L0_OPTIONS_USER + 0x0C)
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#define MCCI_STM32L0_OPTIONS_USER_FLASH_WRPROT2 (MCCI_STM32L0_OPTIONS_USER + 0x10)
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/// \brief create an option dword from a 16-bit value (high 16 bits inverted copy of low)
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#define MCCI_STM32L0_OPTIONS_MAKE_DWORD(v) ((~(uint32_t)(v) << 16) | (uint16_t)(v))
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/// @}
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/// \name System values in system option memory
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/// @{
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#define MCCI_STM32L0_OPTIONS_SYSTEM_FLASH_SIZE_16 UINT32_C(0x1FF8007C)
///< memory size in k bytes (16 bits)
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/// \brief convert flash_size_16 value to bytes
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#define MCCI_STM32L0_OPTIONS_SYSTEM_FLASH_SIZE_TO_BYTES(h) \
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(((h) & UINT32_C(0xFFFF)) * 1024)
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#define MCCI_STM32L0_OPTIONS_U_ID_0 UINT32_C(0x1FF80050)
///< register address: unique ID bits 31:0
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#define MCCI_STM32L0_OPTIONS_U_ID_4 (MCCI_STM32L0_OPTIONS_U_ID_0 + 0x04)
///< register address: unique ID bits 63:32
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#define MCCI_STM32L0_OPTIONS_U_ID_8 (MCCI_STM32L0_OPTIONS_U_ID_0 + 0x014)
///< register address: unique ID bits 95:64
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/// @}
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/****************************************************************************\
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| Flash Control Registers (3.7)
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\****************************************************************************/
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/// \name FLASH registers
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/// @{
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#define MCCI_STM32L0_REG_FLASH_ACR (MCCI_STM32L0_REG_FLASH + 0x00)
///< Flash access control register
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#define MCCI_STM32L0_REG_FLASH_PECR (MCCI_STM32L0_REG_FLASH + 0x04)
///< Flash program and erase control register
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#define MCCI_STM32L0_REG_FLASH_PDKEYR (MCCI_STM32L0_REG_FLASH + 0x08)
///< Flash power-down key register
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#define MCCI_STM32L0_REG_FLASH_PEKEYR (MCCI_STM32L0_REG_FLASH + 0x0C)
///< Flash PECR unlock key register
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#define MCCI_STM32L0_REG_FLASH_PRGKEYR (MCCI_STM32L0_REG_FLASH + 0x10)
///< Flash program/erase key register
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#define MCCI_STM32L0_REG_FLASH_OPTKEYR (MCCI_STM32L0_REG_FLASH + 0x14)
///< Flash option bytes unlock key register
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#define MCCI_STM32L0_REG_FLASH_SR (MCCI_STM32L0_REG_FLASH + 0x18)
///< Flash status register
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#define MCCI_STM32L0_REG_FLASH_OPTR (MCCI_STM32L0_REG_FLASH + 0x1C)
///< Flash option bytes register
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#define MCCI_STM32L0_REG_FLASH_WPROT1 (MCCI_STM32L0_REG_FLASH + 0x20)
///< Flash write proection register 1
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#define MCCI_STM32L0_REG_FLASH_WPROT2 (MCCI_STM32L0_REG_FLASH + 0x80)
///< Flash write protection register 2
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/// @}
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/// \name FLASH_ACR bits
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/// @{
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#define MCCI_STM32L0_REG_FLASH_ACR_RSV7 UINT32_C(0xFFFFFF80)
///< Reserved, don't change
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#define MCCI_STM32L0_REG_FLASH_ACR_PRE_READ (UINT32_C(1) << 6)
///< Enable pre-read
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#define MCCI_STM32L0_REG_FLASH_ACR_DISAB_BUF (UINT32_C(1) << 5)
///< Disable read buffer
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#define MCCI_STM32L0_REG_FLASH_ACR_RUN_PD (UINT32_C(1) << 4)
///< power-down in run mode
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#define MCCI_STM32L0_REG_FLASH_ACR_SLEEP_PD (UINT32_C(1) << 3)
///< power-down in sleep mode
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#define MCCI_STM32L0_REG_FLASH_ACR_RSV2 (UINT32_C(1) << 2)
///< Reserved, don't change
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#define MCCI_STM32L0_REG_FLASH_ACR_PRFTEN (UINT32_C(1) << 1)
///< prefetch enable
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#define MCCI_STM32L0_REG_FLASH_ACR_LATENCY (UINT32_C(1) << 0)
///< NVM latency: 1 wait state (not zero wait state)
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/// @}
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/// \name FLASH_PECR bits
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/// @{
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#define MCCI_STM32L0_REG_FLASH_PECR_RSV24 UINT32_C(0xFF000000)
///< Reserved, don't change
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#define MCCI_STM32L0_REG_FLASH_PECR_NZDISABLE (UINT32_C(1) << 23)
///< Disable non-zero check
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#define MCCI_STM32L0_REG_FLASH_PECR_RSV19 (UINT32_C(0xF) << 19)
///< Reserved, don't change
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#define MCCI_STM32L0_REG_FLASH_PECR_OBL_LAUNCH (UINT32_C(1) << 18)
///< Reload option bytes and reset system
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#define MCCI_STM32L0_REG_FLASH_PECR_ERRIE (UINT32_C(1) << 17)
///< Error interrupt enable
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#define MCCI_STM32L0_REG_FLASH_PECR_EOPIE (UINT32_C(1) << 16)
///< End of programming interrupt enable
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#define MCCI_STM32L0_REG_FLASH_PECR_PARALLELBANK (UINT32_C(1) << 15)
///< Parallel bank programming enable
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#define MCCI_STM32L0_REG_FLASH_PECR_RSV11 (UINT32_C(0xF) << 11)
///< Reserved, don't change
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#define MCCI_STM32L0_REG_FLASH_PECR_FPRG (UINT32_C(1) << 10)
///< Enable half-page programming mode
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#define MCCI_STM32L0_REG_FLASH_PECR_ERASE (UINT32_C(1) << 9)
///< Erase operation requested/not requested
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#define MCCI_STM32L0_REG_FLASH_PECR_FIX (UINT32_C(1) << 8)
///< Atomatically erase before programming EEPROM and options
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#define MCCI_STM32L0_REG_FLASH_PECR_RSV5 (UINT32_C(7) << 5)
///< Reserved, don't change
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#define MCCI_STM32L0_REG_FLASH_PECR_DATA (UINT32_C(1) << 4)
///< Select data memory
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#define MCCI_STM32L0_REG_FLASH_PECR_PROG (UINT32_C(1) << 3)
///< Select program memory
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#define MCCI_STM32L0_REG_FLASH_PECR_OPTLOCK (UINT32_C(1) << 2)
///< Lock option bytes
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#define MCCI_STM32L0_REG_FLASH_PECR_PRGLOCK (UINT32_C(1) << 1)
///< Lock program memory
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#define MCCI_STM32L0_REG_FLASH_PECR_PELOCK (UINT32_C(1) << 0)
///< Lock the FLASH_PECR register
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/// @}
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/// \name FLASH_PDKEYR bits
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/// @{
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#define MCCI_STM32L0_REG_FLASH_PDKEYR_UNLOCK1 UINT32_C(0x04152637)
///< unlock word 1 for RUN_PD
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#define MCCI_STM32L0_REG_FLASH_PDKEYR_UNLOCK2 UINT32_C(0xFAFBFCFD)
///< unlock word 2 for RUN_PD
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/// @}
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/// \name FLASH_PEKEYR bits
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/// @{
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#define MCCI_STM32L0_REG_FLASH_PEKEYR_UNLOCK1 UINT32_C(0x89ABCDEF)
///< unlock word 1 for PECR
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#define MCCI_STM32L0_REG_FLASH_PEKEYR_UNLOCK2 UINT32_C(0x02030405)
///< unlock word 2 for PECR
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/// @}
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/// \name FLASH_PRGKEYR bits
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/// @{
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#define MCCI_STM32L0_REG_FLASH_PRGKEYR_UNLOCK1 UINT32_C(0x8C9DAEBF)
///< unlock word 1 for PRGKEYR
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#define MCCI_STM32L0_REG_FLASH_PRGKEYR_UNLOCK2 UINT32_C(0x13141516)
///< unlock word 2 for PRGKEYR
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/// @}
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/// \name FLASH_OPTKEYR bits
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/// @{
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#define MCCI_STM32L0_REG_FLASH_OPTKEYR_UNLOCK1 UINT32_C(0xFBEAD9C8)
///< unlock word 1 for option bytes
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#define MCCI_STM32L0_REG_FLASH_OPTKEYR_UNLOCK2 UINT32_C(0x24252627)
///< unlock word 2 for option bytes
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/// @}
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/// \name FLASH_SR bits
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/// @{
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#define MCCI_STM32L0_REG_FLASH_SR_RSV18 UINT32_C(0xFFFC0000)
///< Reserved, don't change.
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#define MCCI_STM32L0_REG_FLASH_SR_FWWERR (UINT32_C(1) << 17)
///< Write/erase aborted for fetch.
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#define MCCI_STM32L0_REG_FLASH_SR_NOTZEROERR (UINT32_C(1) << 16)
///< Attempt to program non-zero area
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#define MCCI_STM32L0_REG_FLASH_SR_RSV14 (UINT32_C(3) << 14)
///< Reserved, don't change.
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#define MCCI_STM32L0_REG_FLASH_SR_RDERR (UINT32_C(1) << 13)
///< Read-protection error
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#define MCCI_STM32L0_REG_FLASH_SR_RSV12 (UINT32_C(1) << 12)
///< Reserved, don't change.
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#define MCCI_STM32L0_REG_FLASH_SR_OPTVERR (UINT32_C(1) << 11)
///< Option valid error
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#define MCCI_STM32L0_REG_FLASH_SR_SIZERR (UINT32_C(1) << 10)
///< Size error when programming
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#define MCCI_STM32L0_REG_FLASH_SR_PGAERR (UINT32_C(1) << 9)
///< Programming alignment error
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#define MCCI_STM32L0_REG_FLASH_SR_WRPERR (UINT32_C(1) << 8)
///< write protection error.
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#define MCCI_STM32L0_REG_FLASH_SR_RSV4 (UINT32_C(0xF) << 4)
///< Reserved, don't change.
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#define MCCI_STM32L0_REG_FLASH_SR_READY (UINT32_C(1) << 3)
///< NVM is ready
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#define MCCI_STM32L0_REG_FLASH_SR_ENDHV (UINT32_C(1) << 2)
///< High voltage is off (not on), not active
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#define MCCI_STM32L0_REG_FLASH_SR_EOP (UINT32_C(1) << 1)
///< End of program
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#define MCCI_STM32L0_REG_FLASH_SR_BSY (UINT32_C(1) << 0)
///< Busy doing write/erase
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/// @}
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/// \name FLASH_OPTR bits
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/// @{
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#define MCCI_STM32L0_REG_FLASH_OPTR_nBOOT1 (UINT32_C(1) << 31)
///< If boot0, boot from system rom (not RAM)
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#define MCCI_STM32L0_REG_FLASH_OPTR_RSV24 (UINT32_C(0x7F) << 24)
///< Reserved, don't change
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#define MCCI_STM32L0_REG_FLASH_OPTR_BFB2 (UINT32_C(1) << 23)
///< Boot from system memory (not bank 2)
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#define MCCI_STM32L0_REG_FLASH_OPTR_nRST_STDBY (UINT32_C(1) << 22)
///< do not generate reset when entering standby
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#define MCCI_STM32L0_REG_FLASH_OPTR_nRST_STOP (UINT32_C(1) << 21)
///< do not generate reset when entering stop
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#define MCCI_STM32L0_REG_FLASH_OPTR_WDG_SW (UINT32_C(1) << 20)
///< software (not hardware) watchdog
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#define MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV (UINT32_C(0xF) << 16)
///< brown-out reset level
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#define MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV_1v8 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV, 8)
///< Level 1 (1.8 V)
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#define MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV_2v0 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV, 9)
///< Level 2 (2.0 V)
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#define MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV_2v5 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV, 10)
///< Level 3 (2.5 V)
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#define MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV_2v7 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV, 11)
///< Level 4 (2.7 V)
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#define MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV_3v0 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV, 12)
///< Level 5 (3.0 V)
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#define MCCI_STM32L0_REG_FLASH_OPTR_RSV9 (UINT32_C(0x7F) << 9)
///< Reserved, don't change
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#define MCCI_STM32L0_REG_FLASH_OPTR_WPRMOD (UINT32_C(1) << 8)
///< PCROP enabled (use WPROT for read protection)
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#define MCCI_STM32L0_REG_FLASH_OPTR_RDPROT (UINT32_C(0xFF) << 0)
///< Read protection level
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#define MCCI_STM32L0_REG_FLASH_OPTR_RDPROT_L0 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_RDPROT, 0xAA)
//< level 0
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#define MCCI_STM32L0_REG_FLASH_OPTR_RDPROT_L2 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_RDPROT, 0xCC)
//< level 2
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#define MCCI_STM32L0_REG_FLASH_OPTR_RDPROT_L1 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_RDPROT, 0x0)
//< level 2
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/// \brief given image of FLASH_OPTR, return true if set for level 0 protection
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#define MCCI_STM32L0_FLASH_OPTR_RDPROT_IS_L0(v) \
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((v) & MCCI_STM32L0_REG_FLASH_OPTR_RDPROT) == MCCI_STM32L0_REG_FLASH_OPTR_RDPROT_L0)
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/// \brief given image of FLASH_OPTR, return true if set for level 2 protection
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#define MCCI_STM32L0_FLASH_OPTR_RDPROT_IS_L2(v) \
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((v) & MCCI_STM32L0_REG_FLASH_OPTR_RDPROT) == MCCI_STM32L0_REG_FLASH_OPTR_RDPROT_L0)
257
/// \brief given image of FLASH_OPTR, return true if set for level 1 protection
258
#define MCCI_STM32L0_FLASH_OPTR_RDPROT_IS_L1(v) \
259
(! (MCCI_STM32L0_FLASH_OPTR_RDPROT_IS_L0(v) || MCCI_STM32L0_FLASH_OPTR_RDPROT_IS_L2(v)))
260
/// @}
261
262
/// \name FLASH_WPROT1, FLASH_WPROT2 bits
263
/// @{
264
#define MCCI_STM32L0_FLASH_SECTOR_SIZE UINT32_C(4096)
///< size in bytes of a flash sector
265
/// \brief given a flash address, convert to sector number
266
#define MCCI_STM32L0_FLASH_ADDRESS_GET_SECTOR(a) \
267
(((uint32_t)(a) - MCCI_STM32L0_MEMORY_FLASH) >> MCCI_BOOTLOADER_FIELD_SHIFT(MCCI_STM32L0_FLASH_SECTOR_SIZE))
268
269
/// \brief get reg offset for protection bit for sector \p s
270
#define MCCI_STM32L0_REG_FLASH_WPROTx_FOR_SECTOR(s) ((s) < 32 ? MCCI_STM32L0_REG_FLASH_WPROT1 : MCCI_STM32L0_REG_FLASH_WPROT2)
271
272
/// \brief get mask for sector \p s.
273
#define MCCI_STM32L0_FLASH_WPROT_MASK_FOR_SECTOR(s) (UINT32_C(1) << ((s) & 0x1F))
274
/// @}
275
276
/// \name Flash programming constants
277
/// @{
278
#define MCCI_STM32L0_FLASH_HALF_PAGE_SIZE UINT32_C(64)
///< size in bytes of a half-page
279
#define MCCI_STM32L0_FLASH_PAGE_SIZE UINT32_C(128)
///< size in bytes of a page
280
/// @}
281
282
/****************************************************************************\
283
|
284
| Power Control Registers
285
|
286
\****************************************************************************/
287
288
/// \name PWR registers
289
/// @{
290
#define MCCI_STM32L0_REG_PWR_CR (MCCI_STM32L0_REG_PWR + 0x0)
291
#define MCCI_STM32L0_REG_PWR_CSR (MCCI_STM32L0_REG_PWR + 0x4)
292
/// @}
293
294
/// \name PWR_CR bits
295
/// @{
296
#define MCCI_STM32L0_REG_PWR_CR_LPRUN (UINT32_C(1) << 14)
///< Low power run mode
297
#define MCCI_STM32L0_REG_PWR_CR_DS_EE_KOFF (UINT32_C(1) << 13)
///< deep sleep mode with nv mem off
298
299
#define MCCI_STM32L0_REG_PWR_CR_VOS (UINT32_C(3) << 11)
///< voltage scaling range
300
# define MCCI_STM32L0_REG_PWR_CR_VOS_NC MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_VOS, 0)
///< no change / not allowed
301
# define MCCI_STM32L0_REG_PWR_CR_VOS_1V8 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_VOS, 1)
///< 1.8V
302
# define MCCI_STM32L0_REG_PWR_CR_VOS_1V5 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_VOS, 2)
///< 1.5V
303
# define MCCI_STM32L0_REG_PWR_CR_VOS_1V2 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_VOS, 3)
///< 1.2V
304
305
#define MCCI_STM32L0_REG_PWR_CR_FWU (UINT32_C(1) << 10)
///< fast wakeup
306
#define MCCI_STM32L0_REG_PWR_CR_ULP (UINT32_C(1) << 9)
///< ultra low-power mode
307
#define MCCI_STM32L0_REG_PWR_CR_DBP (UINT32_C(1) << 8)
///< disable backup write protection
308
309
#define MCCI_STM32L0_REG_PWR_CR_PLS (UINT32_C(7) << 5)
///< power voltage detector level
310
# define MCCI_STM32L0_REG_PWR_CR_PLS_1V9 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 0)
///< 1.9 V
311
# define MCCI_STM32L0_REG_PWR_CR_PLS_2V1 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 1)
///< 2.1 V
312
# define MCCI_STM32L0_REG_PWR_CR_PLS_2V3 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 2)
///< 2.3 V
313
# define MCCI_STM32L0_REG_PWR_CR_PLS_2V5 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 3)
///< 2.5 V
314
# define MCCI_STM32L0_REG_PWR_CR_PLS_2V7 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 4)
///< 2.7 V
315
# define MCCI_STM32L0_REG_PWR_CR_PLS_2V9 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 5)
///< 2.9 V
316
# define MCCI_STM32L0_REG_PWR_CR_PLS_3V1 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 6)
///< 3.1 V
317
# define MCCI_STM32L0_REG_PWR_CR_PLS_EXT MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 7)
///< Vrefint
318
319
#define MCCI_STM32L0_REG_PWR_CR_PVDE (UINT32_C(1) << 4)
///< power voltage detector enabled
320
#define MCCI_STM32L0_REG_PWR_CR_CSBF (UINT32_C(1) << 3)
///< clear the SBF standby flag
321
#define MCCI_STM32L0_REG_PWR_CR_CWUF (UINT32_C(1) << 2)
///< clear the wakeup flag
322
#define MCCI_STM32L0_REG_PWR_CR_PDDS (UINT32_C(1) << 1)
///< power-down deep sleep
323
#define MCCI_STM32L0_REG_PWR_CR_LPSDSR (UINT32_C(1) << 0)
///< low-power deep sleep/sleep/low-power run
324
/// @}
325
326
/// \name PWR_SCR bits
327
/// @{
328
#define MCCI_STM32L0_REG_PWR_CSR_RSV11 UINT32C(0xFFFFF800)
///< reserved, do not change
329
#define MCCI_STM32L0_REG_PWR_CSR_EWUP3 (UINT32_C(1) << 10)
///< Enable WKUP pin 3
330
#define MCCI_STM32L0_REG_PWR_CSR_EWUP2 (UINT32_C(1) << 9)
///< Enable WKUP pin 2
331
#define MCCI_STM32L0_REG_PWR_CSR_EWUP1 (UINT32_C(1) << 8)
///< Enable WKUP pin 1
332
#define MCCI_STM32L0_REG_PWR_CSR_RSV6 (UINT32_C(3) << 6)
///< Reserved, do not change
333
#define MCCI_STM32L0_REG_PWR_CSR_REGLPF (UINT32_C(1) << 5)
///< Regulator low-power flag
334
#define MCCI_STM32L0_REG_PWR_CSR_VOSF (UINT32_C(1) << 4)
///< Voltage scaling select flag
335
#define MCCI_STM32L0_REG_PWR_CSR_VREFINTRDYF (UINT32_C(1) << 3)
///< Vrefint ready flag
336
#define MCCI_STM32L0_REG_PWR_CSR_PVDO (UINT32_C(1) << 2)
///< PVD output
337
#define MCCI_STM32L0_REG_PWR_CSR_SBF (UINT32_C(1) << 1)
///< Standby flag
338
#define MCCI_STM32L0_REG_PWR_CSR_WUF (UINT32_C(1) << 0)
///< Wakeup flag
339
/// @}
340
341
/****************************************************************************\
342
|
343
| Reset and Clock Control (RCC) Registers
344
|
345
\****************************************************************************/
346
347
/// \name RCC registers
348
/// @{
349
#define MCCI_STM32L0_REG_RCC_CR (MCCI_STM32L0_REG_RCC + 0x00)
///< Clock control
350
#define MCCI_STM32L0_REG_RCC_ICSCR (MCCI_STM32L0_REG_RCC + 0x04)
///< Internal clock sources calibration
351
#define MCCI_STM32L0_REG_RCC_CRRCR (MCCI_STM32L0_REG_RCC + 0x08)
///< Clock recovery RC
352
#define MCCI_STM32L0_REG_RCC_CFGR (MCCI_STM32L0_REG_RCC + 0x0C)
///< Clock configuration
353
#define MCCI_STM32L0_REG_RCC_CIER (MCCI_STM32L0_REG_RCC + 0x10)
///< Clock interrupt enable
354
#define MCCI_STM32L0_REG_RCC_CIFR (MCCI_STM32L0_REG_RCC + 0x14)
///< Clock interrupt flag
355
#define MCCI_STM32L0_REG_RCC_CICR (MCCI_STM32L0_REG_RCC + 0x18)
///< Clock interrupt clear
356
#define MCCI_STM32L0_REG_RCC_IOPRSTR (MCCI_STM32L0_REG_RCC + 0x1C)
///< GPIO reset
357
#define MCCI_STM32L0_REG_RCC_AHBRSTR (MCCI_STM32L0_REG_RCC + 0x20)
///< AHB peripheral reset
358
#define MCCI_STM32L0_REG_RCC_APB2RSTR (MCCI_STM32L0_REG_RCC + 0x24)
///< APB2 peripheral reset
359
#define MCCI_STM32L0_REG_RCC_APB1RSTR (MCCI_STM32L0_REG_RCC + 0x28)
///< APB1 peripheral reset
360
#define MCCI_STM32L0_REG_RCC_IOPENR (MCCI_STM32L0_REG_RCC + 0x2C)
///< GPIO clock enable
361
#define MCCI_STM32L0_REG_RCC_AHBENR (MCCI_STM32L0_REG_RCC + 0x30)
///< AHB peripheral clock enable
362
#define MCCI_STM32L0_REG_RCC_APB2ENR (MCCI_STM32L0_REG_RCC + 0x34)
///< APB2 peripheral clock enable
363
#define MCCI_STM32L0_REG_RCC_APB1ENR (MCCI_STM32L0_REG_RCC + 0x38)
///< APB1 peripheral clock enable
364
#define MCCI_STM32L0_REG_RCC_IOPSMEN (MCCI_STM32L0_REG_RCC + 0x3C)
///< GPIO clock enable in sleep
365
#define MCCI_STM32L0_REG_RCC_AHBSMENR (MCCI_STM32L0_REG_RCC + 0x40)
///< AHB peripheral clock enable in sleep
366
#define MCCI_STM32L0_REG_RCC_APB2SMENR (MCCI_STM32L0_REG_RCC + 0x44)
///< APB2 peripheral clock enable in sleep
367
#define MCCI_STM32L0_REG_RCC_APB1SMENR (MCCI_STM32L0_REG_RCC + 0x48)
///< APB1 peripheral clock enable in sleep
368
#define MCCI_STM32L0_REG_RCC_CCIPR (MCCI_STM32L0_REG_RCC + 0x4C)
///< Clock configuration CCIPR
369
#define MCCI_STM32L0_REG_RCC_CSR (MCCI_STM32L0_REG_RCC + 0x50)
///< Control/status
370
/// @}
371
372
/// \name RCC_CR bits
373
/// @{
374
#define MCCI_STM32L0_REG_RCC_CR_RSV26 UINT32_C(0xFC000000)
//< reserved, no change
375
#define MCCI_STM32L0_REG_RCC_CR_PLLRDY (UINT32_C(1) << 25)
//< PLL clock is ready
376
#define MCCI_STM32L0_REG_RCC_CR_PLLON (UINT32_C(1) << 24)
//< PLL enable
377
#define MCCI_STM32L0_REG_RCC_CR_RSV22 (UINT32_C(3) << 22)
//< reserved, no change
378
#define MCCI_STM32L0_REG_RCC_CR_RTCPRE (UINT32_C(3) << 20)
//< RTC prescalers
379
#define MCCI_STM32L0_REG_RCC_CR_RTCPRE_2 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLSMCCI_STM32L0_REG_RCC_CR_RTCPRE, 0)
380
#define MCCI_STM32L0_REG_RCC_CR_RTCPRE_4 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLSMCCI_STM32L0_REG_RCC_CR_RTCPRE, 1)
381
#define MCCI_STM32L0_REG_RCC_CR_RTCPRE_8 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLSMCCI_STM32L0_REG_RCC_CR_RTCPRE, 2)
382
#define MCCI_STM32L0_REG_RCC_CR_RTCPRE_16 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLSMCCI_STM32L0_REG_RCC_CR_RTCPRE, 3)
383
#define MCCI_STM32L0_REG_RCC_CR_CSSHSEON (UINT32_C(1) << 19)
//< enable clock security HSE
384
#define MCCI_STM32L0_REG_RCC_CR_HSEBYP (UINT32_C(1) << 18)
//< enable HSE clock bypass
385
#define MCCI_STM32L0_REG_RCC_CR_HSERDY (UINT32_C(1) << 17)
//< HSE clock ready
386
#define MCCI_STM32L0_REG_RCC_CR_HSEON (UINT32_C(1) << 16)
//< HSE enabled
387
#define MCCI_STM32L0_REG_RCC_CR_RSV10 UINT32_C(0x0000FC00)
//< reserved, no change
388
#define MCCI_STM32L0_REG_RCC_CR_MSIRDY (UINT32_C(1) << 9)
//< MSI clock ready
389
#define MCCI_STM32L0_REG_RCC_CR_MSION (UINT32_C(1) << 8)
//< MSI clock on
390
#define MCCI_STM32L0_REG_RCC_CR_RSV6 (UINT32_C(3) << 6)
//< reserved, no change
391
#define MCCI_STM32L0_REG_RCC_CR_HSI16OUTEN (UINT32_C(1) << 5)
//< enable HSI16 output to TIM2
392
#define MCCI_STM32L0_REG_RCC_CR_HSI16DIVF (UINT32_C(1) << 4)
//< HSI16 is being divided by 4 (status)
393
#define MCCI_STM32L0_REG_RCC_CR_HSI16DIVEN (UINT32_C(1) << 3)
//< Divide HSI16 by 4 (control)
394
#define MCCI_STM32L0_REG_RCC_CR_HSI16RDYF (UINT32_C(1) << 2)
//< HSI16 is stable
395
#define MCCI_STM32L0_REG_RCC_CR_HSI16KERON (UINT32_C(1) << 1)
//< force HSI16 on during stop
396
#define MCCI_STM32L0_REG_RCC_CR_HSI16ON (UINT32_C(1) << 0)
//< enable HSI16
397
/// @}
398
399
/// \name RCC_ICSCR bits
400
/// @{
401
#define MCCI_STM32L0_REG_RCC_ICSCR_MSITRIM (UINT32_C(0xFF) << 24)
//< MSI clock trimming
402
#define MCCI_STM32L0_REG_RCC_ICSCR_MSICAL (UINT32_C(0xFF) << 16)
//< MSI clock cal
403
404
#define MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE (UINT32_C(7) << 13)
//< MSI clock ranges
405
#define MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_65k MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 0)
//< 65.536 kHz
406
#define MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_131k MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 1)
//< 131.072 kHz
407
#define MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_262k MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 2)
//< 262.144 kHz
408
#define MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_524k MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 3)
//< 524.288 kHz
409
#define MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_1048k MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 4)
//< 1.048 MHz
410
#define MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_2097k MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 5)
//< 2.097 MHz
411
#define MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_4194k MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 6)
//< 4.194 MHz
412
413
#define MCCI_STM32L0_REG_RCC_ICSCR_HSI16TRIM (UINT32_C(0x1F) << 8)
//< HSI16 trim
414
#define MCCI_STM32L0_REG_RCC_ICSCR_HSI16CAL (UINT32_C(0xFF) << 0)
//< HSI16 clock cal
415
/// @}
416
417
/// \name RCC_CRRCR bits
418
/// @{
419
#define MCCI_STM32L0_REG_RCC_CRRCR_RSV16 UINT32_C(0xFFFF0000)
//< reserved, don't change
420
#define MCCI_STM32L0_REG_RCC_CRRCR_HSI48CAL (UINT32_C(0xFF) << 8)
//< calibration for HSI48
421
#define MCCI_STM32L0_REG_RCC_CRRCR_RSV3 UINT32_C(0xF8)
//< reserved, don't change
422
#define MCCI_STM32L0_REG_RCC_CRRCR_HSI48DIVEN (UINT32_C(1) << 2)
//< deliver HSI48/6 to TIM3
423
#define MCCI_STM32L0_REG_RCC_CRRCR_HSI48RDY (UINT32_C(1) << 1)
//< 48 MHz clock ready
424
#define MCCI_STM32L0_REG_RCC_CRRCR_HSI48ON (UINT32_C(1) << 0)
//< 48 MHz clock enable
425
/// @}
426
427
/// \name RCC_CFGR bits
428
/// @{
429
#define MCCI_STM32L0_REG_RCC_CFGR_RSV31 (UINT32_C(1) << 31)
//< reserved, don't change
430
431
#define MCCI_STM32L0_REG_RCC_CFGR_MCOPRE (UINT32_C(7) << 28)
//< Clock output prescaler
432
#define MCCI_STM32L0_REG_RCC_CFGR_MCOPRE_1 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOPRE, 0)
//< prescale MCO divide by 1
433
#define MCCI_STM32L0_REG_RCC_CFGR_MCOPRE_2 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOPRE, 1)
//< prescale MCO divide by 2
434
#define MCCI_STM32L0_REG_RCC_CFGR_MCOPRE_4 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOPRE, 2)
//< prescale MCO divide by 4
435
#define MCCI_STM32L0_REG_RCC_CFGR_MCOPRE_8 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOPRE, 3)
//< prescale MCO divide by 6
436
#define MCCI_STM32L0_REG_RCC_CFGR_MCOPRE_16 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOPRE, 4)
//< prescale MCO divide by 16
437
438
#define MCCI_STM32L0_REG_RCC_CFGR_MCOSEL (UINT32_C(0xF) << 24)
//< Clock output selection
439
#define MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_OFF MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 0)
//< Clock output disabled
440
#define MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_SYSCLK MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 1)
//< MCO from Sysclk
441
#define MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_HSI16 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 2)
//< MCO from HSI16
442
#define MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_MSI MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 3)
//< MCO from MSI
443
#define MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_HSE MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 4)
//< MCO from HSE
444
#define MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_PLL MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 5)
//< MCO from PLL
445
#define MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_LSI MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 6)
//< MCO from LSI
446
#define MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_LSE MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 7)
//< MCO from LSE
447
#define MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_HSI48 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 8)
//< MCO from HSI48
448
449
#define MCCI_STM32L0_REG_RCC_CFGR_PLLDIV (UINT32_C(3) << 22)
//< PLL divisor
450
#define MCCI_STM32L0_REG_RCC_CFGR_PLLDIV_2 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLDIV, 1)
//< PLL: divide by 2
451
#define MCCI_STM32L0_REG_RCC_CFGR_PLLDIV_3 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLDIV, 2)
//< PLL: divide by 3
452
#define MCCI_STM32L0_REG_RCC_CFGR_PLLDIV_4 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLDIV, 3)
//< PLL: divide by 4
453
#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL (UINT32_C(0xF) << 18)
//< PLL multiplier
454
#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_3 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 0)
//< PLL: multiply by 3
455
#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_4 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 1)
//< PLL: multiply by 4
456
#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_6 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 2)
//< PLL: multiply by 6
457
#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_8 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 3)
//< PLL: multiply by 8
458
#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_12 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 4)
//< PLL: multiply by 12
459
#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_16 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 5)
//< PLL: multiply by 16
460
#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_24 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 6)
//< PLL: multiply by 24
461
#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_32 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 7)
//< PLL: multiply by 32
462
#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_48 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 8)
//< PLL: multiply by 48
463
#define MCCI_STM32L0_REG_RCC_CFGR_RSV17 (UINT32_C(1) << 17)
//< reserved, don't change
464
465
#define MCCI_STM32L0_REG_RCC_CFGR_PLLSRC (UINT32_C(1) << 16)
//< PLL clock source
466
#define MCCI_STM32L0_REG_RCC_CFGR_PLLSRC_HSI16 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLSRC, 0)
//< PLL clock source: HSI16
467
#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_HSE MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLSRC, 1)
//< PLL clock source: HSE
468
469
#define MCCI_STM32L0_REG_RCC_CFGR_STOPWUCK (UINT32_C(1) << 15)
//< Wakeup from stop clock
470
#define MCCI_STM32L0_REG_RCC_CFGR_STOPWUCK_MSI MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_STOPWUCK, 0)
//< Wakeup from stop clock: MSI
471
#define MCCI_STM32L0_REG_RCC_CFGR_STOPWUCK_HSI16 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_STOPWUCK, 1)
//< Wakeup from stop clock: HSI16
472
473
#define MCCI_STM32L0_REG_RCC_CFGR_RSV14 (UINT32_C(1) << 14)
//< reserved, don't change
474
#define MCCI_STM32L0_REG_RCC_CFGR_PPRE2 (UINT32_C(7) << 11)
//< APB high-speed prescaler
475
#define MCCI_STM32L0_REG_RCC_CFGR_PPRE2_1 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE2, 0)
//< AHB high-speed prescaler: not divided
476
#define MCCI_STM32L0_REG_RCC_CFGR_PPRE2_2 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE2, 4)
//< AHB high-speed prescaler: divide by 2
477
#define MCCI_STM32L0_REG_RCC_CFGR_PPRE2_4 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE2, 5)
//< AHB high-speed prescaler: divide by 4
478
#define MCCI_STM32L0_REG_RCC_CFGR_PPRE2_8 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE2, 6)
//< AHB high-speed prescaler: divide by 8
479
#define MCCI_STM32L0_REG_RCC_CFGR_PPRE2_16 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE2, 7)
//< AHB high-speed prescaler: divide by 16
480
#define MCCI_STM32L0_REG_RCC_CFGR_PPRE1 (UINT32_C(7) << 8)
//< APB low-speed prescaler
481
#define MCCI_STM32L0_REG_RCC_CFGR_PPRE1_1 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE1, 0)
//< APB low-speed prescaler: none
482
#define MCCI_STM32L0_REG_RCC_CFGR_PPRE1_2 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE1, 4)
//< APB low-speed prescaler: divide by 2
483
#define MCCI_STM32L0_REG_RCC_CFGR_PPRE1_4 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE1, 5)
//< APB low-speed prescaler: divide by 4
484
#define MCCI_STM32L0_REG_RCC_CFGR_PPRE1_8 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE1, 6)
//< APB low-speed prescaler: divide by 8
485
#define MCCI_STM32L0_REG_RCC_CFGR_PPRE1_16 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE1, 7)
//< APB low-speed prescaler: divide by 16
486
#define MCCI_STM32L0_REG_RCC_CFGR_HPRE (UINT32_C(0xF) << 4)
//< AHB prescaler
487
#define MCCI_STM32L0_REG_RCC_CFGR_HPRE_1 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 0)
//< AHB prescaler: SYSCLK not divided
488
#define MCCI_STM32L0_REG_RCC_CFGR_HPRE_2 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 8)
//< AHB prescaler: SYSCLK / 2
489
#define MCCI_STM32L0_REG_RCC_CFGR_HPRE_4 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 9)
//< AHB prescaler: SYSCLK / 4
490
#define MCCI_STM32L0_REG_RCC_CFGR_HPRE_8 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 10)
//< AHB prescaler: SYSCLK / 8
491
#define MCCI_STM32L0_REG_RCC_CFGR_HPRE_16 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 11)
//< AHB prescaler: SYSCLK / 16
492
#define MCCI_STM32L0_REG_RCC_CFGR_HPRE_64 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 12)
//< AHB prescaler: SYSCLK / 64
493
#define MCCI_STM32L0_REG_RCC_CFGR_HPRE_128 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 13)
//< AHB prescaler: SYSCLK / 128
494
#define MCCI_STM32L0_REG_RCC_CFGR_HPRE_256 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 14)
//< AHB prescaler: SYSCLK / 256
495
#define MCCI_STM32L0_REG_RCC_CFGR_HPRE_512 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 15)
//< AHB prescaler: SYSCLK / 512
496
#define MCCI_STM32L0_REG_RCC_CFGR_SWS (UINT32_C(3) << 2)
//< SYSCLK switch status
497
#define MCCI_STM32L0_REG_RCC_CFGR_SWS_MSI MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SWS, 0)
//< SYSCLK using MSI
498
#define MCCI_STM32L0_REG_RCC_CFGR_SWS_HSI16 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SWS, 1)
//< SYSCLK using HSI16
499
#define MCCI_STM32L0_REG_RCC_CFGR_SWS_HSE MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SWS, 2)
//< SYSCLK using HSE
500
#define MCCI_STM32L0_REG_RCC_CFGR_SWS_PLL MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SWS, 3)
//< SYSCLK using PLLL
501
#define MCCI_STM32L0_REG_RCC_CFGR_SW (UINT32_C(3) << 0)
//< SYSCLK source select
502
#define MCCI_STM32L0_REG_RCC_CFGR_SW_MSI MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SW, 0)
//< SYSCLK: use MSI
503
#define MCCI_STM32L0_REG_RCC_CFGR_SW_HSI16 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SW, 1)
//< SYSCLK: use HSI16
504
#define MCCI_STM32L0_REG_RCC_CFGR_SW_HSE MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SW, 2)
//< SYSCLK: use HSE
505
#define MCCI_STM32L0_REG_RCC_CFGR_SW_PLL MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SW, 3)
//< SYSCLK: use PLL
506
/// @}
507
508
/// \name RCC_CIER bits
509
/// @{
510
#define MCCI_STM32L0_REG_RCC_CIER_RSV8 UINT32_C(0xFFFFFF00)
511
#define MCCI_STM32L0_REG_RCC_CIER_CSSLSE (UINT32_C(1) << 7)
512
#define MCCI_STM32L0_REG_RCC_CIER_HSI48RDYIE (UINT32_C(1) << 6)
513
#define MCCI_STM32L0_REG_RCC_CIER_MSIRDYIE (UINT32_C(1) << 5)
514
#define MCCI_STM32L0_REG_RCC_CIER_PLLRDYIE (UINT32_C(1) << 4)
515
#define MCCI_STM32L0_REG_RCC_CIER_HSERDYIE (UINT32_C(1) << 3)
516
#define MCCI_STM32L0_REG_RCC_CIER_HSI16RDYIE (UINT32_C(1) << 2)
517
#define MCCI_STM32L0_REG_RCC_CIER_LSERDYIE (UINT32_C(1) << 1)
518
#define MCCI_STM32L0_REG_RCC_CIER_LSIRDYIE (UINT32_C(1) << 0)
519
/// @}
520
521
/// \name RCC_CIFR bits
522
/// @{
523
#define MCCI_STM32L0_REG_RCC_CIFR_RSV9 UINT32_C(0xFFFFFE00)
524
#define MCCI_STM32L0_REG_RCC_CIFR_CSSHSEF (UINT32_C(1) << 8)
525
#define MCCI_STM32L0_REG_RCC_CIFR_CSSLSEF (UINT32_C(1) << 7)
526
#define MCCI_STM32L0_REG_RCC_CIFR_HSI48RDYF (UINT32_C(1) << 6)
527
#define MCCI_STM32L0_REG_RCC_CIFR_MSIRDYF (UINT32_C(1) << 5)
528
#define MCCI_STM32L0_REG_RCC_CIFR_PLLRDYF (UINT32_C(1) << 4)
529
#define MCCI_STM32L0_REG_RCC_CIFR_HSERDYF (UINT32_C(1) << 3)
530
#define MCCI_STM32L0_REG_RCC_CIFR_HSI16RDYF (UINT32_C(1) << 2)
531
#define MCCI_STM32L0_REG_RCC_CIFR_LSERDYF (UINT32_C(1) << 1)
532
#define MCCI_STM32L0_REG_RCC_CIFR_LSIRDYF (UINT32_C(1) << 0)
533
/// @}
534
535
/// \name RCC_CICR bits
536
/// @{
537
#define MCCI_STM32L0_REG_RCC_CICR_RSV9 UINT32_C(0xFFFFFE00)
538
#define MCCI_STM32L0_REG_RCC_CICR_CSSHSEC (UINT32_C(1) << 8)
539
#define MCCI_STM32L0_REG_RCC_CICR_CSSLSEC (UINT32_C(1) << 7)
540
#define MCCI_STM32L0_REG_RCC_CICR_HSI48RDYC (UINT32_C(1) << 6)
541
#define MCCI_STM32L0_REG_RCC_CICR_MSIRDYC (UINT32_C(1) << 5)
542
#define MCCI_STM32L0_REG_RCC_CICR_PLLRDYC (UINT32_C(1) << 4)
543
#define MCCI_STM32L0_REG_RCC_CICR_HSERDYC (UINT32_C(1) << 3)
544
#define MCCI_STM32L0_REG_RCC_CICR_HSI16RDYC (UINT32_C(1) << 2)
545
#define MCCI_STM32L0_REG_RCC_CICR_LSERDYC (UINT32_C(1) << 1)
546
#define MCCI_STM32L0_REG_RCC_CICR_LSIRDYC (UINT32_C(1) << 0)
547
/// @}
548
549
/// \name RCC_IOPRSTR bits
550
/// @{
551
#define MCCI_STM32L0_REG_RCC_IOPRSTR_RSV8 UINT32_C(0xFFFFFF00)
//< reserved, don't change
552
#define MCCI_STM32L0_REG_RCC_IOPRSTR_IOPHRST (UINT32_C(1) << 7)
//< Port H reset
553
#define MCCI_STM32L0_REG_RCC_IOPRSTR_RSV5 (UINT32_C(3) << 5)
//< reserved, don't change
554
#define MCCI_STM32L0_REG_RCC_IOPRSTR_IOPERST (UINT32_C(1) << 4)
//< Port E reset
555
#define MCCI_STM32L0_REG_RCC_IOPRSTR_IOPDRST (UINT32_C(1) << 3)
//< Port D reset
556
#define MCCI_STM32L0_REG_RCC_IOPRSTR_IOPCRST (UINT32_C(1) << 2)
//< Port C reset
557
#define MCCI_STM32L0_REG_RCC_IOPRSTR_IOPBRST (UINT32_C(1) << 1)
//< Port B reset
558
#define MCCI_STM32L0_REG_RCC_IOPRSTR_IOPARST (UINT32_C(1) << 0)
//< Port A reset
559
/// @}
560
561
/// \name RCC_AHBRSTR bits
562
/// @{
563
#define MCCI_STM32L0_REG_RCC_AHBRSTR_RSV25 (UINT32_C(0x7F) << 25)
//< reserved, don't change
564
#define MCCI_STM32L0_REG_RCC_AHBRSTR_CRYPRST (UINT32_C(1) << 24)
//< Crypto reset
565
#define MCCI_STM32L0_REG_RCC_AHBRSTR_RSV21 (UINT32_C(7) << 21)
//< reserved, don't change
566
#define MCCI_STM32L0_REG_RCC_AHBRSTR_RNGRST (UINT32_C(1) << 20)
//< Random number generator reset
567
#define MCCI_STM32L0_REG_RCC_AHBRSTR_RSV17 (UINT32_C(7) << 17)
//< reserved, don't change
568
#define MCCI_STM32L0_REG_RCC_AHBRSTR_TSCRST (UINT32_C(1) << 16)
//< Touch sensor reset
569
#define MCCI_STM32L0_REG_RCC_AHBRSTR_RSV13 (UINT32_C(7) << 13)
//< reserved, don't change
570
#define MCCI_STM32L0_REG_RCC_AHBRSTR_CRCRST (UINT32_C(1) << 12)
//< CRC reset
571
#define MCCI_STM32L0_REG_RCC_AHBRSTR_RSV9 (UINT32_C(7) << 9)
//< reserved, don't change
572
#define MCCI_STM32L0_REG_RCC_AHBRSTR_MIFRST (UINT32_C(1) << 8)
//< Memory interface reset
573
#define MCCI_STM32L0_REG_RCC_AHBRSTR_RSV1 (UINT32_C(0x7F) << 1)
//< reserved, don't change
574
#define MCCI_STM32L0_REG_RCC_AHBRSTR_DMARST (UINT32_C(1) << 0)
//< DMA reset
575
/// @}
576
577
/// \name RCC_APB2RSTR bits
578
/// @{
579
#define MCCI_STM32L0_REG_RCC_APB2RSTR_RSV23 UINT32_C(0xFF800000)
///< reserved, don't change
580
#define MCCI_STM32L0_REG_RCC_APB2RSTR_DBGRST (UINT32_C(1) << 22)
///< Debug reset
581
#define MCCI_STM32L0_REG_RCC_APB2RSTR_RSV15 (UINT32_C(0x7F) << 15)
///< reserved, don't change
582
#define MCCI_STM32L0_REG_RCC_APB2RSTR_USART1RST (UINT32_C(1) << 14)
///< USART1 reset
583
#define MCCI_STM32L0_REG_RCC_APB2RSTR_RSV13 (UINT32_C(1) << 13)
///< reserved, don't change
584
#define MCCI_STM32L0_REG_RCC_APB2RSTR_SPI1RST (UINT32_C(1) << 12)
///< SPI1 reset
585
#define MCCI_STM32L0_REG_RCC_APB2RSTR_RSV10 (UINT32_C(3) << 10)
///< reserved, don't change
586
#define MCCI_STM32L0_REG_RCC_APB2RSTR_ADCRST (UINT32_C(1) << 9)
///< ADC reset
587
#define MCCI_STM32L0_REG_RCC_APB2RSTR_RSV6 (UINT32_C(7) << 6)
///< reserved, don't change
588
#define MCCI_STM32L0_REG_RCC_APB2RSTR_TIM22RST (UINT32_C(1) << 5)
///< TIM22 reset
589
#define MCCI_STM32L0_REG_RCC_APB2RSTR_RSV3 (UINT32_C(3) << 3)
///< reserved, don't change
590
#define MCCI_STM32L0_REG_RCC_APB2RSTR_TIM21RST (UINT32_C(1) << 2)
///< TIM21 reset
591
#define MCCI_STM32L0_REG_RCC_APB2RSTR_RSV1 (UINT32_C(1) << 1)
///< reserved, don't change
592
#define MCCI_STM32L0_REG_RCC_APB2RSTR_SYSCFRST (UINT32_C(1) << 0)
///< SYSCFG reset
593
/// @}
594
595
/// \name RCC_APB1RSTR bits
596
/// @{
597
#define MCCI_STM32L0_REG_RCC_APB1RSTR_LPTIM1RST (UINT32_C(1) << 31)
//< LPTIM1 reset
598
#define MCCI_STM32L0_REG_RCC_APB1RSTR_I2C3RST (UINT32_C(1) << 30)
//< I2C3 reset
599
#define MCCI_STM32L0_REG_RCC_APB1RSTR_DACRRST (UINT32_C(1) << 29)
//< DACR reset
600
#define MCCI_STM32L0_REG_RCC_APB1RSTR_PWRRST (UINT32_C(1) << 28)
//< PWR reset
601
#define MCCI_STM32L0_REG_RCC_APB1RSTR_CRSRST (UINT32_C(1) << 27)
//< CRS reset
602
#define MCCI_STM32L0_REG_RCC_APB1RSTR_RSV24 (UINT32_C(7) << 24)
//< reserved, don't change
603
#define MCCI_STM32L0_REG_RCC_APB1RSTR_USBRST (UINT32_C(1) << 23)
//< USB reset
604
#define MCCI_STM32L0_REG_RCC_APB1RSTR_I2C2RST (UINT32_C(1) << 22)
//< I2C2 reset
605
#define MCCI_STM32L0_REG_RCC_APB1RSTR_I2C1RST (UINT32_C(1) << 21)
//< I2C1 reset
606
#define MCCI_STM32L0_REG_RCC_APB1RSTR_USART5RST (UINT32_C(1) << 20)
//< USART5 reset
607
#define MCCI_STM32L0_REG_RCC_APB1RSTR_USART4RST (UINT32_C(1) << 19)
//< USART4 reset
608
#define MCCI_STM32L0_REG_RCC_APB1RSTR_LPUART1RST (UINT32_C(1) << 18)
//< LPUART1 reset
609
#define MCCI_STM32L0_REG_RCC_APB1RSTR_USART2RST (UINT32_C(1) << 17)
//< USART2 reset
610
#define MCCI_STM32L0_REG_RCC_APB1RSTR_RSV15 (UINT32_C(3) << 15)
//< reserved, don't change
611
#define MCCI_STM32L0_REG_RCC_APB1RSTR_SPI2RST (UINT32_C(1) << 14)
//< SPI2 reset
612
#define MCCI_STM32L0_REG_RCC_APB1RSTR_RSV12 (UINT32_C(3) << 12)
//< reserved, don't change
613
#define MCCI_STM32L0_REG_RCC_APB1RSTR_WWDGRST (UINT32_C(1) << 11)
//< Watchdog reset
614
#define MCCI_STM32L0_REG_RCC_APB1RSTR_RSV6 (UINT32_C(0x1F) << 6)
//< reserved, don't change
615
#define MCCI_STM32L0_REG_RCC_APB1RSTR_TIM7RST (UINT32_C(1) << 5)
//< TIM7 reset
616
#define MCCI_STM32L0_REG_RCC_APB1RSTR_TIM6RST (UINT32_C(1) << 4)
//< TIM6 reset
617
#define MCCI_STM32L0_REG_RCC_APB1RSTR_RSV2 (UINT32_C(3) << 2)
//< reserved, don't change
618
#define MCCI_STM32L0_REG_RCC_APB1RSTR_TIM3 (UINT32_C(1) << 1)
//< TIM3 reset
619
#define MCCI_STM32L0_REG_RCC_APB1RSTR_TIM2 (UINT32_C(1) << 0)
//< TIM2 reset
620
/// @}
621
622
/// \name RCC_IOPENR bits
623
/// @{
624
#define MCCI_STM32L0_REG_RCC_IOPENR_RSV8 UINT32_C(0xFFFFFF00)
//< reserved, don't change
625
#define MCCI_STM32L0_REG_RCC_IOPENR_IOPHEN (UINT32_C(1) << 7)
//< Port H enable
626
#define MCCI_STM32L0_REG_RCC_IOPENR_RSV5 (UINT32_C(3) << 5)
//< reserved, don't change
627
#define MCCI_STM32L0_REG_RCC_IOPENR_IOPEEN (UINT32_C(1) << 4)
//< Port E enable
628
#define MCCI_STM32L0_REG_RCC_IOPENR_IOPDEN (UINT32_C(1) << 3)
//< Port D enable
629
#define MCCI_STM32L0_REG_RCC_IOPENR_IOPCEN (UINT32_C(1) << 2)
//< Port C enable
630
#define MCCI_STM32L0_REG_RCC_IOPENR_IOPBEN (UINT32_C(1) << 1)
//< Port B enable
631
#define MCCI_STM32L0_REG_RCC_IOPENR_IOPAEN (UINT32_C(1) << 0)
//< Port A enable
632
/// @}
633
634
/// \name RCC_AHBENR bits
635
/// @{
636
#define MCCI_STM32L0_REG_RCC_AHBENR_RSV25 (UINT32_C(0x7F) << 25)
//< reserved, don't change
637
#define MCCI_STM32L0_REG_RCC_AHBENR_CRYPEN (UINT32_C(1) << 24)
//< Crypto enable
638
#define MCCI_STM32L0_REG_RCC_AHBENR_RSV21 (UINT32_C(7) << 21)
//< reserved, don't change
639
#define MCCI_STM32L0_REG_RCC_AHBENR_RNGEN (UINT32_C(1) << 20)
//< Random number generator enable
640
#define MCCI_STM32L0_REG_RCC_AHBENR_RSV17 (UINT32_C(7) << 17)
//< reserved, don't change
641
#define MCCI_STM32L0_REG_RCC_AHBENR_TSCEN (UINT32_C(1) << 16)
//< Touch sensor enable
642
#define MCCI_STM32L0_REG_RCC_AHBENR_RSV13 (UINT32_C(7) << 13)
//< reserved, don't change
643
#define MCCI_STM32L0_REG_RCC_AHBENR_CRCEN (UINT32_C(1) << 12)
//< CRC enable
644
#define MCCI_STM32L0_REG_RCC_AHBENR_RSV9 (UINT32_C(7) << 9)
//< reserved, don't change
645
#define MCCI_STM32L0_REG_RCC_AHBENR_MIFEN (UINT32_C(1) << 8)
//< Memory interface enable
646
#define MCCI_STM32L0_REG_RCC_AHBENR_RSV1 (UINT32_C(0x7F) << 1)
//< reserved, don't change
647
#define MCCI_STM32L0_REG_RCC_AHBENR_DMAEN (UINT32_C(1) << 0)
//< DMA enable
648
/// @}
649
650
/// \name RCC_APB2ENR bits
651
/// @{
652
#define MCCI_STM32L0_REG_RCC_APB2ENR_RSV23 UINT32_C(0xFF800000)
///< reserved, don't change
653
#define MCCI_STM32L0_REG_RCC_APB2ENR_DBGEN (UINT32_C(1) << 22)
///< Debug enable
654
#define MCCI_STM32L0_REG_RCC_APB2ENR_RSV15 (UINT32_C(0x7F) << 15)
///< reserved, don't change
655
#define MCCI_STM32L0_REG_RCC_APB2ENR_USART1EN (UINT32_C(1) << 14)
///< USART1 enable
656
#define MCCI_STM32L0_REG_RCC_APB2ENR_RSV13 (UINT32_C(1) << 13)
///< reserved, don't change
657
#define MCCI_STM32L0_REG_RCC_APB2ENR_SPI1EN (UINT32_C(1) << 12)
///< SPI1 enable
658
#define MCCI_STM32L0_REG_RCC_APB2ENR_RSV10 (UINT32_C(3) << 10)
///< reserved, don't change
659
#define MCCI_STM32L0_REG_RCC_APB2ENR_ADCEN (UINT32_C(1) << 9)
///< ADC enable
660
#define MCCI_STM32L0_REG_RCC_APB2ENR_RSV6 (UINT32_C(7) << 6)
///< reserved, don't change
661
#define MCCI_STM32L0_REG_RCC_APB2ENR_TIM22EN (UINT32_C(1) << 5)
///< TIM22 enable
662
#define MCCI_STM32L0_REG_RCC_APB2ENR_RSV3 (UINT32_C(3) << 3)
///< reserved, don't change
663
#define MCCI_STM32L0_REG_RCC_APB2ENR_TIM21EN (UINT32_C(1) << 2)
///< TIM21 enable
664
#define MCCI_STM32L0_REG_RCC_APB2ENR_RSV1 (UINT32_C(1) << 1)
///< reserved, don't change
665
#define MCCI_STM32L0_REG_RCC_APB2ENR_SYSCFEN (UINT32_C(1) << 0)
///< SYSCFG enable
666
/// @}
667
668
/// \name RCC_APB1ENR bits
669
/// @{
670
#define MCCI_STM32L0_REG_RCC_APB1ENR_LPTIM1EN (UINT32_C(1) << 31)
//< LPTIM1 enable
671
#define MCCI_STM32L0_REG_RCC_APB1ENR_I2C3EN (UINT32_C(1) << 30)
//< I2C3 enable
672
#define MCCI_STM32L0_REG_RCC_APB1ENR_DACREN (UINT32_C(1) << 29)
//< DACR enable
673
#define MCCI_STM32L0_REG_RCC_APB1ENR_PWREN (UINT32_C(1) << 28)
//< PWR enable
674
#define MCCI_STM32L0_REG_RCC_APB1ENR_CRSEN (UINT32_C(1) << 27)
//< CRS enable
675
#define MCCI_STM32L0_REG_RCC_APB1ENR_RSV24 (UINT32_C(7) << 24)
//< reserved, don't change
676
#define MCCI_STM32L0_REG_RCC_APB1ENR_USBEN (UINT32_C(1) << 23)
//< USB enable
677
#define MCCI_STM32L0_REG_RCC_APB1ENR_I2C2EN (UINT32_C(1) << 22)
//< I2C2 enable
678
#define MCCI_STM32L0_REG_RCC_APB1ENR_I2C1EN (UINT32_C(1) << 21)
//< I2C1 enable
679
#define MCCI_STM32L0_REG_RCC_APB1ENR_USART5EN (UINT32_C(1) << 20)
//< USART5 enable
680
#define MCCI_STM32L0_REG_RCC_APB1ENR_USART4EN (UINT32_C(1) << 19)
//< USART4 enable
681
#define MCCI_STM32L0_REG_RCC_APB1ENR_LPUART1EN (UINT32_C(1) << 18)
//< LPUART1 enable
682
#define MCCI_STM32L0_REG_RCC_APB1ENR_USART2EN (UINT32_C(1) << 17)
//< USART2 enable
683
#define MCCI_STM32L0_REG_RCC_APB1ENR_RSV15 (UINT32_C(3) << 15)
//< reserved, don't change
684
#define MCCI_STM32L0_REG_RCC_APB1ENR_SPI2EN (UINT32_C(1) << 14)
//< SPI2 enable
685
#define MCCI_STM32L0_REG_RCC_APB1ENR_RSV12 (UINT32_C(3) << 12)
//< reserved, don't change
686
#define MCCI_STM32L0_REG_RCC_APB1ENR_WWDGEN (UINT32_C(1) << 11)
//< Watchdog enable
687
#define MCCI_STM32L0_REG_RCC_APB1ENR_RSV6 (UINT32_C(0x1F) << 6)
//< reserved, don't change
688
#define MCCI_STM32L0_REG_RCC_APB1ENR_TIM7EN (UINT32_C(1) << 5)
//< TIM7 enable
689
#define MCCI_STM32L0_REG_RCC_APB1ENR_TIM6EN (UINT32_C(1) << 4)
//< TIM6 enable
690
#define MCCI_STM32L0_REG_RCC_APB1ENR_RSV2 (UINT32_C(3) << 2)
//< reserved, don't change
691
#define MCCI_STM32L0_REG_RCC_APB1ENR_TIM3 (UINT32_C(1) << 1)
//< TIM3 enable
692
#define MCCI_STM32L0_REG_RCC_APB1ENR_TIM2 (UINT32_C(1) << 0)
//< TIM2 enable
693
/// @}
694
695
/// \name RCC_IOPSMEN bits
696
/// @{
697
#define MCCI_STM32L0_REG_RCC_IOPSMENR_RSV8 UINT32_C(0xFFFFFF00)
//< reserved, don't change
698
#define MCCI_STM32L0_REG_RCC_IOPSMENR_IOPHSMEN (UINT32_C(1) << 7)
//< Port H sleep-mode enable
699
#define MCCI_STM32L0_REG_RCC_IOPSMENR_RSV5 (UINT32_C(3) << 5)
//< reserved, don't change
700
#define MCCI_STM32L0_REG_RCC_IOPSMENR_IOPESMEN (UINT32_C(1) << 4)
//< Port E sleep-mode enable
701
#define MCCI_STM32L0_REG_RCC_IOPSMENR_IOPDSMEN (UINT32_C(1) << 3)
//< Port D sleep-mode enable
702
#define MCCI_STM32L0_REG_RCC_IOPSMENR_IOPCSMEN (UINT32_C(1) << 2)
//< Port C sleep-mode enable
703
#define MCCI_STM32L0_REG_RCC_IOPSMENR_IOPBSMEN (UINT32_C(1) << 1)
//< Port B sleep-mode enable
704
#define MCCI_STM32L0_REG_RCC_IOPSMENR_IOPASMEN (UINT32_C(1) << 0)
//< Port A sleep-mode enable
705
/// @}
706
707
/// \name RCC_AHBSMENR bits
708
/// @{
709
#define MCCI_STM32L0_REG_RCC_AHBSMENR_RSV25 (UINT32_C(0x7F) << 25)
//< reserved, don't change
710
#define MCCI_STM32L0_REG_RCC_AHBSMENR_CRYPSMEN (UINT32_C(1) << 24)
//< Crypto sleep-mode enable
711
#define MCCI_STM32L0_REG_RCC_AHBSMENR_RSV21 (UINT32_C(7) << 21)
//< reserved, don't change
712
#define MCCI_STM32L0_REG_RCC_AHBSMENR_RNGSMEN (UINT32_C(1) << 20)
//< Random number generator sleep-mode enable
713
#define MCCI_STM32L0_REG_RCC_AHBSMENR_RSV17 (UINT32_C(7) << 17)
//< reserved, don't change
714
#define MCCI_STM32L0_REG_RCC_AHBSMENR_TSCSMEN (UINT32_C(1) << 16)
//< Touch sensor sleep-mode enable
715
#define MCCI_STM32L0_REG_RCC_AHBSMENR_RSV13 (UINT32_C(7) << 13)
//< reserved, don't change
716
#define MCCI_STM32L0_REG_RCC_AHBSMENR_CRCSMEN (UINT32_C(1) << 12)
//< CRC sleep-mode enable
717
#define MCCI_STM32L0_REG_RCC_AHBSMENR_RSV10 (UINT32_C(3) << 10)
//< reserved, don't change
718
#define MCCI_STM32L0_REG_RCC_AHBSMENR_SRAMSMEN (UINT32_C(1) << 9)
//< SRAM sleep-mode enable
719
#define MCCI_STM32L0_REG_RCC_AHBSMENR_MIFSMEN (UINT32_C(1) << 8)
//< Memory interface sleep-mode enable
720
#define MCCI_STM32L0_REG_RCC_AHBSMENR_RSV1 (UINT32_C(0x7F) << 1)
//< reserved, don't change
721
#define MCCI_STM32L0_REG_RCC_AHBSMENR_DMASMEN (UINT32_C(1) << 0)
//< DMA sleep-mode enable
722
/// @}
723
724
/// \name RCC_APB2SMENR bits
725
/// @{
726
#define MCCI_STM32L0_REG_RCC_APB2SMENR_RSV23 UINT32_C(0xFF800000)
///< reserved, don't change
727
#define MCCI_STM32L0_REG_RCC_APB2SMENR_DBGSMEN (UINT32_C(1) << 22)
///< Debug sleep-mode enable
728
#define MCCI_STM32L0_REG_RCC_APB2SMENR_RSV15 (UINT32_C(0x7F) << 15)
///< reserved, don't change
729
#define MCCI_STM32L0_REG_RCC_APB2SMENR_USART1SMEN (UINT32_C(1) << 14)
///< USART1 sleep-mode enable
730
#define MCCI_STM32L0_REG_RCC_APB2SMENR_RSV13 (UINT32_C(1) << 13)
///< reserved, don't change
731
#define MCCI_STM32L0_REG_RCC_APB2SMENR_SPI1SMEN (UINT32_C(1) << 12)
///< SPI1 sleep-mode enable
732
#define MCCI_STM32L0_REG_RCC_APB2SMENR_RSV10 (UINT32_C(3) << 10)
///< reserved, don't change
733
#define MCCI_STM32L0_REG_RCC_APB2SMENR_ADCSMEN (UINT32_C(1) << 9)
///< ADC sleep-mode enable
734
#define MCCI_STM32L0_REG_RCC_APB2SMENR_RSV6 (UINT32_C(7) << 6)
///< reserved, don't change
735
#define MCCI_STM32L0_REG_RCC_APB2SMENR_TIM22SMEN (UINT32_C(1) << 5)
///< TIM22 sleep-mode enable
736
#define MCCI_STM32L0_REG_RCC_APB2SMENR_RSV3 (UINT32_C(3) << 3)
///< reserved, don't change
737
#define MCCI_STM32L0_REG_RCC_APB2SMENR_TIM21SMEN (UINT32_C(1) << 2)
///< TIM21 sleep-mode enable
738
#define MCCI_STM32L0_REG_RCC_APB2SMENR_RSV1 (UINT32_C(1) << 1)
///< reserved, don't change
739
#define MCCI_STM32L0_REG_RCC_APB2SMENR_SYSCFSMEN (UINT32_C(1) << 0)
///< SYSCFG sleep-mode enable
740
/// @}
741
742
/// \name RCC_APB1SMENR bits
743
/// @{
744
#define MCCI_STM32L0_REG_RCC_APB1SMENR_LPTIM1SMEN (UINT32_C(1) << 31)
//< LPTIM1 sleep-mode enable
745
#define MCCI_STM32L0_REG_RCC_APB1SMENR_I2C3SMEN (UINT32_C(1) << 30)
//< I2C3 sleep-mode enable
746
#define MCCI_STM32L0_REG_RCC_APB1SMENR_DACRSMEN (UINT32_C(1) << 29)
//< DACR sleep-mode enable
747
#define MCCI_STM32L0_REG_RCC_APB1SMENR_PWRSMEN (UINT32_C(1) << 28)
//< PWR sleep-mode enable
748
#define MCCI_STM32L0_REG_RCC_APB1SMENR_CRSSMEN (UINT32_C(1) << 27)
//< CRS sleep-mode enable
749
#define MCCI_STM32L0_REG_RCC_APB1SMENR_RSV24 (UINT32_C(7) << 24)
//< reserved, don't change
750
#define MCCI_STM32L0_REG_RCC_APB1SMENR_USBSMEN (UINT32_C(1) << 23)
//< USB sleep-mode enable
751
#define MCCI_STM32L0_REG_RCC_APB1SMENR_I2C2SMEN (UINT32_C(1) << 22)
//< I2C2 sleep-mode enable
752
#define MCCI_STM32L0_REG_RCC_APB1SMENR_I2C1SMEN (UINT32_C(1) << 21)
//< I2C1 sleep-mode enable
753
#define MCCI_STM32L0_REG_RCC_APB1SMENR_USART5SMEN (UINT32_C(1) << 20)
//< USART5 sleep-mode enable
754
#define MCCI_STM32L0_REG_RCC_APB1SMENR_USART4SMEN (UINT32_C(1) << 19)
//< USART4 sleep-mode enable
755
#define MCCI_STM32L0_REG_RCC_APB1SMENR_LPUART1SMEN (UINT32_C(1) << 18)
//< LPUART1 sleep-mode enable
756
#define MCCI_STM32L0_REG_RCC_APB1SMENR_USART2SMEN (UINT32_C(1) << 17)
//< USART2 sleep-mode enable
757
#define MCCI_STM32L0_REG_RCC_APB1SMENR_RSV15 (UINT32_C(3) << 15)
//< reserved, don't change
758
#define MCCI_STM32L0_REG_RCC_APB1SMENR_SPI2SMEN (UINT32_C(1) << 14)
//< SPI2 sleep-mode enable
759
#define MCCI_STM32L0_REG_RCC_APB1SMENR_RSV12 (UINT32_C(3) << 12)
//< reserved, don't change
760
#define MCCI_STM32L0_REG_RCC_APB1SMENR_WWDGSMEN (UINT32_C(1) << 11)
//< Watchdog sleep-mode enable
761
#define MCCI_STM32L0_REG_RCC_APB1SMENR_RSV6 (UINT32_C(0x1F) << 6)
//< reserved, don't change
762
#define MCCI_STM32L0_REG_RCC_APB1SMENR_TIM7SMEN (UINT32_C(1) << 5)
//< TIM7 sleep-mode enable
763
#define MCCI_STM32L0_REG_RCC_APB1SMENR_TIM6SMEN (UINT32_C(1) << 4)
//< TIM6 sleep-mode enable
764
#define MCCI_STM32L0_REG_RCC_APB1SMENR_RSV2 (UINT32_C(3) << 2)
//< reserved, don't change
765
#define MCCI_STM32L0_REG_RCC_APB1SMENR_TIM3 (UINT32_C(1) << 1)
//< TIM3 sleep-mode enable
766
#define MCCI_STM32L0_REG_RCC_APB1SMENR_TIM2 (UINT32_C(1) << 0)
//< TIM2 sleep-mode enable
767
/// @}
768
769
/// \name RCC_CCIPR bits
770
/// @{
771
#define MCCI_STM32L0_REG_RCC_CCIPR_RSV27 (UINT32_C(0x1F) << 27)
//< reserved, don't change
772
#define MCCI_STM32L0_REG_RCC_CCIPR_HSI48SEL (UINT32_C(1) << 26)
//< HSI48 from PLL USB (not RC48)
773
#define MCCI_STM32L0_REG_RCC_CCIPR_RSV20 (UINT32_C(0x3F) << 20)
//< reserved, don't change
774
775
#define MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL (UINT32_C(3) << 18)
//< select LPTIM1 srt
776
#define MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL_APB MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL, 0)
//< APB clock
777
#define MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL_LSI MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL, 1)
//< LSI clock
778
#define MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL_HSI16 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL, 2)
//< HSI16 clock
779
#define MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL_LSE MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL, 3)
//< LSE clock
780
781
#define MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL (UINT32_C(3) << 16)
//<
782
#define MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL_APB MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL, 0)
//< APB clock
783
#define MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL_LSI MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL, 1)
//< LSI clock
784
#define MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL_HSI16 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL, 2)
//< HSI16 clock
785
786
#define MCCI_STM32L0_REG_RCC_CCIPR_RSV14 (UINT32_C(3) << 14)
//< reserved, don't change
787
#define MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL (UINT32_C(3) << 12)
//<
788
#define MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL_APB MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL, 0)
//< APB clock
789
#define MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL_LSI MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL, 1)
//< LSI clock
790
#define MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL_HSI16 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL, 2)
//< HSI16 clock
791
792
#define MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL (UINT32_C(3) << 10)
//<
793
#define MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL_APB MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL, 0)
//< APB clock
794
#define MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL_LSI MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL, 1)
//< LSI clock
795
#define MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL_HSI16 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL, 2)
//< HSI16 clock
796
#define MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL_LSE MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL, 3)
//< LSE clock
797
798
#define MCCI_STM32L0_REG_RCC_CCIPR_RSV4 (UINT32_C(0x3F) << 4)
//< reserved, don't change
799
800
#define MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL (UINT32_C(3) << 2)
//<
801
#define MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL_APB MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL, 0)
//< APB clock
802
#define MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL_LSI MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL, 1)
//< LSI clock
803
#define MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL_HSI16 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL, 2)
//< HSI16 clock
804
#define MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL_LSE MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL, 3)
//< LSE clock
805
806
#define MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL (UINT32_C(3) << 0)
//<
807
#define MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL_APB MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL, 0)
//< APB clock
808
#define MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL_LSI MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL, 1)
//< LSI clock
809
#define MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL_HSI16 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL, 2)
//< HSI16 clock
810
#define MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL_LSE MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL, 3)
//< LSE clock
811
/// @}
812
813
/// \name RCC_CSR bits
814
/// @{
815
#define MCCI_STM32L0_REG_RCC_CSR_LPWRRSTF (UINT32_C(1) << 31)
//< Reset due to low-power
816
#define MCCI_STM32L0_REG_RCC_CSR_WWDGRSTF (UINT32_C(1) << 30)
//< reset due to window watchdog
817
#define MCCI_STM32L0_REG_RCC_CSR_IWDGRSTF (UINT32_C(1) << 29)
//< reset due to independent watchdog
818
#define MCCI_STM32L0_REG_RCC_CSR_SFTRSTF (UINT32_C(1) << 28)
//< reset due to softwaare
819
#define MCCI_STM32L0_REG_RCC_CSR_PORRSTF (UINT32_C(1) << 27)
//< reset due to power: POR, PDR
820
#define MCCI_STM32L0_REG_RCC_CSR_PINRSTF (UINT32_C(1) << 26)
//< reset due to NRST pin
821
#define MCCI_STM32L0_REG_RCC_CSR_OBLRSTF (UINT32_C(1) << 25)
//< reset due to option byte loading
822
#define MCCI_STM32L0_REG_RCC_CSR_FWRSTF (UINT32_C(1) << 24)
//< reset due to firewall
823
#define MCCI_STM32L0_REG_RCC_CSR_RMVF (UINT32_C(1) << 23)
//< remove reset (clears flags)
824
#define MCCI_STM32L0_REG_RCC_CSR_RSV20 (UINT32_C(7) << 20)
//< Reserved, don't change
825
#define MCCI_STM32L0_REG_RCC_CSR_RTCRST (UINT32_C(1) << 19)
//< reset RTC and backup
826
#define MCCI_STM32L0_REG_RCC_CSR_RTCEN (UINT32_C(1) << 18)
//< enable RTC
827
828
#define MCCI_STM32L0_REG_RCC_CSR_RTCSEL (UINT32_C(3) << 16)
//< RTC clock source select
829
#define MCCI_STM32L0_REG_RCC_CSR_RTCSEL_NONE MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_RTCSEL, 0)
//< no RTC clock
830
#define MCCI_STM32L0_REG_RCC_CSR_RTCSEL_LSE MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_RTCSEL, 0)
//< LSE clock as RTC clock
831
#define MCCI_STM32L0_REG_RCC_CSR_RTCSEL_LSI MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_RTCSEL, 0)
//< LSI clock as RTC clock
832
#define MCCI_STM32L0_REG_RCC_CSR_RTCSEL_HSE MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_RTCSEL, 0)
//< HSE clock divided as RTC clock
833
834
#define MCCI_STM32L0_REG_RCC_CSR_RSV15 (UINT32_C(1) << 15)
//< Reserved, don't change
835
#define MCCI_STM32L0_REG_RCC_CSR_CSSLSED (UINT32_C(1) << 14)
//< CSS on LSE failure
836
#define MCCI_STM32L0_REG_RCC_CSR_CSSLSEON (UINT32_C(1) << 13)
//< CSS on LSE enable
837
838
#define MCCI_STM32L0_REG_RCC_CSR_LSEDRV (UINT32_C(3) << 11)
//< LSE drive
839
#define MCCI_STM32L0_REG_RCC_CSR_LSEDRV_LOW MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_LSEDRV, 0)
//< LSE drive: lowest
840
#define MCCI_STM32L0_REG_RCC_CSR_LSEDRV_M1 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_LSEDRV, 1)
//< LSE drive: medium low
841
#define MCCI_STM32L0_REG_RCC_CSR_LSEDRV_M2 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_LSEDRV, 2)
//< LSE drive: medium high
842
#define MCCI_STM32L0_REG_RCC_CSR_LSEDRV_HIGH MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_LSEDRV, 3)
//< LSE drive: highest
843
844
#define MCCI_STM32L0_REG_RCC_CSR_LSEBYP (UINT32_C(1) << 10)
//< external LSE bypass
845
#define MCCI_STM32L0_REG_RCC_CSR_LSERDY (UINT32_C(1) << 9)
//< LSE ready
846
#define MCCI_STM32L0_REG_RCC_CSR_LSEON (UINT32_C(1) << 8)
//< LSE enable
847
#define MCCI_STM32L0_REG_RCC_CSR_RSV2 (UINT32_C(0x3F) << 2)
//< Reserved, don't change
848
#define MCCI_STM32L0_REG_RCC_CSR_LSIRDY (UINT32_C(1) << 1)
//< LSI ready
849
#define MCCI_STM32L0_REG_RCC_CSR_LSION (UINT32_C(1) << 0)
//< LSI enable
850
/// @}
851
852
/****************************************************************************\
853
|
854
| GPIO Control Registers
855
|
856
\****************************************************************************/
857
858
/// \name GPIO register offsets
859
/// @{
860
#define MCCI_STM32L0_GPIO_MODER UINT32_C(0x00)
//< port mode register
861
#define MCCI_STM32L0_GPIO_OTYPER UINT32_C(0x04)
//< port output type register
862
#define MCCI_STM32L0_GPIO_OSPEEDR UINT32_C(0x08)
//< port output speed register
863
#define MCCI_STM32L0_GPIO_PUPDR UINT32_C(0x0C)
//< port pull-up/pull-down register
864
#define MCCI_STM32L0_GPIO_IDR UINT32_C(0x10)
//< port input data register
865
#define MCCI_STM32L0_GPIO_ODR UINT32_C(0x14)
//< port output data register
866
#define MCCI_STM32L0_GPIO_BSRR UINT32_C(0x18)
//< port bit set/reset register
867
#define MCCI_STM32L0_GPIO_LCKR UINT32_C(0x1C)
//< port configuration lock register
868
#define MCCI_STM32L0_GPIO_AFRL UINT32_C(0x20)
//< port alternate function low register
869
#define MCCI_STM32L0_GPIO_AFRH UINT32_C(0x24)
//< port alternate function high register
870
#define MCCI_STM32L0_GPIO_BRR UINT32_C(0x28)
//< port bit reset register
871
/// @}
872
873
/// \name GPIO_MODER bits -- used to select pin mode, two bits per pin
874
/// @{
875
#define MCCI_STM32L0_GPIO_MODE_MASK UINT32_C(3)
//< mode bit masks
876
#define MCCI_STM32L0_GPIO_MODE_IN UINT32_C(0)
//< digital input
877
#define MCCI_STM32L0_GPIO_MODE_OUT UINT32_C(1)
//< digital output
878
#define MCCI_STM32L0_GPIO_MODE_AF UINT32_C(2)
//< alternate function
879
#define MCCI_STM32L0_GPIO_MODE_ANALOG UINT32_C(3)
//< analog
880
/// @}
881
882
/// \brief compute the mask for the mode bits for port bits 0..15
883
///
884
/// Normally we compute a mask using an expression like:
885
///
886
/// `MCCI_BOOTLOADER_FIELD_SET_VALUE(
887
/// MCCI_STM32L0_GPIO_MODE_P(3),
888
/// MCCI_STM32L0_GPIO_MODE_IN
889
/// )`
890
///
891
#define MCCI_STM32L0_GPIO_MODE_P(p) (UINT32_C(3) << (2 * (p)))
892
893
/// \name GPIO_OTYPER bits
894
/// @{
895
#define MCCI_STM32L0_GPIO_OTYPE_OD UINT32_C(1)
//<
896
/// @}
897
898
/// \name GPIO_OSPEEDR bits -- used to select pin speed, two bits per pin
899
/// @{
900
#define MCCI_STM32L0_GPIO_OSPEED_MASK UINT32_C(3)
//< speed bit masks
901
#define MCCI_STM32L0_GPIO_OSPEED_LOW UINT32_C(0)
//< low
902
#define MCCI_STM32L0_GPIO_OSPEED_MEDIUM UINT32_C(1)
//< medium
903
#define MCCI_STM32L0_GPIO_OSPEED_HIGH UINT32_C(2)
//< high
904
#define MCCI_STM32L0_GPIO_OSPEED_VHIGH UINT32_C(3)
//< very high
905
906
/// \brief compute the mask for the mode bits for port bits 0..15
907
///
908
/// Normally we compute a mask using an expression like:
909
///
910
/// `MCCI_BOOTLOADER_FIELD_SET_VALUE(
911
/// MCCI_STM32L0_GPIO_OSPEED_P(3),
912
/// MCCI_STM32L0_GPIO_OSPEED_IN
913
/// )`
914
///
915
#define MCCI_STM32L0_GPIO_OSPEED_P(p) (UINT32_C(3) << (2 * (p)))
916
/// @}
917
918
/// \name GPIO_PUPDR bits -- used to select pin speed, two bits per pin
919
/// @{
920
#define MCCI_STM32L0_GPIO_PUPD_MASK UINT32_C(3)
//< speed bit masks
921
#define MCCI_STM32L0_GPIO_PUPD_NONE UINT32_C(0)
//< no pullup/pulldown
922
#define MCCI_STM32L0_GPIO_PUPD_PULLUP UINT32_C(1)
//< pullup
923
#define MCCI_STM32L0_GPIO_PUPD_PULLDOWN UINT32_C(2)
//< pulldown
924
925
/// \brief compute the mask for the mode bits for port bits 0..15
926
///
927
/// Normally we compute a mask using an expression like:
928
///
929
/// `MCCI_BOOTLOADER_FIELD_SET_VALUE(
930
/// MCCI_STM32L0_GPIO_PUPD_P(3),
931
/// MCCI_STM32L0_GPIO_PUPD_PULLDOWN
932
/// )`
933
///
934
#define MCCI_STM32L0_GPIO_PUPD_P(p) (UINT32_C(3) << (2 * (p)))
935
/// @}
936
937
/// \name GPIO_BSRR bits
938
/// @{
939
#define MCCI_STM32L0_GPIO_BSRR_BR0 (UINT32_C(1) << 16)
//< reset port bit 0
940
#define MCCI_STM32L0_GPIO_BSRR_BR (UINT32_C(0xFFFF) << 16)
//< mask of port-reset bits
941
#define MCCI_STM32L0_GPIO_BSRR_BS0 (UINT32_C(1) << 0)
//< set port bit 0
942
#define MCCI_STM32L0_GPIO_BSRR_BS (UINT32_C(0xFFFF) << 0)
//< mask of port-set bits
943
/// \brief compute port-bit reset mask for bit \p p.
944
#define MCCI_STM32L0_GPIO_BSRR_BR_P(p) (MCCI_STM32L0_GPIO_BSRR_BR0 << (p))
945
/// \brief compute port-bit set mask for bit \p p.
946
#define MCCI_STM32L0_GPIO_BSRR_BS_P(p) (MCCI_STM32L0_GPIO_BSRR_BS0 << (p))
947
/// @}
948
949
/// \name GPIO_LCKR bits
950
/// @{
951
#define MCCI_STM32L0_GPIO_LCKR_RSV17 UINT32_C(0xFFFE0000)
//< reserved, don't change
952
#define MCCI_STM32L0_GPIO_LCKR_LCKK (UINT32_C(1) << 16)
//< lock key bit; if set, ports are locked.
953
/// \brief compute GPIO lock bit fmask for bit \p p.
954
#define MCCI_STM32L0_GPIO_LCKR_LCK_P(p) (UINT32_C(1) << (p))
955
#define MCCI_STM32L0_GPIO_LCKR_LCK (UINT32_C(0xFFFF) << 0)
//< mask of port-lock bits.
956
/// @}
957
958
/// \name GPIO_AFRx bits
959
/// @{
960
/// \brief get reg offset for GPIO_AFRx
961
#define MCCI_STM32L0_GPIO_AFRx_P(p) (MCCI_STM32L0_GPIO_AFRL + ((p) / UINT32_C(8)))
//< f
962
963
/// \brief get AFRx mask for port bit \p p.
964
///
965
/// Normal use:
966
/// MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_GPIO_AFSEL_P(bitnum), 0..7)
967
///
968
#define MCCI_STM32L0_GPIO_AFSEL_P(p) (UINT32_C(0xF) << ((p) & 0x7u)
969
/// @}
970
971
/****************************************************************************\
972
|
973
| SPI Control Registers
974
|
975
\****************************************************************************/
976
977
/// \name SPI offsets
978
/// @{
979
#define MCCI_STM32L0_SPI_CR1 UINT32_C(0x00)
///< offset to SPI control register 1
980
#define MCCI_STM32L0_SPI_CR2 UINT32_C(0x04)
///< offset to SPI control register 2
981
#define MCCI_STM32L0_SPI_SR UINT32_C(0x08)
///< offset to SPI status register
982
#define MCCI_STM32L0_SPI_DR UINT32_C(0x0C)
///< offset to SPI data register
983
#define MCCI_STM32L0_SPI_CRCPR UINT32_C(0x10)
///< offset to SPI CRC polynomial
984
#define MCCI_STM32L0_SPI_RXCRCR UINT32_C(0x14)
///< offset to SPI receive CRC
985
#define MCCI_STM32L0_SPI_TXCRCR UINT32_C(0x18)
///< offset to SPI transmit CRC
986
#define MCCI_STM32L0_SPI_I2SCFGR UINT32_C(0x1C)
///< offset to SPI I2S config register
987
#define MCCI_STM32L0_SPI_I2SPR UINT32_C(0x20)
///< offset to SPI I2S prescaler
988
/// @}
989
990
/// \name SPI_CR1 bits
991
/// @{
992
#define MCCI_STM32L0_SPI_CR1_RSV16 UINT32_C(0xFFFF0000)
///< reserved
993
#define MCCI_STM32L0_SPI_CR1_BIDIMODE (UINT32_C(1) << 15)
///< Bidirectional mode
994
#define MCCI_STM32L0_SPI_CR1_BIDIOE (UINT32_C(1) << 14)
///< Bidirectional output enable
995
#define MCCI_STM32L0_SPI_CR1_CRCEN (UINT32_C(1) << 13)
///< CRC enabled
996
#define MCCI_STM32L0_SPI_CR1_CRCNEXT (UINT32_C(1) << 12)
///< CRC is next
997
#define MCCI_STM32L0_SPI_CR1_DFF (UINT32_C(1) << 11)
///< Data frame format (16 bit / not 8 bit)
998
#define MCCI_STM32L0_SPI_CR1_RXONLY (UINT32_C(1) << 10)
///< Receive-only mode
999
#define MCCI_STM32L0_SPI_CR1_SSM (UINT32_C(1) << 9)
///< software slave management
1000
#define MCCI_STM32L0_SPI_CR1_SSI (UINT32_C(1) << 8)
///< internal slave select
1001
#define MCCI_STM32L0_SPI_CR1_LSBFIRST (UINT32_C(1) << 7)
///< LSB first (not MSB)
1002
#define MCCI_STM32L0_SPI_CR1_SPE (UINT32_C(1) << 6)
///< SPI enabled
1003
1004
#define MCCI_STM32L0_SPI_CR1_BR (UINT32_C(7) << 3)
///< baud rate control (PCLK divisor)
1005
# define MCCI_STM32L0_SPI_CR1_BR_2 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 0)
///< PCLK/2
1006
# define MCCI_STM32L0_SPI_CR1_BR_4 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 1)
///< PCLK/4
1007
# define MCCI_STM32L0_SPI_CR1_BR_8 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 2)
///< PCLK/8
1008
# define MCCI_STM32L0_SPI_CR1_BR_16 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 3)
///< PCLK/16
1009
# define MCCI_STM32L0_SPI_CR1_BR_32 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 4)
///< PCLK/32
1010
# define MCCI_STM32L0_SPI_CR1_BR_64 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 5)
///< PCLK/64
1011
# define MCCI_STM32L0_SPI_CR1_BR_128 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 6)
///< PCLK/128
1012
# define MCCI_STM32L0_SPI_CR1_BR_256 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 7)
///< PCLK/256
1013
1014
#define MCCI_STM32L0_SPI_CR1_MSTR (UINT32_C(1) << 2)
///< Master (not slave)
1015
#define MCCI_STM32L0_SPI_CR1_CPOL (UINT32_C(1) << 1)
///< Clk to 1 when idle (not zero)
1016
#define MCCI_STM32L0_SPI_CR1_CPHA (UINT32_C(1) << 0)
///< Clock phase: second clock transaction captures (not first)
1017
/// @}
1018
1019
/// \name SPI_CR2 bits
1020
/// @{
1021
#define MCCI_STM32L0_SPI_CR2_RSV8 UINT32_C(0xFFFFFF00)
///< reserved
1022
#define MCCI_STM32L0_SPI_CR2_TXEIE (UINT32_C(1) << 7)
///< tx empty interrupt enable
1023
#define MCCI_STM32L0_SPI_CR2_RXNEIE (UINT32_C(1) << 6)
///< rx not empty interrupt enable
1024
#define MCCI_STM32L0_SPI_CR2_ERRIE (UINT32_C(1) << 5)
///< error interrupt enable
1025
#define MCCI_STM32L0_SPI_CR2_FRF (UINT32_C(1) << 4)
///< frame format TI (not Motorola)
1026
#define MCCI_STM32L0_SPI_CR2_RSV3 (UINT32_C(1) << 3)
///< reserved, zero
1027
#define MCCI_STM32L0_SPI_CR2_SSOE (UINT32_C(1) << 2)
///< enable SS in master mode
1028
#define MCCI_STM32L0_SPI_CR2_TXDMAEN (UINT32_C(1) << 1)
///< tx DMA enable
1029
#define MCCI_STM32L0_SPI_CR2_RXDMAEN (UINT32_C(1) << 0)
///< rx DMA enable
1030
/// @}
1031
1032
/// \name SPI_SR bits
1033
/// @{
1034
#define MCCI_STM32L0_SPI_SR_RSV9 UINT32_C(0xFFFFFE00)
///< reserved, zero
1035
#define MCCI_STM32L0_SPI_SR_FRE (UINT32_C(1) << 8)
///< frame error (read to clear)
1036
#define MCCI_STM32L0_SPI_SR_BSY (UINT32_C(1) << 7)
///< busy
1037
#define MCCI_STM32L0_SPI_SR_OVR (UINT32_C(1) << 6)
///< overrun
1038
#define MCCI_STM32L0_SPI_SR_MODF (UINT32_C(1) << 5)
///< mode fault
1039
#define MCCI_STM32L0_SPI_SR_CRCERR (UINT32_C(1) << 4)
///< CRC error (write zero to clear)
1040
#define MCCI_STM32L0_SPI_SR_UDR (UINT32_C(1) << 3)
///< underrun
1041
#define MCCI_STM32L0_SPI_SR_CHSIDE (UINT32_C(1) << 2)
///< channel right (not left)
1042
#define MCCI_STM32L0_SPI_SR_TXE (UINT32_C(1) << 1)
///< TX buffer empty
1043
#define MCCI_STM32L0_SPI_SR_RXNE (UINT32_C(1) << 0)
///< RX buffer not-empty
1044
/// @}
1045
1046
/// \name SPI_I2SCFGR bits
1047
/// @{
1048
#define MCCI_STM32L0_SPI_I2SCFGR_RSV13 UINT32_C(0xFFFFE000)
///< reserved (do not change)
1049
#define MCCI_STM32L0_SPI_I2SCFGR_I2SMOD (UINT32_C(1) << 11)
///< I2S mode (not SPI)
1050
#define MCCI_STM32L0_SPI_I2SCFGR_I2SE (UINT32_C(1) << 10)
///< I2S enable
1051
#define MCCI_STM32L0_SPI_I2SCFGR_I2SCFG (UINT32_C(3) << 8)
///< I2S configuration mode
1052
#define MCCI_STM32L0_SPI_I2SCFGR_I2SCFG_STX MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SCFG, 0)
///< I2S slave transmit
1053
#define MCCI_STM32L0_SPI_I2SCFGR_I2SCFG_SRX MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SCFG, 1)
///< I2S slave receive
1054
#define MCCI_STM32L0_SPI_I2SCFGR_I2SCFG_MTX MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SCFG, 2)
///< I2S master transmit
1055
#define MCCI_STM32L0_SPI_I2SCFGR_I2SCFG_MRX MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SCFG, 3)
///< I2S master receive
1056
#define MCCI_STM32L0_SPI_I2SCFGR_PCMSYNC (UINT32_C(1) << 7)
///< Long (not short) PCM frame synchronization
1057
#define MCCI_STM32L0_SPI_I2SCFGR_RSV6 (UINT32_C(1) << 6)
///< reserved, zero
1058
#define MCCI_STM32L0_SPI_I2SCFGR_I2SSTD (UINT32_C(3) << 4)
///< I2S standard selection
1059
#define MCCI_STM32L0_SPI_I2SCFGR_I2SSTD_PHILIPS MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SSTD, 0)
///< Philips standard.
1060
#define MCCI_STM32L0_SPI_I2SCFGR_I2SSTD_LEFT MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SSTD, 1)
///< MSB justified
1061
#define MCCI_STM32L0_SPI_I2SCFGR_I2SSTD_RIGHT MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SSTD, 2)
///< LSB justified
1062
#define MCCI_STM32L0_SPI_I2SCFGR_I2SSTD_PCM MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SSTD, 3)
///< PCM standard
1063
#define MCCI_STM32L0_SPI_I2SCFGR_CKPOL (UINT32_C(1) << 3)
///< steady state clock polarity high (not low)
1064
#define MCCI_STM32L0_SPI_I2SCFGR_DATLEN (UINT32_C(3) << 1)
///< data length
1065
#define MCCI_STM32L0_SPI_I2SCFGR_DATLEN_16 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_DATLEN, 0)
///< 16-bit data
1066
#define MCCI_STM32L0_SPI_I2SCFGR_DATLEN_24 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_DATLEN, 1)
///< 24-bit data
1067
#define MCCI_STM32L0_SPI_I2SCFGR_DATLEN_32 MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_DATLEN, 2)
///< 32-bit data
1068
#define MCCI_STM32L0_SPI_I2SCFGR_DATLEN_XX MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_DATLEN, 3)
///< invalid data length
1069
#define MCCI_STM32L0_SPI_I2SCFGR_CHLEN (UINT32_C(1) << 0)
///< channel 32-bits wide (not 16)
1070
/// @}
1071
1072
1073
#ifdef __cplusplus
1074
}
1075
#endif
1076
1077
#endif
/* _mcci_stm32l0xx_h_ */
mcci_arm_cm0plus.h
mcci_bootloader_bits.h
platform
soc
stm32l0
i
mcci_stm32l0xx.h
Generated on Thu Feb 19 2026 18:47:32 for MCCI Trusted Bootloader by
1.9.8
1.9.8