mcci_stm32l0xx.h File Reference

#include "mcci_bootloader_bits.h"
#include "mcci_arm_cm0plus.h"
#include <stdint.h>

Go to the source code of this file.

Macros
#define	_mcci_stm32l0xx_h_   /* prevent multiple includes */
#define	MCCI_STM32L0_GPIO_MODE_P(p)   (UINT32_C(3) << (2 * (p)))
	compute the mask for the mode bits for port bits 0..15
#define	MCCI_STM32L0_GPIO_OTYPE_P(p)   (UINT32_C(1) << (p))
	compute the mask for the mode bits for port bits 0..15
#define	MCCI_STM32L0_GPIO_OTYPE_PV(p, v)   (((v) & 1u) << (p))
	directly compute a GPIO OTYPE mask
STM32L0xx top-level address breakdown
#define	MCCI_STM32L0_MEMORY_EEPROM   UINT32_C(0x08080000)
	Data EEPROM (up to 6K)
#define	MCCI_STM32L0_MEMORY_FLASH   UINT32_C(0x08000000)
	Flash program memory (up to 192K)
#define	MCCI_STM32L0_MEMORY_SRAM   UINT32_C(0x20000000)
	SRAM (up to 20K)
#define	MCCI_STM32L0_MEMORY_SYSTEM   UINT32_C(0x1FF00000)
	System memory (8K)
#define	MCCI_STM32L0_OPTIONS_FACTORY   UINT32_C(0x1FF80020)
	Factory option bytes (96)
#define	MCCI_STM32L0_OPTIONS_USER   UINT32_C(0x1FF80000)
	User option bytes (32)
#define	MCCI_STM32L0_REG_ADC1   UINT32_C(0x40012400)
	Section 14.12.12: ADC register map (1K)
#define	MCCI_STM32L0_REG_AES   UINT32_C(0x40026000)
	Section 18.12.13: AES register map (1K)
#define	MCCI_STM32L0_REG_CRC   UINT32_C(0x40023000)
	Section 4.4.6: CRC register map (1K)
#define	MCCI_STM32L0_REG_CRS   UINT32_C(0x40006C00)
	Section 8.6.5: CRS register map (1K)
#define	MCCI_STM32L0_REG_DAC1   UINT32_C(0x40007400)
	Section 15.10.15: DAC register map (1K)
#define	MCCI_STM32L0_REG_DBG   UINT32_C(0x40015800)
	Section 32.10: DBG register map (1K)
#define	MCCI_STM32L0_REG_DMA1   UINT32_C(0x40020000)
	Section 11.4.8: DMA register map (1K)
#define	MCCI_STM32L0_REG_EXTI   UINT32_C(0x40010400)
	Section 13.5.7: EXTI register map (1K)
#define	MCCI_STM32L0_REG_FIREWALL   UINT32_C(0x40011C00)
	Section 5.4.8: Firewall register map (1K)
#define	MCCI_STM32L0_REG_FLASH   UINT32_C(0x40022000)
	Section 3.7.11: Flash register map (1K)
#define	MCCI_STM32L0_REG_GPIOA   UINT32_C(0x50000000)
	Section 9.4.12: GPIO register map (1K)
#define	MCCI_STM32L0_REG_GPIOB   UINT32_C(0x50000400)
	Section 9.4.12: GPIO register map (1K)
#define	MCCI_STM32L0_REG_GPIOC   UINT32_C(0x50000800)
	Section 9.4.12: GPIO register map (1K)
#define	MCCI_STM32L0_REG_GPIOD   UINT32_C(0x50000C00)
	Section 9.4.12: GPIO register map (1K)
#define	MCCI_STM32L0_REG_GPIOE   UINT32_C(0x50001000)
	Section 9.4.12: GPIO register map (1K)
#define	MCCI_STM32L0_REG_GPIOH   UINT32_C(0x50001C00)
	Section 9.4.12: GPIO register map (1K)
#define	MCCI_STM32L0_REG_I2C1   UINT32_C(0x40005400)
	Section 27.7.12: I2C register map (1K)
#define	MCCI_STM32L0_REG_I2C2   UINT32_C(0x40005800)
	Section 27.7.12: I2C register map (1K)
#define	MCCI_STM32L0_REG_I2C3   UINT32_C(0x40007800)
	Section 27.7.12: I2C register map (1K)
#define	MCCI_STM32L0_REG_IWDG   UINT32_C(0x40003000)
	Section 24.4.6: IWDG register map (1K)
#define	MCCI_STM32L0_REG_LPTIM1   UINT32_C(0x40007C00)
	Section 23.6.9: LPTIM register map (1K)
#define	MCCI_STM32L0_REG_LPUART1   UINT32_C(0x40004800)
	Section 29.7.10: LPUART register map (1K)
#define	MCCI_STM32L0_REG_PWR   UINT32_C(0x40007000)
	Section 6.4.3: PWR register map (1K)
#define	MCCI_STM32L0_REG_RCC   UINT32_C(0x40021000)
	Section 7.3.22: RCC register map (1K)
#define	MCCI_STM32L0_REG_RNG   UINT32_C(0x40025000)
	Section 19.8.4: RNG register map (1K)
#define	MCCI_STM32L0_REG_RTC   UINT32_C(0x40002800)
	Section 26.7.21: RTC + BKUP register map (1K)
#define	MCCI_STM32L0_REG_SPI1   UINT32_C(0x40013000)
	Section 30.7.10: SPI register map (1K)
#define	MCCI_STM32L0_REG_SPI2   UINT32_C(0x40003800)
	Section 30.7.10: SPI register map (1K)
#define	MCCI_STM32L0_REG_SYSCFG_COMP   UINT32_C(0x40010000)
	Section 10.2.8: SYSCFG register map, Section 16.5.3: COMP register map (1K)
#define	MCCI_STM32L0_REG_TIM21   UINT32_C(0x40010800)
	Section 21.4.16: TIM21/22 register map (1K)
#define	MCCI_STM32L0_REG_TIM22   UINT32_C(0x40011400)
	Section 21.4.16: TIM21/22 register map (1K)
#define	MCCI_STM32L0_REG_TIMER2   UINT32_C(0x40000000)
	Section 20.5: TIMx register map (1K)
#define	MCCI_STM32L0_REG_TIMER3   UINT32_C(0x40000400)
	Section 20.5: TIMx register map (1K)
#define	MCCI_STM32L0_REG_TIMER6   UINT32_C(0x40001000)
	Section 22.4.9: TIM6/7 register map (1K)
#define	MCCI_STM32L0_REG_TIMER7   UINT32_C(0x40001400)
	Section 22.4.9: TIM6/7 register map (1K)
#define	MCCI_STM32L0_REG_TSC   UINT32_C(0x40024000)
	Section 17.6.11: TSC register map (1K)
#define	MCCI_STM32L0_REG_USART1   UINT32_C(0x40013800)
	Section 28.8.12: USART register map (1K)
#define	MCCI_STM32L0_REG_USART2   UINT32_C(0x40004400)
	Section 28.8.12: USART register map (1K)
#define	MCCI_STM32L0_REG_USART4   UINT32_C(0x40004C00)
	Section 28.8.12: USART register map (1K)
#define	MCCI_STM32L0_REG_USART5   UINT32_C(0x40005000)
	Section 28.8.12: USART register map (1K)
#define	MCCI_STM32L0_REG_USB_FS   UINT32_C(0x40005C00)
	Section 31.6.3: USB register map (1K)
#define	MCCI_STM32L0_REG_USB_SRAM   UINT32_C(0x40006000)
	USB (SRAM 512x16bit) (2K)
#define	MCCI_STM32L0_REG_WWDG   UINT32_C(0x40002C00)
	Section 25.4.4: WWDG register map (1K)
User option bytes
#define	MCCI_STM32L0_OPTIONS_MAKE_DWORD(v)   ((~(uint32_t)(v) << 16) | (uint16_t)(v))
	create an option dword from a 16-bit value (high 16 bits inverted copy of low)
#define	MCCI_STM32L0_OPTIONS_USER_FLASH_OPTR_HIGH   (MCCI_STM32L0_OPTIONS_USER + 0x04)
#define	MCCI_STM32L0_OPTIONS_USER_FLASH_OPTR_LOW   (MCCI_STM32L0_OPTIONS_USER + 0x00)
#define	MCCI_STM32L0_OPTIONS_USER_FLASH_WRPROT1_HIGH   (MCCI_STM32L0_OPTIONS_USER + 0x0C)
#define	MCCI_STM32L0_OPTIONS_USER_FLASH_WRPROT1_LOW   (MCCI_STM32L0_OPTIONS_USER + 0x08)
#define	MCCI_STM32L0_OPTIONS_USER_FLASH_WRPROT2   (MCCI_STM32L0_OPTIONS_USER + 0x10)
System values in system option memory
#define	MCCI_STM32L0_OPTIONS_SYSTEM_FLASH_SIZE_16   UINT32_C(0x1FF8007C)
	memory size in k bytes (16 bits)
#define	MCCI_STM32L0_OPTIONS_SYSTEM_FLASH_SIZE_TO_BYTES(h)    (((h) & UINT32_C(0xFFFF)) * 1024)
	convert flash_size_16 value to bytes
#define	MCCI_STM32L0_OPTIONS_U_ID_0   UINT32_C(0x1FF80050)
	register address: unique ID bits 31:0
#define	MCCI_STM32L0_OPTIONS_U_ID_4   (MCCI_STM32L0_OPTIONS_U_ID_0 + 0x04)
	register address: unique ID bits 63:32
#define	MCCI_STM32L0_OPTIONS_U_ID_8   (MCCI_STM32L0_OPTIONS_U_ID_0 + 0x014)
	register address: unique ID bits 95:64
FLASH registers
#define	MCCI_STM32L0_REG_FLASH_ACR   (MCCI_STM32L0_REG_FLASH + 0x00)
	Flash access control register.
#define	MCCI_STM32L0_REG_FLASH_OPTKEYR   (MCCI_STM32L0_REG_FLASH + 0x14)
	Flash option bytes unlock key register.
#define	MCCI_STM32L0_REG_FLASH_OPTR   (MCCI_STM32L0_REG_FLASH + 0x1C)
	Flash option bytes register.
#define	MCCI_STM32L0_REG_FLASH_PDKEYR   (MCCI_STM32L0_REG_FLASH + 0x08)
	Flash power-down key register.
#define	MCCI_STM32L0_REG_FLASH_PECR   (MCCI_STM32L0_REG_FLASH + 0x04)
	Flash program and erase control register.
#define	MCCI_STM32L0_REG_FLASH_PEKEYR   (MCCI_STM32L0_REG_FLASH + 0x0C)
	Flash PECR unlock key register.
#define	MCCI_STM32L0_REG_FLASH_PRGKEYR   (MCCI_STM32L0_REG_FLASH + 0x10)
	Flash program/erase key register.
#define	MCCI_STM32L0_REG_FLASH_SR   (MCCI_STM32L0_REG_FLASH + 0x18)
	Flash status register.
#define	MCCI_STM32L0_REG_FLASH_WPROT1   (MCCI_STM32L0_REG_FLASH + 0x20)
	Flash write proection register 1.
#define	MCCI_STM32L0_REG_FLASH_WPROT2   (MCCI_STM32L0_REG_FLASH + 0x80)
	Flash write protection register 2.
FLASH_ACR bits
#define	MCCI_STM32L0_REG_FLASH_ACR_DISAB_BUF   (UINT32_C(1) << 5)
	Disable read buffer.
#define	MCCI_STM32L0_REG_FLASH_ACR_LATENCY   (UINT32_C(1) << 0)
	NVM latency: 1 wait state (not zero wait state)
#define	MCCI_STM32L0_REG_FLASH_ACR_PRE_READ   (UINT32_C(1) << 6)
	Enable pre-read.
#define	MCCI_STM32L0_REG_FLASH_ACR_PRFTEN   (UINT32_C(1) << 1)
	prefetch enable
#define	MCCI_STM32L0_REG_FLASH_ACR_RSV2   (UINT32_C(1) << 2)
	Reserved, don't change.
#define	MCCI_STM32L0_REG_FLASH_ACR_RSV7   UINT32_C(0xFFFFFF80)
	Reserved, don't change.
#define	MCCI_STM32L0_REG_FLASH_ACR_RUN_PD   (UINT32_C(1) << 4)
	power-down in run mode
#define	MCCI_STM32L0_REG_FLASH_ACR_SLEEP_PD   (UINT32_C(1) << 3)
	power-down in sleep mode
FLASH_PECR bits
#define	MCCI_STM32L0_REG_FLASH_PECR_DATA   (UINT32_C(1) << 4)
	Select data memory.
#define	MCCI_STM32L0_REG_FLASH_PECR_EOPIE   (UINT32_C(1) << 16)
	End of programming interrupt enable.
#define	MCCI_STM32L0_REG_FLASH_PECR_ERASE   (UINT32_C(1) << 9)
	Erase operation requested/not requested.
#define	MCCI_STM32L0_REG_FLASH_PECR_ERRIE   (UINT32_C(1) << 17)
	Error interrupt enable.
#define	MCCI_STM32L0_REG_FLASH_PECR_FIX   (UINT32_C(1) << 8)
	Atomatically erase before programming EEPROM and options.
#define	MCCI_STM32L0_REG_FLASH_PECR_FPRG   (UINT32_C(1) << 10)
	Enable half-page programming mode.
#define	MCCI_STM32L0_REG_FLASH_PECR_NZDISABLE   (UINT32_C(1) << 23)
	Disable non-zero check.
#define	MCCI_STM32L0_REG_FLASH_PECR_OBL_LAUNCH   (UINT32_C(1) << 18)
	Reload option bytes and reset system.
#define	MCCI_STM32L0_REG_FLASH_PECR_OPTLOCK   (UINT32_C(1) << 2)
	Lock option bytes.
#define	MCCI_STM32L0_REG_FLASH_PECR_PARALLELBANK   (UINT32_C(1) << 15)
	Parallel bank programming enable.
#define	MCCI_STM32L0_REG_FLASH_PECR_PELOCK   (UINT32_C(1) << 0)
	Lock the FLASH_PECR register.
#define	MCCI_STM32L0_REG_FLASH_PECR_PRGLOCK   (UINT32_C(1) << 1)
	Lock program memory.
#define	MCCI_STM32L0_REG_FLASH_PECR_PROG   (UINT32_C(1) << 3)
	Select program memory.
#define	MCCI_STM32L0_REG_FLASH_PECR_RSV11   (UINT32_C(0xF) << 11)
	Reserved, don't change.
#define	MCCI_STM32L0_REG_FLASH_PECR_RSV19   (UINT32_C(0xF) << 19)
	Reserved, don't change.
#define	MCCI_STM32L0_REG_FLASH_PECR_RSV24   UINT32_C(0xFF000000)
	Reserved, don't change.
#define	MCCI_STM32L0_REG_FLASH_PECR_RSV5   (UINT32_C(7) << 5)
	Reserved, don't change.
FLASH_PDKEYR bits
#define	MCCI_STM32L0_REG_FLASH_PDKEYR_UNLOCK1   UINT32_C(0x04152637)
	unlock word 1 for RUN_PD
#define	MCCI_STM32L0_REG_FLASH_PDKEYR_UNLOCK2   UINT32_C(0xFAFBFCFD)
	unlock word 2 for RUN_PD
FLASH_PEKEYR bits
#define	MCCI_STM32L0_REG_FLASH_PEKEYR_UNLOCK1   UINT32_C(0x89ABCDEF)
	unlock word 1 for PECR
#define	MCCI_STM32L0_REG_FLASH_PEKEYR_UNLOCK2   UINT32_C(0x02030405)
	unlock word 2 for PECR
FLASH_PRGKEYR bits
#define	MCCI_STM32L0_REG_FLASH_PRGKEYR_UNLOCK1   UINT32_C(0x8C9DAEBF)
	unlock word 1 for PRGKEYR
#define	MCCI_STM32L0_REG_FLASH_PRGKEYR_UNLOCK2   UINT32_C(0x13141516)
	unlock word 2 for PRGKEYR
FLASH_OPTKEYR bits
#define	MCCI_STM32L0_REG_FLASH_OPTKEYR_UNLOCK1   UINT32_C(0xFBEAD9C8)
	unlock word 1 for option bytes
#define	MCCI_STM32L0_REG_FLASH_OPTKEYR_UNLOCK2   UINT32_C(0x24252627)
	unlock word 2 for option bytes
FLASH_SR bits
#define	MCCI_STM32L0_REG_FLASH_SR_BSY   (UINT32_C(1) << 0)
	Busy doing write/erase.
#define	MCCI_STM32L0_REG_FLASH_SR_ENDHV   (UINT32_C(1) << 2)
	High voltage is off (not on), not active.
#define	MCCI_STM32L0_REG_FLASH_SR_EOP   (UINT32_C(1) << 1)
	End of program.
#define	MCCI_STM32L0_REG_FLASH_SR_FWWERR   (UINT32_C(1) << 17)
	Write/erase aborted for fetch.
#define	MCCI_STM32L0_REG_FLASH_SR_NOTZEROERR   (UINT32_C(1) << 16)
	Attempt to program non-zero area.
#define	MCCI_STM32L0_REG_FLASH_SR_OPTVERR   (UINT32_C(1) << 11)
	Option valid error.
#define	MCCI_STM32L0_REG_FLASH_SR_PGAERR   (UINT32_C(1) << 9)
	Programming alignment error.
#define	MCCI_STM32L0_REG_FLASH_SR_RDERR   (UINT32_C(1) << 13)
	Read-protection error.
#define	MCCI_STM32L0_REG_FLASH_SR_READY   (UINT32_C(1) << 3)
	NVM is ready.
#define	MCCI_STM32L0_REG_FLASH_SR_RSV12   (UINT32_C(1) << 12)
	Reserved, don't change.
#define	MCCI_STM32L0_REG_FLASH_SR_RSV14   (UINT32_C(3) << 14)
	Reserved, don't change.
#define	MCCI_STM32L0_REG_FLASH_SR_RSV18   UINT32_C(0xFFFC0000)
	Reserved, don't change.
#define	MCCI_STM32L0_REG_FLASH_SR_RSV4   (UINT32_C(0xF) << 4)
	Reserved, don't change.
#define	MCCI_STM32L0_REG_FLASH_SR_SIZERR   (UINT32_C(1) << 10)
	Size error when programming.
#define	MCCI_STM32L0_REG_FLASH_SR_WRPERR   (UINT32_C(1) << 8)
	write protection error.
FLASH_OPTR bits
#define	MCCI_STM32L0_FLASH_OPTR_RDPROT_IS_L0(v)    ((v) & MCCI_STM32L0_REG_FLASH_OPTR_RDPROT) == MCCI_STM32L0_REG_FLASH_OPTR_RDPROT_L0)
	given image of FLASH_OPTR, return true if set for level 0 protection
#define	MCCI_STM32L0_FLASH_OPTR_RDPROT_IS_L1(v)    (! (MCCI_STM32L0_FLASH_OPTR_RDPROT_IS_L0(v) || MCCI_STM32L0_FLASH_OPTR_RDPROT_IS_L2(v)))
	given image of FLASH_OPTR, return true if set for level 1 protection
#define	MCCI_STM32L0_FLASH_OPTR_RDPROT_IS_L2(v)    ((v) & MCCI_STM32L0_REG_FLASH_OPTR_RDPROT) == MCCI_STM32L0_REG_FLASH_OPTR_RDPROT_L0)
	given image of FLASH_OPTR, return true if set for level 2 protection
#define	MCCI_STM32L0_REG_FLASH_OPTR_BFB2   (UINT32_C(1) << 23)
	Boot from system memory (not bank 2)
#define	MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV   (UINT32_C(0xF) << 16)
	brown-out reset level
#define	MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV_1v8   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV, 8)
	Level 1 (1.8 V)
#define	MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV_2v0   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV, 9)
	Level 2 (2.0 V)
#define	MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV_2v5   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV, 10)
	Level 3 (2.5 V)
#define	MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV_2v7   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV, 11)
	Level 4 (2.7 V)
#define	MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV_3v0   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV, 12)
	Level 5 (3.0 V)
#define	MCCI_STM32L0_REG_FLASH_OPTR_nBOOT1   (UINT32_C(1) << 31)
	If boot0, boot from system rom (not RAM)
#define	MCCI_STM32L0_REG_FLASH_OPTR_nRST_STDBY   (UINT32_C(1) << 22)
	do not generate reset when entering standby
#define	MCCI_STM32L0_REG_FLASH_OPTR_nRST_STOP   (UINT32_C(1) << 21)
	do not generate reset when entering stop
#define	MCCI_STM32L0_REG_FLASH_OPTR_RDPROT   (UINT32_C(0xFF) << 0)
	Read protection level.
#define	MCCI_STM32L0_REG_FLASH_OPTR_RDPROT_L0   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_RDPROT, 0xAA)
#define	MCCI_STM32L0_REG_FLASH_OPTR_RDPROT_L1   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_RDPROT, 0x0)
#define	MCCI_STM32L0_REG_FLASH_OPTR_RDPROT_L2   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_RDPROT, 0xCC)
#define	MCCI_STM32L0_REG_FLASH_OPTR_RSV24   (UINT32_C(0x7F) << 24)
	Reserved, don't change.
#define	MCCI_STM32L0_REG_FLASH_OPTR_RSV9   (UINT32_C(0x7F) << 9)
	Reserved, don't change.
#define	MCCI_STM32L0_REG_FLASH_OPTR_WDG_SW   (UINT32_C(1) << 20)
	software (not hardware) watchdog
#define	MCCI_STM32L0_REG_FLASH_OPTR_WPRMOD   (UINT32_C(1) << 8)
	PCROP enabled (use WPROT for read protection)
FLASH_WPROT1, FLASH_WPROT2 bits
#define	MCCI_STM32L0_FLASH_ADDRESS_GET_SECTOR(a)    (((uint32_t)(a) - MCCI_STM32L0_MEMORY_FLASH) >> MCCI_BOOTLOADER_FIELD_SHIFT(MCCI_STM32L0_FLASH_SECTOR_SIZE))
	given a flash address, convert to sector number
#define	MCCI_STM32L0_FLASH_SECTOR_SIZE   UINT32_C(4096)
	size in bytes of a flash sector
#define	MCCI_STM32L0_FLASH_WPROT_MASK_FOR_SECTOR(s)   (UINT32_C(1) << ((s) & 0x1F))
	get mask for sector s.
#define	MCCI_STM32L0_REG_FLASH_WPROTx_FOR_SECTOR(s)   ((s) < 32 ? MCCI_STM32L0_REG_FLASH_WPROT1 : MCCI_STM32L0_REG_FLASH_WPROT2)
	get reg offset for protection bit for sector s
Flash programming constants
#define	MCCI_STM32L0_FLASH_HALF_PAGE_SIZE   UINT32_C(64)
	size in bytes of a half-page
#define	MCCI_STM32L0_FLASH_PAGE_SIZE   UINT32_C(128)
	size in bytes of a page
PWR registers
#define	MCCI_STM32L0_REG_PWR_CR   (MCCI_STM32L0_REG_PWR + 0x0)
#define	MCCI_STM32L0_REG_PWR_CSR   (MCCI_STM32L0_REG_PWR + 0x4)
PWR_CR bits
#define	MCCI_STM32L0_REG_PWR_CR_CSBF   (UINT32_C(1) << 3)
	clear the SBF standby flag
#define	MCCI_STM32L0_REG_PWR_CR_CWUF   (UINT32_C(1) << 2)
	clear the wakeup flag
#define	MCCI_STM32L0_REG_PWR_CR_DBP   (UINT32_C(1) << 8)
	disable backup write protection
#define	MCCI_STM32L0_REG_PWR_CR_DS_EE_KOFF   (UINT32_C(1) << 13)
	deep sleep mode with nv mem off
#define	MCCI_STM32L0_REG_PWR_CR_FWU   (UINT32_C(1) << 10)
	fast wakeup
#define	MCCI_STM32L0_REG_PWR_CR_LPRUN   (UINT32_C(1) << 14)
	Low power run mode.
#define	MCCI_STM32L0_REG_PWR_CR_LPSDSR   (UINT32_C(1) << 0)
	low-power deep sleep/sleep/low-power run
#define	MCCI_STM32L0_REG_PWR_CR_PDDS   (UINT32_C(1) << 1)
	power-down deep sleep
#define	MCCI_STM32L0_REG_PWR_CR_PLS   (UINT32_C(7) << 5)
	power voltage detector level
#define	MCCI_STM32L0_REG_PWR_CR_PLS_1V9   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 0)
	1.9 V
#define	MCCI_STM32L0_REG_PWR_CR_PLS_2V1   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 1)
	2.1 V
#define	MCCI_STM32L0_REG_PWR_CR_PLS_2V3   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 2)
	2.3 V
#define	MCCI_STM32L0_REG_PWR_CR_PLS_2V5   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 3)
	2.5 V
#define	MCCI_STM32L0_REG_PWR_CR_PLS_2V7   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 4)
	2.7 V
#define	MCCI_STM32L0_REG_PWR_CR_PLS_2V9   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 5)
	2.9 V
#define	MCCI_STM32L0_REG_PWR_CR_PLS_3V1   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 6)
	3.1 V
#define	MCCI_STM32L0_REG_PWR_CR_PLS_EXT   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 7)
	Vrefint.
#define	MCCI_STM32L0_REG_PWR_CR_PVDE   (UINT32_C(1) << 4)
	power voltage detector enabled
#define	MCCI_STM32L0_REG_PWR_CR_ULP   (UINT32_C(1) << 9)
	ultra low-power mode
#define	MCCI_STM32L0_REG_PWR_CR_VOS   (UINT32_C(3) << 11)
	voltage scaling range
#define	MCCI_STM32L0_REG_PWR_CR_VOS_1V2   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_VOS, 3)
	1.2V
#define	MCCI_STM32L0_REG_PWR_CR_VOS_1V5   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_VOS, 2)
	1.5V
#define	MCCI_STM32L0_REG_PWR_CR_VOS_1V8   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_VOS, 1)
	1.8V
#define	MCCI_STM32L0_REG_PWR_CR_VOS_NC   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_VOS, 0)
	no change / not allowed
PWR_SCR bits
#define	MCCI_STM32L0_REG_PWR_CSR_EWUP1   (UINT32_C(1) << 8)
	Enable WKUP pin 1.
#define	MCCI_STM32L0_REG_PWR_CSR_EWUP2   (UINT32_C(1) << 9)
	Enable WKUP pin 2.
#define	MCCI_STM32L0_REG_PWR_CSR_EWUP3   (UINT32_C(1) << 10)
	Enable WKUP pin 3.
#define	MCCI_STM32L0_REG_PWR_CSR_PVDO   (UINT32_C(1) << 2)
	PVD output.
#define	MCCI_STM32L0_REG_PWR_CSR_REGLPF   (UINT32_C(1) << 5)
	Regulator low-power flag.
#define	MCCI_STM32L0_REG_PWR_CSR_RSV11   UINT32C(0xFFFFF800)
	reserved, do not change
#define	MCCI_STM32L0_REG_PWR_CSR_RSV6   (UINT32_C(3) << 6)
	Reserved, do not change.
#define	MCCI_STM32L0_REG_PWR_CSR_SBF   (UINT32_C(1) << 1)
	Standby flag.
#define	MCCI_STM32L0_REG_PWR_CSR_VOSF   (UINT32_C(1) << 4)
	Voltage scaling select flag.
#define	MCCI_STM32L0_REG_PWR_CSR_VREFINTRDYF   (UINT32_C(1) << 3)
	Vrefint ready flag.
#define	MCCI_STM32L0_REG_PWR_CSR_WUF   (UINT32_C(1) << 0)
	Wakeup flag.
RCC registers
#define	MCCI_STM32L0_REG_RCC_AHBENR   (MCCI_STM32L0_REG_RCC + 0x30)
	AHB peripheral clock enable.
#define	MCCI_STM32L0_REG_RCC_AHBRSTR   (MCCI_STM32L0_REG_RCC + 0x20)
	AHB peripheral reset.
#define	MCCI_STM32L0_REG_RCC_AHBSMENR   (MCCI_STM32L0_REG_RCC + 0x40)
	AHB peripheral clock enable in sleep.
#define	MCCI_STM32L0_REG_RCC_APB1ENR   (MCCI_STM32L0_REG_RCC + 0x38)
	APB1 peripheral clock enable.
#define	MCCI_STM32L0_REG_RCC_APB1RSTR   (MCCI_STM32L0_REG_RCC + 0x28)
	APB1 peripheral reset.
#define	MCCI_STM32L0_REG_RCC_APB1SMENR   (MCCI_STM32L0_REG_RCC + 0x48)
	APB1 peripheral clock enable in sleep.
#define	MCCI_STM32L0_REG_RCC_APB2ENR   (MCCI_STM32L0_REG_RCC + 0x34)
	APB2 peripheral clock enable.
#define	MCCI_STM32L0_REG_RCC_APB2RSTR   (MCCI_STM32L0_REG_RCC + 0x24)
	APB2 peripheral reset.
#define	MCCI_STM32L0_REG_RCC_APB2SMENR   (MCCI_STM32L0_REG_RCC + 0x44)
	APB2 peripheral clock enable in sleep.
#define	MCCI_STM32L0_REG_RCC_CCIPR   (MCCI_STM32L0_REG_RCC + 0x4C)
	Clock configuration CCIPR.
#define	MCCI_STM32L0_REG_RCC_CFGR   (MCCI_STM32L0_REG_RCC + 0x0C)
	Clock configuration.
#define	MCCI_STM32L0_REG_RCC_CICR   (MCCI_STM32L0_REG_RCC + 0x18)
	Clock interrupt clear.
#define	MCCI_STM32L0_REG_RCC_CIER   (MCCI_STM32L0_REG_RCC + 0x10)
	Clock interrupt enable.
#define	MCCI_STM32L0_REG_RCC_CIFR   (MCCI_STM32L0_REG_RCC + 0x14)
	Clock interrupt flag.
#define	MCCI_STM32L0_REG_RCC_CR   (MCCI_STM32L0_REG_RCC + 0x00)
	Clock control.
#define	MCCI_STM32L0_REG_RCC_CRRCR   (MCCI_STM32L0_REG_RCC + 0x08)
	Clock recovery RC.
#define	MCCI_STM32L0_REG_RCC_CSR   (MCCI_STM32L0_REG_RCC + 0x50)
	Control/status.
#define	MCCI_STM32L0_REG_RCC_ICSCR   (MCCI_STM32L0_REG_RCC + 0x04)
	Internal clock sources calibration.
#define	MCCI_STM32L0_REG_RCC_IOPENR   (MCCI_STM32L0_REG_RCC + 0x2C)
	GPIO clock enable.
#define	MCCI_STM32L0_REG_RCC_IOPRSTR   (MCCI_STM32L0_REG_RCC + 0x1C)
	GPIO reset.
#define	MCCI_STM32L0_REG_RCC_IOPSMEN   (MCCI_STM32L0_REG_RCC + 0x3C)
	GPIO clock enable in sleep.
RCC_CR bits
#define	MCCI_STM32L0_REG_RCC_CR_CSSHSEON   (UINT32_C(1) << 19)
#define	MCCI_STM32L0_REG_RCC_CR_HSEBYP   (UINT32_C(1) << 18)
#define	MCCI_STM32L0_REG_RCC_CR_HSEON   (UINT32_C(1) << 16)
#define	MCCI_STM32L0_REG_RCC_CR_HSERDY   (UINT32_C(1) << 17)
#define	MCCI_STM32L0_REG_RCC_CR_HSI16DIVEN   (UINT32_C(1) << 3)
#define	MCCI_STM32L0_REG_RCC_CR_HSI16DIVF   (UINT32_C(1) << 4)
#define	MCCI_STM32L0_REG_RCC_CR_HSI16KERON   (UINT32_C(1) << 1)
#define	MCCI_STM32L0_REG_RCC_CR_HSI16ON   (UINT32_C(1) << 0)
#define	MCCI_STM32L0_REG_RCC_CR_HSI16OUTEN   (UINT32_C(1) << 5)
#define	MCCI_STM32L0_REG_RCC_CR_HSI16RDYF   (UINT32_C(1) << 2)
#define	MCCI_STM32L0_REG_RCC_CR_MSION   (UINT32_C(1) << 8)
#define	MCCI_STM32L0_REG_RCC_CR_MSIRDY   (UINT32_C(1) << 9)
#define	MCCI_STM32L0_REG_RCC_CR_PLLON   (UINT32_C(1) << 24)
#define	MCCI_STM32L0_REG_RCC_CR_PLLRDY   (UINT32_C(1) << 25)
#define	MCCI_STM32L0_REG_RCC_CR_RSV10   UINT32_C(0x0000FC00)
#define	MCCI_STM32L0_REG_RCC_CR_RSV22   (UINT32_C(3) << 22)
#define	MCCI_STM32L0_REG_RCC_CR_RSV26   UINT32_C(0xFC000000)
#define	MCCI_STM32L0_REG_RCC_CR_RSV6   (UINT32_C(3) << 6)
#define	MCCI_STM32L0_REG_RCC_CR_RTCPRE   (UINT32_C(3) << 20)
#define	MCCI_STM32L0_REG_RCC_CR_RTCPRE_16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLSMCCI_STM32L0_REG_RCC_CR_RTCPRE, 3)
#define	MCCI_STM32L0_REG_RCC_CR_RTCPRE_2   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLSMCCI_STM32L0_REG_RCC_CR_RTCPRE, 0)
#define	MCCI_STM32L0_REG_RCC_CR_RTCPRE_4   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLSMCCI_STM32L0_REG_RCC_CR_RTCPRE, 1)
#define	MCCI_STM32L0_REG_RCC_CR_RTCPRE_8   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLSMCCI_STM32L0_REG_RCC_CR_RTCPRE, 2)
RCC_ICSCR bits
#define	MCCI_STM32L0_REG_RCC_ICSCR_HSI16CAL   (UINT32_C(0xFF) << 0)
#define	MCCI_STM32L0_REG_RCC_ICSCR_HSI16TRIM   (UINT32_C(0x1F) << 8)
#define	MCCI_STM32L0_REG_RCC_ICSCR_MSICAL   (UINT32_C(0xFF) << 16)
#define	MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE   (UINT32_C(7) << 13)
#define	MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_1048k   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 4)
#define	MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_131k   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 1)
#define	MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_2097k   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 5)
#define	MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_262k   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 2)
#define	MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_4194k   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 6)
#define	MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_524k   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 3)
#define	MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_65k   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 0)
#define	MCCI_STM32L0_REG_RCC_ICSCR_MSITRIM   (UINT32_C(0xFF) << 24)
RCC_CRRCR bits
#define	MCCI_STM32L0_REG_RCC_CRRCR_HSI48CAL   (UINT32_C(0xFF) << 8)
#define	MCCI_STM32L0_REG_RCC_CRRCR_HSI48DIVEN   (UINT32_C(1) << 2)
#define	MCCI_STM32L0_REG_RCC_CRRCR_HSI48ON   (UINT32_C(1) << 0)
#define	MCCI_STM32L0_REG_RCC_CRRCR_HSI48RDY   (UINT32_C(1) << 1)
#define	MCCI_STM32L0_REG_RCC_CRRCR_RSV16   UINT32_C(0xFFFF0000)
#define	MCCI_STM32L0_REG_RCC_CRRCR_RSV3   UINT32_C(0xF8)
RCC_CFGR bits
#define	MCCI_STM32L0_REG_RCC_CFGR_HPRE   (UINT32_C(0xF) << 4)
#define	MCCI_STM32L0_REG_RCC_CFGR_HPRE_1   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 0)
#define	MCCI_STM32L0_REG_RCC_CFGR_HPRE_128   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 13)
#define	MCCI_STM32L0_REG_RCC_CFGR_HPRE_16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 11)
#define	MCCI_STM32L0_REG_RCC_CFGR_HPRE_2   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 8)
#define	MCCI_STM32L0_REG_RCC_CFGR_HPRE_256   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 14)
#define	MCCI_STM32L0_REG_RCC_CFGR_HPRE_4   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 9)
#define	MCCI_STM32L0_REG_RCC_CFGR_HPRE_512   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 15)
#define	MCCI_STM32L0_REG_RCC_CFGR_HPRE_64   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 12)
#define	MCCI_STM32L0_REG_RCC_CFGR_HPRE_8   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 10)
#define	MCCI_STM32L0_REG_RCC_CFGR_MCOPRE   (UINT32_C(7) << 28)
#define	MCCI_STM32L0_REG_RCC_CFGR_MCOPRE_1   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOPRE, 0)
#define	MCCI_STM32L0_REG_RCC_CFGR_MCOPRE_16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOPRE, 4)
#define	MCCI_STM32L0_REG_RCC_CFGR_MCOPRE_2   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOPRE, 1)
#define	MCCI_STM32L0_REG_RCC_CFGR_MCOPRE_4   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOPRE, 2)
#define	MCCI_STM32L0_REG_RCC_CFGR_MCOPRE_8   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOPRE, 3)
#define	MCCI_STM32L0_REG_RCC_CFGR_MCOSEL   (UINT32_C(0xF) << 24)
#define	MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_HSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 4)
#define	MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 2)
#define	MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_HSI48   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 8)
#define	MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_LSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 7)
#define	MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_LSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 6)
#define	MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_MSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 3)
#define	MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_OFF   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 0)
#define	MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_PLL   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 5)
#define	MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_SYSCLK   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 1)
#define	MCCI_STM32L0_REG_RCC_CFGR_PLLDIV   (UINT32_C(3) << 22)
#define	MCCI_STM32L0_REG_RCC_CFGR_PLLDIV_2   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLDIV, 1)
#define	MCCI_STM32L0_REG_RCC_CFGR_PLLDIV_3   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLDIV, 2)
#define	MCCI_STM32L0_REG_RCC_CFGR_PLLDIV_4   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLDIV, 3)
#define	MCCI_STM32L0_REG_RCC_CFGR_PLLMUL   (UINT32_C(0xF) << 18)
#define	MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_12   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 4)
#define	MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 5)
#define	MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_24   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 6)
#define	MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_3   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 0)
#define	MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_32   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 7)
#define	MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_4   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 1)
#define	MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_48   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 8)
#define	MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_6   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 2)
#define	MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_8   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 3)
#define	MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_HSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLSRC, 1)
#define	MCCI_STM32L0_REG_RCC_CFGR_PLLSRC   (UINT32_C(1) << 16)
#define	MCCI_STM32L0_REG_RCC_CFGR_PLLSRC_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLSRC, 0)
#define	MCCI_STM32L0_REG_RCC_CFGR_PPRE1   (UINT32_C(7) << 8)
#define	MCCI_STM32L0_REG_RCC_CFGR_PPRE1_1   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE1, 0)
#define	MCCI_STM32L0_REG_RCC_CFGR_PPRE1_16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE1, 7)
#define	MCCI_STM32L0_REG_RCC_CFGR_PPRE1_2   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE1, 4)
#define	MCCI_STM32L0_REG_RCC_CFGR_PPRE1_4   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE1, 5)
#define	MCCI_STM32L0_REG_RCC_CFGR_PPRE1_8   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE1, 6)
#define	MCCI_STM32L0_REG_RCC_CFGR_PPRE2   (UINT32_C(7) << 11)
#define	MCCI_STM32L0_REG_RCC_CFGR_PPRE2_1   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE2, 0)
#define	MCCI_STM32L0_REG_RCC_CFGR_PPRE2_16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE2, 7)
#define	MCCI_STM32L0_REG_RCC_CFGR_PPRE2_2   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE2, 4)
#define	MCCI_STM32L0_REG_RCC_CFGR_PPRE2_4   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE2, 5)
#define	MCCI_STM32L0_REG_RCC_CFGR_PPRE2_8   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE2, 6)
#define	MCCI_STM32L0_REG_RCC_CFGR_RSV14   (UINT32_C(1) << 14)
#define	MCCI_STM32L0_REG_RCC_CFGR_RSV17   (UINT32_C(1) << 17)
#define	MCCI_STM32L0_REG_RCC_CFGR_RSV31   (UINT32_C(1) << 31)
#define	MCCI_STM32L0_REG_RCC_CFGR_STOPWUCK   (UINT32_C(1) << 15)
#define	MCCI_STM32L0_REG_RCC_CFGR_STOPWUCK_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_STOPWUCK, 1)
#define	MCCI_STM32L0_REG_RCC_CFGR_STOPWUCK_MSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_STOPWUCK, 0)
#define	MCCI_STM32L0_REG_RCC_CFGR_SW   (UINT32_C(3) << 0)
#define	MCCI_STM32L0_REG_RCC_CFGR_SW_HSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SW, 2)
#define	MCCI_STM32L0_REG_RCC_CFGR_SW_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SW, 1)
#define	MCCI_STM32L0_REG_RCC_CFGR_SW_MSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SW, 0)
#define	MCCI_STM32L0_REG_RCC_CFGR_SW_PLL   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SW, 3)
#define	MCCI_STM32L0_REG_RCC_CFGR_SWS   (UINT32_C(3) << 2)
#define	MCCI_STM32L0_REG_RCC_CFGR_SWS_HSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SWS, 2)
#define	MCCI_STM32L0_REG_RCC_CFGR_SWS_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SWS, 1)
#define	MCCI_STM32L0_REG_RCC_CFGR_SWS_MSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SWS, 0)
#define	MCCI_STM32L0_REG_RCC_CFGR_SWS_PLL   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SWS, 3)
RCC_CIER bits
#define	MCCI_STM32L0_REG_RCC_CIER_CSSLSE   (UINT32_C(1) << 7)
#define	MCCI_STM32L0_REG_RCC_CIER_HSERDYIE   (UINT32_C(1) << 3)
#define	MCCI_STM32L0_REG_RCC_CIER_HSI16RDYIE   (UINT32_C(1) << 2)
#define	MCCI_STM32L0_REG_RCC_CIER_HSI48RDYIE   (UINT32_C(1) << 6)
#define	MCCI_STM32L0_REG_RCC_CIER_LSERDYIE   (UINT32_C(1) << 1)
#define	MCCI_STM32L0_REG_RCC_CIER_LSIRDYIE   (UINT32_C(1) << 0)
#define	MCCI_STM32L0_REG_RCC_CIER_MSIRDYIE   (UINT32_C(1) << 5)
#define	MCCI_STM32L0_REG_RCC_CIER_PLLRDYIE   (UINT32_C(1) << 4)
#define	MCCI_STM32L0_REG_RCC_CIER_RSV8   UINT32_C(0xFFFFFF00)
RCC_CIFR bits
#define	MCCI_STM32L0_REG_RCC_CIFR_CSSHSEF   (UINT32_C(1) << 8)
#define	MCCI_STM32L0_REG_RCC_CIFR_CSSLSEF   (UINT32_C(1) << 7)
#define	MCCI_STM32L0_REG_RCC_CIFR_HSERDYF   (UINT32_C(1) << 3)
#define	MCCI_STM32L0_REG_RCC_CIFR_HSI16RDYF   (UINT32_C(1) << 2)
#define	MCCI_STM32L0_REG_RCC_CIFR_HSI48RDYF   (UINT32_C(1) << 6)
#define	MCCI_STM32L0_REG_RCC_CIFR_LSERDYF   (UINT32_C(1) << 1)
#define	MCCI_STM32L0_REG_RCC_CIFR_LSIRDYF   (UINT32_C(1) << 0)
#define	MCCI_STM32L0_REG_RCC_CIFR_MSIRDYF   (UINT32_C(1) << 5)
#define	MCCI_STM32L0_REG_RCC_CIFR_PLLRDYF   (UINT32_C(1) << 4)
#define	MCCI_STM32L0_REG_RCC_CIFR_RSV9   UINT32_C(0xFFFFFE00)
RCC_CICR bits
#define	MCCI_STM32L0_REG_RCC_CICR_CSSHSEC   (UINT32_C(1) << 8)
#define	MCCI_STM32L0_REG_RCC_CICR_CSSLSEC   (UINT32_C(1) << 7)
#define	MCCI_STM32L0_REG_RCC_CICR_HSERDYC   (UINT32_C(1) << 3)
#define	MCCI_STM32L0_REG_RCC_CICR_HSI16RDYC   (UINT32_C(1) << 2)
#define	MCCI_STM32L0_REG_RCC_CICR_HSI48RDYC   (UINT32_C(1) << 6)
#define	MCCI_STM32L0_REG_RCC_CICR_LSERDYC   (UINT32_C(1) << 1)
#define	MCCI_STM32L0_REG_RCC_CICR_LSIRDYC   (UINT32_C(1) << 0)
#define	MCCI_STM32L0_REG_RCC_CICR_MSIRDYC   (UINT32_C(1) << 5)
#define	MCCI_STM32L0_REG_RCC_CICR_PLLRDYC   (UINT32_C(1) << 4)
#define	MCCI_STM32L0_REG_RCC_CICR_RSV9   UINT32_C(0xFFFFFE00)
RCC_IOPRSTR bits
#define	MCCI_STM32L0_REG_RCC_IOPRSTR_IOPARST   (UINT32_C(1) << 0)
#define	MCCI_STM32L0_REG_RCC_IOPRSTR_IOPBRST   (UINT32_C(1) << 1)
#define	MCCI_STM32L0_REG_RCC_IOPRSTR_IOPCRST   (UINT32_C(1) << 2)
#define	MCCI_STM32L0_REG_RCC_IOPRSTR_IOPDRST   (UINT32_C(1) << 3)
#define	MCCI_STM32L0_REG_RCC_IOPRSTR_IOPERST   (UINT32_C(1) << 4)
#define	MCCI_STM32L0_REG_RCC_IOPRSTR_IOPHRST   (UINT32_C(1) << 7)
#define	MCCI_STM32L0_REG_RCC_IOPRSTR_RSV5   (UINT32_C(3) << 5)
#define	MCCI_STM32L0_REG_RCC_IOPRSTR_RSV8   UINT32_C(0xFFFFFF00)
RCC_AHBRSTR bits
#define	MCCI_STM32L0_REG_RCC_AHBRSTR_CRCRST   (UINT32_C(1) << 12)
#define	MCCI_STM32L0_REG_RCC_AHBRSTR_CRYPRST   (UINT32_C(1) << 24)
#define	MCCI_STM32L0_REG_RCC_AHBRSTR_DMARST   (UINT32_C(1) << 0)
#define	MCCI_STM32L0_REG_RCC_AHBRSTR_MIFRST   (UINT32_C(1) << 8)
#define	MCCI_STM32L0_REG_RCC_AHBRSTR_RNGRST   (UINT32_C(1) << 20)
#define	MCCI_STM32L0_REG_RCC_AHBRSTR_RSV1   (UINT32_C(0x7F) << 1)
#define	MCCI_STM32L0_REG_RCC_AHBRSTR_RSV13   (UINT32_C(7) << 13)
#define	MCCI_STM32L0_REG_RCC_AHBRSTR_RSV17   (UINT32_C(7) << 17)
#define	MCCI_STM32L0_REG_RCC_AHBRSTR_RSV21   (UINT32_C(7) << 21)
#define	MCCI_STM32L0_REG_RCC_AHBRSTR_RSV25   (UINT32_C(0x7F) << 25)
#define	MCCI_STM32L0_REG_RCC_AHBRSTR_RSV9   (UINT32_C(7) << 9)
#define	MCCI_STM32L0_REG_RCC_AHBRSTR_TSCRST   (UINT32_C(1) << 16)
RCC_APB2RSTR bits
#define	MCCI_STM32L0_REG_RCC_APB2RSTR_ADCRST   (UINT32_C(1) << 9)
	ADC reset.
#define	MCCI_STM32L0_REG_RCC_APB2RSTR_DBGRST   (UINT32_C(1) << 22)
	Debug reset.
#define	MCCI_STM32L0_REG_RCC_APB2RSTR_RSV1   (UINT32_C(1) << 1)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2RSTR_RSV10   (UINT32_C(3) << 10)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2RSTR_RSV13   (UINT32_C(1) << 13)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2RSTR_RSV15   (UINT32_C(0x7F) << 15)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2RSTR_RSV23   UINT32_C(0xFF800000)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2RSTR_RSV3   (UINT32_C(3) << 3)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2RSTR_RSV6   (UINT32_C(7) << 6)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2RSTR_SPI1RST   (UINT32_C(1) << 12)
	SPI1 reset.
#define	MCCI_STM32L0_REG_RCC_APB2RSTR_SYSCFRST   (UINT32_C(1) << 0)
	SYSCFG reset.
#define	MCCI_STM32L0_REG_RCC_APB2RSTR_TIM21RST   (UINT32_C(1) << 2)
	TIM21 reset.
#define	MCCI_STM32L0_REG_RCC_APB2RSTR_TIM22RST   (UINT32_C(1) << 5)
	TIM22 reset.
#define	MCCI_STM32L0_REG_RCC_APB2RSTR_USART1RST   (UINT32_C(1) << 14)
	USART1 reset.
RCC_APB1RSTR bits
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_CRSRST   (UINT32_C(1) << 27)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_DACRRST   (UINT32_C(1) << 29)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_I2C1RST   (UINT32_C(1) << 21)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_I2C2RST   (UINT32_C(1) << 22)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_I2C3RST   (UINT32_C(1) << 30)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_LPTIM1RST   (UINT32_C(1) << 31)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_LPUART1RST   (UINT32_C(1) << 18)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_PWRRST   (UINT32_C(1) << 28)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_RSV12   (UINT32_C(3) << 12)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_RSV15   (UINT32_C(3) << 15)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_RSV2   (UINT32_C(3) << 2)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_RSV24   (UINT32_C(7) << 24)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_RSV6   (UINT32_C(0x1F) << 6)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_SPI2RST   (UINT32_C(1) << 14)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_TIM2   (UINT32_C(1) << 0)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_TIM3   (UINT32_C(1) << 1)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_TIM6RST   (UINT32_C(1) << 4)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_TIM7RST   (UINT32_C(1) << 5)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_USART2RST   (UINT32_C(1) << 17)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_USART4RST   (UINT32_C(1) << 19)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_USART5RST   (UINT32_C(1) << 20)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_USBRST   (UINT32_C(1) << 23)
#define	MCCI_STM32L0_REG_RCC_APB1RSTR_WWDGRST   (UINT32_C(1) << 11)
RCC_IOPENR bits
#define	MCCI_STM32L0_REG_RCC_IOPENR_IOPAEN   (UINT32_C(1) << 0)
#define	MCCI_STM32L0_REG_RCC_IOPENR_IOPBEN   (UINT32_C(1) << 1)
#define	MCCI_STM32L0_REG_RCC_IOPENR_IOPCEN   (UINT32_C(1) << 2)
#define	MCCI_STM32L0_REG_RCC_IOPENR_IOPDEN   (UINT32_C(1) << 3)
#define	MCCI_STM32L0_REG_RCC_IOPENR_IOPEEN   (UINT32_C(1) << 4)
#define	MCCI_STM32L0_REG_RCC_IOPENR_IOPHEN   (UINT32_C(1) << 7)
#define	MCCI_STM32L0_REG_RCC_IOPENR_RSV5   (UINT32_C(3) << 5)
#define	MCCI_STM32L0_REG_RCC_IOPENR_RSV8   UINT32_C(0xFFFFFF00)
RCC_AHBENR bits
#define	MCCI_STM32L0_REG_RCC_AHBENR_CRCEN   (UINT32_C(1) << 12)
#define	MCCI_STM32L0_REG_RCC_AHBENR_CRYPEN   (UINT32_C(1) << 24)
#define	MCCI_STM32L0_REG_RCC_AHBENR_DMAEN   (UINT32_C(1) << 0)
#define	MCCI_STM32L0_REG_RCC_AHBENR_MIFEN   (UINT32_C(1) << 8)
#define	MCCI_STM32L0_REG_RCC_AHBENR_RNGEN   (UINT32_C(1) << 20)
#define	MCCI_STM32L0_REG_RCC_AHBENR_RSV1   (UINT32_C(0x7F) << 1)
#define	MCCI_STM32L0_REG_RCC_AHBENR_RSV13   (UINT32_C(7) << 13)
#define	MCCI_STM32L0_REG_RCC_AHBENR_RSV17   (UINT32_C(7) << 17)
#define	MCCI_STM32L0_REG_RCC_AHBENR_RSV21   (UINT32_C(7) << 21)
#define	MCCI_STM32L0_REG_RCC_AHBENR_RSV25   (UINT32_C(0x7F) << 25)
#define	MCCI_STM32L0_REG_RCC_AHBENR_RSV9   (UINT32_C(7) << 9)
#define	MCCI_STM32L0_REG_RCC_AHBENR_TSCEN   (UINT32_C(1) << 16)
RCC_APB2ENR bits
#define	MCCI_STM32L0_REG_RCC_APB2ENR_ADCEN   (UINT32_C(1) << 9)
	ADC enable.
#define	MCCI_STM32L0_REG_RCC_APB2ENR_DBGEN   (UINT32_C(1) << 22)
	Debug enable.
#define	MCCI_STM32L0_REG_RCC_APB2ENR_RSV1   (UINT32_C(1) << 1)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2ENR_RSV10   (UINT32_C(3) << 10)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2ENR_RSV13   (UINT32_C(1) << 13)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2ENR_RSV15   (UINT32_C(0x7F) << 15)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2ENR_RSV23   UINT32_C(0xFF800000)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2ENR_RSV3   (UINT32_C(3) << 3)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2ENR_RSV6   (UINT32_C(7) << 6)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2ENR_SPI1EN   (UINT32_C(1) << 12)
	SPI1 enable.
#define	MCCI_STM32L0_REG_RCC_APB2ENR_SYSCFEN   (UINT32_C(1) << 0)
	SYSCFG enable.
#define	MCCI_STM32L0_REG_RCC_APB2ENR_TIM21EN   (UINT32_C(1) << 2)
	TIM21 enable.
#define	MCCI_STM32L0_REG_RCC_APB2ENR_TIM22EN   (UINT32_C(1) << 5)
	TIM22 enable.
#define	MCCI_STM32L0_REG_RCC_APB2ENR_USART1EN   (UINT32_C(1) << 14)
	USART1 enable.
RCC_APB1ENR bits
#define	MCCI_STM32L0_REG_RCC_APB1ENR_CRSEN   (UINT32_C(1) << 27)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_DACREN   (UINT32_C(1) << 29)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_I2C1EN   (UINT32_C(1) << 21)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_I2C2EN   (UINT32_C(1) << 22)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_I2C3EN   (UINT32_C(1) << 30)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_LPTIM1EN   (UINT32_C(1) << 31)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_LPUART1EN   (UINT32_C(1) << 18)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_PWREN   (UINT32_C(1) << 28)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_RSV12   (UINT32_C(3) << 12)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_RSV15   (UINT32_C(3) << 15)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_RSV2   (UINT32_C(3) << 2)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_RSV24   (UINT32_C(7) << 24)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_RSV6   (UINT32_C(0x1F) << 6)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_SPI2EN   (UINT32_C(1) << 14)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_TIM2   (UINT32_C(1) << 0)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_TIM3   (UINT32_C(1) << 1)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_TIM6EN   (UINT32_C(1) << 4)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_TIM7EN   (UINT32_C(1) << 5)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_USART2EN   (UINT32_C(1) << 17)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_USART4EN   (UINT32_C(1) << 19)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_USART5EN   (UINT32_C(1) << 20)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_USBEN   (UINT32_C(1) << 23)
#define	MCCI_STM32L0_REG_RCC_APB1ENR_WWDGEN   (UINT32_C(1) << 11)
RCC_IOPSMEN bits
#define	MCCI_STM32L0_REG_RCC_IOPSMENR_IOPASMEN   (UINT32_C(1) << 0)
#define	MCCI_STM32L0_REG_RCC_IOPSMENR_IOPBSMEN   (UINT32_C(1) << 1)
#define	MCCI_STM32L0_REG_RCC_IOPSMENR_IOPCSMEN   (UINT32_C(1) << 2)
#define	MCCI_STM32L0_REG_RCC_IOPSMENR_IOPDSMEN   (UINT32_C(1) << 3)
#define	MCCI_STM32L0_REG_RCC_IOPSMENR_IOPESMEN   (UINT32_C(1) << 4)
#define	MCCI_STM32L0_REG_RCC_IOPSMENR_IOPHSMEN   (UINT32_C(1) << 7)
#define	MCCI_STM32L0_REG_RCC_IOPSMENR_RSV5   (UINT32_C(3) << 5)
#define	MCCI_STM32L0_REG_RCC_IOPSMENR_RSV8   UINT32_C(0xFFFFFF00)
RCC_AHBSMENR bits
#define	MCCI_STM32L0_REG_RCC_AHBSMENR_CRCSMEN   (UINT32_C(1) << 12)
#define	MCCI_STM32L0_REG_RCC_AHBSMENR_CRYPSMEN   (UINT32_C(1) << 24)
#define	MCCI_STM32L0_REG_RCC_AHBSMENR_DMASMEN   (UINT32_C(1) << 0)
#define	MCCI_STM32L0_REG_RCC_AHBSMENR_MIFSMEN   (UINT32_C(1) << 8)
#define	MCCI_STM32L0_REG_RCC_AHBSMENR_RNGSMEN   (UINT32_C(1) << 20)
#define	MCCI_STM32L0_REG_RCC_AHBSMENR_RSV1   (UINT32_C(0x7F) << 1)
#define	MCCI_STM32L0_REG_RCC_AHBSMENR_RSV10   (UINT32_C(3) << 10)
#define	MCCI_STM32L0_REG_RCC_AHBSMENR_RSV13   (UINT32_C(7) << 13)
#define	MCCI_STM32L0_REG_RCC_AHBSMENR_RSV17   (UINT32_C(7) << 17)
#define	MCCI_STM32L0_REG_RCC_AHBSMENR_RSV21   (UINT32_C(7) << 21)
#define	MCCI_STM32L0_REG_RCC_AHBSMENR_RSV25   (UINT32_C(0x7F) << 25)
#define	MCCI_STM32L0_REG_RCC_AHBSMENR_SRAMSMEN   (UINT32_C(1) << 9)
#define	MCCI_STM32L0_REG_RCC_AHBSMENR_TSCSMEN   (UINT32_C(1) << 16)
RCC_APB2SMENR bits
#define	MCCI_STM32L0_REG_RCC_APB2SMENR_ADCSMEN   (UINT32_C(1) << 9)
	ADC sleep-mode enable.
#define	MCCI_STM32L0_REG_RCC_APB2SMENR_DBGSMEN   (UINT32_C(1) << 22)
	Debug sleep-mode enable.
#define	MCCI_STM32L0_REG_RCC_APB2SMENR_RSV1   (UINT32_C(1) << 1)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2SMENR_RSV10   (UINT32_C(3) << 10)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2SMENR_RSV13   (UINT32_C(1) << 13)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2SMENR_RSV15   (UINT32_C(0x7F) << 15)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2SMENR_RSV23   UINT32_C(0xFF800000)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2SMENR_RSV3   (UINT32_C(3) << 3)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2SMENR_RSV6   (UINT32_C(7) << 6)
	reserved, don't change
#define	MCCI_STM32L0_REG_RCC_APB2SMENR_SPI1SMEN   (UINT32_C(1) << 12)
	SPI1 sleep-mode enable.
#define	MCCI_STM32L0_REG_RCC_APB2SMENR_SYSCFSMEN   (UINT32_C(1) << 0)
	SYSCFG sleep-mode enable.
#define	MCCI_STM32L0_REG_RCC_APB2SMENR_TIM21SMEN   (UINT32_C(1) << 2)
	TIM21 sleep-mode enable.
#define	MCCI_STM32L0_REG_RCC_APB2SMENR_TIM22SMEN   (UINT32_C(1) << 5)
	TIM22 sleep-mode enable.
#define	MCCI_STM32L0_REG_RCC_APB2SMENR_USART1SMEN   (UINT32_C(1) << 14)
	USART1 sleep-mode enable.
RCC_APB1SMENR bits
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_CRSSMEN   (UINT32_C(1) << 27)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_DACRSMEN   (UINT32_C(1) << 29)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_I2C1SMEN   (UINT32_C(1) << 21)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_I2C2SMEN   (UINT32_C(1) << 22)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_I2C3SMEN   (UINT32_C(1) << 30)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_LPTIM1SMEN   (UINT32_C(1) << 31)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_LPUART1SMEN   (UINT32_C(1) << 18)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_PWRSMEN   (UINT32_C(1) << 28)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_RSV12   (UINT32_C(3) << 12)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_RSV15   (UINT32_C(3) << 15)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_RSV2   (UINT32_C(3) << 2)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_RSV24   (UINT32_C(7) << 24)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_RSV6   (UINT32_C(0x1F) << 6)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_SPI2SMEN   (UINT32_C(1) << 14)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_TIM2   (UINT32_C(1) << 0)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_TIM3   (UINT32_C(1) << 1)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_TIM6SMEN   (UINT32_C(1) << 4)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_TIM7SMEN   (UINT32_C(1) << 5)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_USART2SMEN   (UINT32_C(1) << 17)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_USART4SMEN   (UINT32_C(1) << 19)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_USART5SMEN   (UINT32_C(1) << 20)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_USBSMEN   (UINT32_C(1) << 23)
#define	MCCI_STM32L0_REG_RCC_APB1SMENR_WWDGSMEN   (UINT32_C(1) << 11)
RCC_CCIPR bits
#define	MCCI_STM32L0_REG_RCC_CCIPR_HSI48SEL   (UINT32_C(1) << 26)
#define	MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL   (UINT32_C(3) << 12)
#define	MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL_APB   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL, 0)
#define	MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL, 2)
#define	MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL_LSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL, 1)
#define	MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL   (UINT32_C(3) << 16)
#define	MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL_APB   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL, 0)
#define	MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL, 2)
#define	MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL_LSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL, 1)
#define	MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL   (UINT32_C(3) << 18)
#define	MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL_APB   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL, 0)
#define	MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL, 2)
#define	MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL_LSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL, 3)
#define	MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL_LSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL, 1)
#define	MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL   (UINT32_C(3) << 10)
#define	MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL_APB   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL, 0)
#define	MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL, 2)
#define	MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL_LSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL, 3)
#define	MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL_LSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL, 1)
#define	MCCI_STM32L0_REG_RCC_CCIPR_RSV14   (UINT32_C(3) << 14)
#define	MCCI_STM32L0_REG_RCC_CCIPR_RSV20   (UINT32_C(0x3F) << 20)
#define	MCCI_STM32L0_REG_RCC_CCIPR_RSV27   (UINT32_C(0x1F) << 27)
#define	MCCI_STM32L0_REG_RCC_CCIPR_RSV4   (UINT32_C(0x3F) << 4)
#define	MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL   (UINT32_C(3) << 0)
#define	MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL_APB   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL, 0)
#define	MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL, 2)
#define	MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL_LSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL, 3)
#define	MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL_LSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL, 1)
#define	MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL   (UINT32_C(3) << 2)
#define	MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL_APB   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL, 0)
#define	MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL, 2)
#define	MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL_LSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL, 3)
#define	MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL_LSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL, 1)
RCC_CSR bits
#define	MCCI_STM32L0_REG_RCC_CSR_CSSLSED   (UINT32_C(1) << 14)
#define	MCCI_STM32L0_REG_RCC_CSR_CSSLSEON   (UINT32_C(1) << 13)
#define	MCCI_STM32L0_REG_RCC_CSR_FWRSTF   (UINT32_C(1) << 24)
#define	MCCI_STM32L0_REG_RCC_CSR_IWDGRSTF   (UINT32_C(1) << 29)
#define	MCCI_STM32L0_REG_RCC_CSR_LPWRRSTF   (UINT32_C(1) << 31)
#define	MCCI_STM32L0_REG_RCC_CSR_LSEBYP   (UINT32_C(1) << 10)
#define	MCCI_STM32L0_REG_RCC_CSR_LSEDRV   (UINT32_C(3) << 11)
#define	MCCI_STM32L0_REG_RCC_CSR_LSEDRV_HIGH   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_LSEDRV, 3)
#define	MCCI_STM32L0_REG_RCC_CSR_LSEDRV_LOW   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_LSEDRV, 0)
#define	MCCI_STM32L0_REG_RCC_CSR_LSEDRV_M1   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_LSEDRV, 1)
#define	MCCI_STM32L0_REG_RCC_CSR_LSEDRV_M2   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_LSEDRV, 2)
#define	MCCI_STM32L0_REG_RCC_CSR_LSEON   (UINT32_C(1) << 8)
#define	MCCI_STM32L0_REG_RCC_CSR_LSERDY   (UINT32_C(1) << 9)
#define	MCCI_STM32L0_REG_RCC_CSR_LSION   (UINT32_C(1) << 0)
#define	MCCI_STM32L0_REG_RCC_CSR_LSIRDY   (UINT32_C(1) << 1)
#define	MCCI_STM32L0_REG_RCC_CSR_OBLRSTF   (UINT32_C(1) << 25)
#define	MCCI_STM32L0_REG_RCC_CSR_PINRSTF   (UINT32_C(1) << 26)
#define	MCCI_STM32L0_REG_RCC_CSR_PORRSTF   (UINT32_C(1) << 27)
#define	MCCI_STM32L0_REG_RCC_CSR_RMVF   (UINT32_C(1) << 23)
#define	MCCI_STM32L0_REG_RCC_CSR_RSV15   (UINT32_C(1) << 15)
#define	MCCI_STM32L0_REG_RCC_CSR_RSV2   (UINT32_C(0x3F) << 2)
#define	MCCI_STM32L0_REG_RCC_CSR_RSV20   (UINT32_C(7) << 20)
#define	MCCI_STM32L0_REG_RCC_CSR_RTCEN   (UINT32_C(1) << 18)
#define	MCCI_STM32L0_REG_RCC_CSR_RTCRST   (UINT32_C(1) << 19)
#define	MCCI_STM32L0_REG_RCC_CSR_RTCSEL   (UINT32_C(3) << 16)
#define	MCCI_STM32L0_REG_RCC_CSR_RTCSEL_HSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_RTCSEL, 0)
#define	MCCI_STM32L0_REG_RCC_CSR_RTCSEL_LSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_RTCSEL, 0)
#define	MCCI_STM32L0_REG_RCC_CSR_RTCSEL_LSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_RTCSEL, 0)
#define	MCCI_STM32L0_REG_RCC_CSR_RTCSEL_NONE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_RTCSEL, 0)
#define	MCCI_STM32L0_REG_RCC_CSR_SFTRSTF   (UINT32_C(1) << 28)
#define	MCCI_STM32L0_REG_RCC_CSR_WWDGRSTF   (UINT32_C(1) << 30)
GPIO register offsets
#define	MCCI_STM32L0_GPIO_AFRH   UINT32_C(0x24)
#define	MCCI_STM32L0_GPIO_AFRL   UINT32_C(0x20)
#define	MCCI_STM32L0_GPIO_BRR   UINT32_C(0x28)
#define	MCCI_STM32L0_GPIO_BSRR   UINT32_C(0x18)
#define	MCCI_STM32L0_GPIO_IDR   UINT32_C(0x10)
#define	MCCI_STM32L0_GPIO_LCKR   UINT32_C(0x1C)
#define	MCCI_STM32L0_GPIO_MODER   UINT32_C(0x00)
#define	MCCI_STM32L0_GPIO_ODR   UINT32_C(0x14)
#define	MCCI_STM32L0_GPIO_OSPEEDR   UINT32_C(0x08)
#define	MCCI_STM32L0_GPIO_OTYPER   UINT32_C(0x04)
#define	MCCI_STM32L0_GPIO_PUPDR   UINT32_C(0x0C)
GPIO_MODER bits – used to select pin mode, two bits per pin
#define	MCCI_STM32L0_GPIO_MODE_AF   UINT32_C(2)
#define	MCCI_STM32L0_GPIO_MODE_ANALOG   UINT32_C(3)
#define	MCCI_STM32L0_GPIO_MODE_IN   UINT32_C(0)
#define	MCCI_STM32L0_GPIO_MODE_MASK   UINT32_C(3)
#define	MCCI_STM32L0_GPIO_MODE_OUT   UINT32_C(1)
GPIO_OTYPER bits
#define	MCCI_STM32L0_GPIO_OTYPE_OD   UINT32_C(1)
#define	MCCI_STM32L0_GPIO_OTYPE_PP   UINT32_C(0)
GPIO_OSPEEDR bits – used to select pin speed, two bits per pin
#define	MCCI_STM32L0_GPIO_OSPEED_HIGH   UINT32_C(2)
#define	MCCI_STM32L0_GPIO_OSPEED_LOW   UINT32_C(0)
#define	MCCI_STM32L0_GPIO_OSPEED_MASK   UINT32_C(3)
#define	MCCI_STM32L0_GPIO_OSPEED_MEDIUM   UINT32_C(1)
#define	MCCI_STM32L0_GPIO_OSPEED_P(p)   (UINT32_C(3) << (2 * (p)))
	compute the mask for the mode bits for port bits 0..15
#define	MCCI_STM32L0_GPIO_OSPEED_VHIGH   UINT32_C(3)
GPIO_PUPDR bits – used to select pin pullup/pulldown, two bits per pin
#define	MCCI_STM32L0_GPIO_PUPD_MASK   UINT32_C(3)
#define	MCCI_STM32L0_GPIO_PUPD_NONE   UINT32_C(0)
#define	MCCI_STM32L0_GPIO_PUPD_P(p)   (UINT32_C(3) << (2 * (p)))
	compute the mask for the mode bits for port bits 0..15
#define	MCCI_STM32L0_GPIO_PUPD_PULLDOWN   UINT32_C(2)
#define	MCCI_STM32L0_GPIO_PUPD_PULLUP   UINT32_C(1)
GPIO_BSRR bits
#define	MCCI_STM32L0_GPIO_BSRR_BR   (UINT32_C(0xFFFF) << 16)
#define	MCCI_STM32L0_GPIO_BSRR_BR0   (UINT32_C(1) << 16)
#define	MCCI_STM32L0_GPIO_BSRR_BR_P(p)   (MCCI_STM32L0_GPIO_BSRR_BR0 << (p))
	compute port-bit reset mask for bit p.
#define	MCCI_STM32L0_GPIO_BSRR_BS   (UINT32_C(0xFFFF) << 0)
#define	MCCI_STM32L0_GPIO_BSRR_BS0   (UINT32_C(1) << 0)
#define	MCCI_STM32L0_GPIO_BSRR_BS_P(p)   (MCCI_STM32L0_GPIO_BSRR_BS0 << (p))
	compute port-bit set mask for bit p.
GPIO_LCKR bits
#define	MCCI_STM32L0_GPIO_LCKR_LCK   (UINT32_C(0xFFFF) << 0)
#define	MCCI_STM32L0_GPIO_LCKR_LCK_P(p)   (UINT32_C(1) << (p))
	compute GPIO lock bit fmask for bit p.
#define	MCCI_STM32L0_GPIO_LCKR_LCKK   (UINT32_C(1) << 16)
#define	MCCI_STM32L0_GPIO_LCKR_RSV17   UINT32_C(0xFFFE0000)
GPIO_AFRx bits
get reg offset for GPIO_AFRx for port bit p. This is the byte offset relative to the base of the GPIO block.
#define	MCCI_STM32L0_GPIO_AFRx_P(p)   (MCCI_STM32L0_GPIO_AFRL + (((p) / 8u) * 4u))
#define	MCCI_STM32L0_GPIO_AFSEL_P(p)   (UINT32_C(0xF) << (((p) & 7u) * 4u))
	get AFRx mask for port bit p.
#define	MCCI_STM32L0_GPIO_AFSEL_PV(p, v)   (((v) & UINT32_C(0xF)) << (((p) & 7u) * 4u))
	make a mask of AFRx value v for port bit p..
SPI offsets
#define	MCCI_STM32L0_SPI_CR1   UINT32_C(0x00)
	offset to SPI control register 1
#define	MCCI_STM32L0_SPI_CR2   UINT32_C(0x04)
	offset to SPI control register 2
#define	MCCI_STM32L0_SPI_CRCPR   UINT32_C(0x10)
	offset to SPI CRC polynomial
#define	MCCI_STM32L0_SPI_DR   UINT32_C(0x0C)
	offset to SPI data register
#define	MCCI_STM32L0_SPI_I2SCFGR   UINT32_C(0x1C)
	offset to SPI I2S config register
#define	MCCI_STM32L0_SPI_I2SPR   UINT32_C(0x20)
	offset to SPI I2S prescaler
#define	MCCI_STM32L0_SPI_RXCRCR   UINT32_C(0x14)
	offset to SPI receive CRC
#define	MCCI_STM32L0_SPI_SR   UINT32_C(0x08)
	offset to SPI status register
#define	MCCI_STM32L0_SPI_TXCRCR   UINT32_C(0x18)
	offset to SPI transmit CRC
SPI_CR1 bits
#define	MCCI_STM32L0_SPI_CR1_BIDIMODE   (UINT32_C(1) << 15)
	Bidirectional mode.
#define	MCCI_STM32L0_SPI_CR1_BIDIOE   (UINT32_C(1) << 14)
	Bidirectional output enable.
#define	MCCI_STM32L0_SPI_CR1_BR   (UINT32_C(7) << 3)
	baud rate control (PCLK divisor)
#define	MCCI_STM32L0_SPI_CR1_BR_128   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 6)
	PCLK/128.
#define	MCCI_STM32L0_SPI_CR1_BR_16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 3)
	PCLK/16.
#define	MCCI_STM32L0_SPI_CR1_BR_2   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 0)
	PCLK/2.
#define	MCCI_STM32L0_SPI_CR1_BR_256   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 7)
	PCLK/256.
#define	MCCI_STM32L0_SPI_CR1_BR_32   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 4)
	PCLK/32.
#define	MCCI_STM32L0_SPI_CR1_BR_4   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 1)
	PCLK/4.
#define	MCCI_STM32L0_SPI_CR1_BR_64   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 5)
	PCLK/64.
#define	MCCI_STM32L0_SPI_CR1_BR_8   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 2)
	PCLK/8.
#define	MCCI_STM32L0_SPI_CR1_CPHA   (UINT32_C(1) << 0)
	Clock phase: second clock transaction captures (not first)
#define	MCCI_STM32L0_SPI_CR1_CPOL   (UINT32_C(1) << 1)
	Clk to 1 when idle (not zero)
#define	MCCI_STM32L0_SPI_CR1_CRCEN   (UINT32_C(1) << 13)
	CRC enabled.
#define	MCCI_STM32L0_SPI_CR1_CRCNEXT   (UINT32_C(1) << 12)
	CRC is next.
#define	MCCI_STM32L0_SPI_CR1_DFF   (UINT32_C(1) << 11)
	Data frame format (16 bit / not 8 bit)
#define	MCCI_STM32L0_SPI_CR1_LSBFIRST   (UINT32_C(1) << 7)
	LSB first (not MSB)
#define	MCCI_STM32L0_SPI_CR1_MSTR   (UINT32_C(1) << 2)
	Master (not slave)
#define	MCCI_STM32L0_SPI_CR1_RSV16   UINT32_C(0xFFFF0000)
	reserved
#define	MCCI_STM32L0_SPI_CR1_RXONLY   (UINT32_C(1) << 10)
	Receive-only mode.
#define	MCCI_STM32L0_SPI_CR1_SPE   (UINT32_C(1) << 6)
	SPI enabled.
#define	MCCI_STM32L0_SPI_CR1_SSI   (UINT32_C(1) << 8)
	internal slave select
#define	MCCI_STM32L0_SPI_CR1_SSM   (UINT32_C(1) << 9)
	software slave management
SPI_CR2 bits
#define	MCCI_STM32L0_SPI_CR2_ERRIE   (UINT32_C(1) << 5)
	error interrupt enable
#define	MCCI_STM32L0_SPI_CR2_FRF   (UINT32_C(1) << 4)
	frame format TI (not Motorola)
#define	MCCI_STM32L0_SPI_CR2_RSV3   (UINT32_C(1) << 3)
	reserved, zero
#define	MCCI_STM32L0_SPI_CR2_RSV8   UINT32_C(0xFFFFFF00)
	reserved
#define	MCCI_STM32L0_SPI_CR2_RXDMAEN   (UINT32_C(1) << 0)
	rx DMA enable
#define	MCCI_STM32L0_SPI_CR2_RXNEIE   (UINT32_C(1) << 6)
	rx not empty interrupt enable
#define	MCCI_STM32L0_SPI_CR2_SSOE   (UINT32_C(1) << 2)
	enable SS in master mode
#define	MCCI_STM32L0_SPI_CR2_TXDMAEN   (UINT32_C(1) << 1)
	tx DMA enable
#define	MCCI_STM32L0_SPI_CR2_TXEIE   (UINT32_C(1) << 7)
	tx empty interrupt enable
SPI_SR bits
#define	MCCI_STM32L0_SPI_SR_BSY   (UINT32_C(1) << 7)
	busy
#define	MCCI_STM32L0_SPI_SR_CHSIDE   (UINT32_C(1) << 2)
	channel right (not left)
#define	MCCI_STM32L0_SPI_SR_CRCERR   (UINT32_C(1) << 4)
	CRC error (write zero to clear)
#define	MCCI_STM32L0_SPI_SR_FRE   (UINT32_C(1) << 8)
	frame error (read to clear)
#define	MCCI_STM32L0_SPI_SR_MODF   (UINT32_C(1) << 5)
	mode fault
#define	MCCI_STM32L0_SPI_SR_OVR   (UINT32_C(1) << 6)
	overrun
#define	MCCI_STM32L0_SPI_SR_RSV9   UINT32_C(0xFFFFFE00)
	reserved, zero
#define	MCCI_STM32L0_SPI_SR_RXNE   (UINT32_C(1) << 0)
	RX buffer not-empty.
#define	MCCI_STM32L0_SPI_SR_TXE   (UINT32_C(1) << 1)
	TX buffer empty.
#define	MCCI_STM32L0_SPI_SR_UDR   (UINT32_C(1) << 3)
	underrun
SPI_I2SCFGR bits
#define	MCCI_STM32L0_SPI_I2SCFGR_CHLEN   (UINT32_C(1) << 0)
	channel 32-bits wide (not 16)
#define	MCCI_STM32L0_SPI_I2SCFGR_CKPOL   (UINT32_C(1) << 3)
	steady state clock polarity high (not low)
#define	MCCI_STM32L0_SPI_I2SCFGR_DATLEN   (UINT32_C(3) << 1)
	data length
#define	MCCI_STM32L0_SPI_I2SCFGR_DATLEN_16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_DATLEN, 0)
	16-bit data
#define	MCCI_STM32L0_SPI_I2SCFGR_DATLEN_24   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_DATLEN, 1)
	24-bit data
#define	MCCI_STM32L0_SPI_I2SCFGR_DATLEN_32   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_DATLEN, 2)
	32-bit data
#define	MCCI_STM32L0_SPI_I2SCFGR_DATLEN_XX   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_DATLEN, 3)
	invalid data length
#define	MCCI_STM32L0_SPI_I2SCFGR_I2SCFG   (UINT32_C(3) << 8)
	I2S configuration mode.
#define	MCCI_STM32L0_SPI_I2SCFGR_I2SCFG_MRX   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SCFG, 3)
	I2S master receive.
#define	MCCI_STM32L0_SPI_I2SCFGR_I2SCFG_MTX   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SCFG, 2)
	I2S master transmit.
#define	MCCI_STM32L0_SPI_I2SCFGR_I2SCFG_SRX   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SCFG, 1)
	I2S slave receive.
#define	MCCI_STM32L0_SPI_I2SCFGR_I2SCFG_STX   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SCFG, 0)
	I2S slave transmit.
#define	MCCI_STM32L0_SPI_I2SCFGR_I2SE   (UINT32_C(1) << 10)
	I2S enable.
#define	MCCI_STM32L0_SPI_I2SCFGR_I2SMOD   (UINT32_C(1) << 11)
	I2S mode (not SPI)
#define	MCCI_STM32L0_SPI_I2SCFGR_I2SSTD   (UINT32_C(3) << 4)
	I2S standard selection.
#define	MCCI_STM32L0_SPI_I2SCFGR_I2SSTD_LEFT   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SSTD, 1)
	MSB justified.
#define	MCCI_STM32L0_SPI_I2SCFGR_I2SSTD_PCM   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SSTD, 3)
	PCM standard.
#define	MCCI_STM32L0_SPI_I2SCFGR_I2SSTD_PHILIPS   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SSTD, 0)
	Philips standard.
#define	MCCI_STM32L0_SPI_I2SCFGR_I2SSTD_RIGHT   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SSTD, 2)
	LSB justified.
#define	MCCI_STM32L0_SPI_I2SCFGR_PCMSYNC   (UINT32_C(1) << 7)
	Long (not short) PCM frame synchronization.
#define	MCCI_STM32L0_SPI_I2SCFGR_RSV13   UINT32_C(0xFFFFE000)
	reserved (do not change)
#define	MCCI_STM32L0_SPI_I2SCFGR_RSV6   (UINT32_C(1) << 6)
	reserved, zero
I2C register offsets
#define	MCCI_STM32L0_I2C_CR1   UINT32_C(0x00)
	Section 27.7.1: control register 1.
#define	MCCI_STM32L0_I2C_CR2   UINT32_C(0x04)
	Section 27.7.2: control register 2.
#define	MCCI_STM32L0_I2C_ICR   UINT32_C(0x1C)
	Section 27.7.8: interrupt clear register.
#define	MCCI_STM32L0_I2C_ISR   UINT32_C(0x18)
	Section 27.7.7: interrupt and status register.
#define	MCCI_STM32L0_I2C_OAR1   UINT32_C(0x08)
	Section 27.7.3: own address register 1.
#define	MCCI_STM32L0_I2C_OAR2   UINT32_C(0x0C)
	Section 27.7.4: own address register 2.
#define	MCCI_STM32L0_I2C_PECR   UINT32_C(0x20)
	Section 27.7.9: PEC register.
#define	MCCI_STM32L0_I2C_RXDR   UINT32_C(0x24)
	Section 27.7.10: receive data register.
#define	MCCI_STM32L0_I2C_TIMEOUTR   UINT32_C(0x14)
	Section 27.7.6: timeout register.
#define	MCCI_STM32L0_I2C_TIMINGR   UINT32_C(0x10)
	Section 27.7.5: timing register.
#define	MCCI_STM32L0_I2C_TXDR   UINT32_C(0x28)
	Section 27.7.11: transmit data register.
I2C_CR1 bits
#define	MCCI_STM32L0_I2C_CR1_ADDRIE   (UINT32_C(1) << 3)
	address match interrupt enable (slave)
#define	MCCI_STM32L0_I2C_CR1_ALERTEN   (UINT32_C(1) << 22)
	SMBus alert enable.
#define	MCCI_STM32L0_I2C_CR1_ANFOFF   (UINT32_C(1) << 12)
	analog noise filter OFF
#define	MCCI_STM32L0_I2C_CR1_DNF   (UINT32_C(0xF) << 8)
	digital noise filter [3:0]
#define	MCCI_STM32L0_I2C_CR1_ERRIE   (UINT32_C(1) << 7)
	error interrupts enable
#define	MCCI_STM32L0_I2C_CR1_GCEN   (UINT32_C(1) << 19)
	general call enable
#define	MCCI_STM32L0_I2C_CR1_NACKIE   (UINT32_C(1) << 4)
	NACK received interrupt enable.
#define	MCCI_STM32L0_I2C_CR1_NOSTRETCH   (UINT32_C(1) << 17)
	clock stretching disable
#define	MCCI_STM32L0_I2C_CR1_PE   (UINT32_C(1) << 0)
	peripheral enable
#define	MCCI_STM32L0_I2C_CR1_PECEN   (UINT32_C(1) << 23)
	PEC calculation enable.
#define	MCCI_STM32L0_I2C_CR1_RSV13   (UINT32_C(1) << 13)
	reserved: do not change
#define	MCCI_STM32L0_I2C_CR1_RSV24   UINT32_C(0xFF000000)
	reserved: do not change
#define	MCCI_STM32L0_I2C_CR1_RXDMAEN   (UINT32_C(1) << 15)
	DMA reception requests enable.
#define	MCCI_STM32L0_I2C_CR1_RXIE   (UINT32_C(1) << 2)
	RX interrupt enable.
#define	MCCI_STM32L0_I2C_CR1_SBC   (UINT32_C(1) << 16)
	slave byte control
#define	MCCI_STM32L0_I2C_CR1_SMBDEN   (UINT32_C(1) << 21)
	SMBus device default address enable.
#define	MCCI_STM32L0_I2C_CR1_SMBHEN   (UINT32_C(1) << 20)
	SMBus host address enable.
#define	MCCI_STM32L0_I2C_CR1_STOPIE   (UINT32_C(1) << 5)
	STOP detection interrupt enable.
#define	MCCI_STM32L0_I2C_CR1_TCIE   (UINT32_C(1) << 6)
	transfer complete interrupt enable
#define	MCCI_STM32L0_I2C_CR1_TXDMAEN   (UINT32_C(1) << 14)
	DMA transmission requests enable.
#define	MCCI_STM32L0_I2C_CR1_TXIE   (UINT32_C(1) << 1)
	TX interrupt enable.
#define	MCCI_STM32L0_I2C_CR1_WUPEN   (UINT32_C(1) << 18)
	wakeup from Stop mode enable
I2C_CR2 bits
#define	MCCI_STM32L0_I2C_CR2_ADD10   (UINT32_C(1) << 11)
	10-bit addressing mode (master)
#define	MCCI_STM32L0_I2C_CR2_AUTOEND   (UINT32_C(1) << 25)
	automatic end mode (master)
#define	MCCI_STM32L0_I2C_CR2_HEAD10R   (UINT32_C(1) << 12)
	10-bit address header only read direction
#define	MCCI_STM32L0_I2C_CR2_NACK   (UINT32_C(1) << 15)
	NACK generation (slave)
#define	MCCI_STM32L0_I2C_CR2_NBYTES   (UINT32_C(0xFF) << 16)
	number of bytes [7:0]
#define	MCCI_STM32L0_I2C_CR2_PECBYTE   (UINT32_C(1) << 26)
	packet error checking byte
#define	MCCI_STM32L0_I2C_CR2_RD_WRN   (UINT32_C(1) << 10)
	transfer direction: 1=read, 0=write
#define	MCCI_STM32L0_I2C_CR2_RELOAD   (UINT32_C(1) << 24)
	NBYTES reload mode.
#define	MCCI_STM32L0_I2C_CR2_RSV27   UINT32_C(0xf8000000)
	reserved: do not change
#define	MCCI_STM32L0_I2C_CR2_SADD   (UINT32_C(0x3FF) << 0)
	slave address [9:0]
#define	MCCI_STM32L0_I2C_CR2_START   (UINT32_C(1) << 13)
	START generation.
#define	MCCI_STM32L0_I2C_CR2_STOP   (UINT32_C(1) << 14)
	STOP generation (master)
I2C_OAR1 bits
#define	MCCI_STM32L0_I2C_OAR1_OA1   (UINT32_C(0x3FF) << 0)
	own address 1 [9:0]
#define	MCCI_STM32L0_I2C_OAR1_OA1EN   (UINT32_C(1) << 15)
	own address 1 enable
#define	MCCI_STM32L0_I2C_OAR1_OA1MODE   (UINT32_C(1) << 10)
	own address 1 10-bit mode
#define	MCCI_STM32L0_I2C_OAR1_RSV11   (UINT32_C(0xF) << 11)
	reserved: do not change
#define	MCCI_STM32L0_I2C_OAR1_RSV16   UINT32_C(0xFFFF0000)
	reserved: do not change
I2C_OAR2 bits
#define	MCCI_STM32L0_I2C_OAR2_OA2   (UINT32_C(0x7F) << 1)
	own address 2 [7:1]
#define	MCCI_STM32L0_I2C_OAR2_OA2EN   (UINT32_C(1) << 15)
	own address 2 enable
#define	MCCI_STM32L0_I2C_OAR2_OA2MSK   (UINT32_C(0x7) << 8)
	own address 2 masks [2:0]
#define	MCCI_STM32L0_I2C_OAR2_RSV0   (UINT32_C(1) << 0)
	reserved: do not change
#define	MCCI_STM32L0_I2C_OAR2_RSV11   (UINT32_C(0xF) << 11)
	reserved: do not change
#define	MCCI_STM32L0_I2C_OAR2_RSV16   UINT32_C(0xFFFF0000)
	reserved: do not change
I2C_TIMINGR bits
#define	MCCI_STM32L0_I2C_TIMINGR_PRESC   (UINT32_C(0xF) << 28)
	timing prescaler [3:0]
#define	MCCI_STM32L0_I2C_TIMINGR_RSV24   (UINT32_C(0xF) << 24)
	reserved: do not change
#define	MCCI_STM32L0_I2C_TIMINGR_SCLDEL   (UINT32_C(0xF) << 20)
	data setup time [3:0]
#define	MCCI_STM32L0_I2C_TIMINGR_SCLH   (UINT32_C(0xFF) << 8)
	SCL high period [7:0] (master)
#define	MCCI_STM32L0_I2C_TIMINGR_SCLL   (UINT32_C(0xFF) << 0)
	SCL low period [7:0] (master)
#define	MCCI_STM32L0_I2C_TIMINGR_SDADEL   (UINT32_C(0xF) << 16)
	data hold time [3:0]
I2C_TIMEOUTR bits
#define	MCCI_STM32L0_I2C_TIMEOUTR_RSV13   (UINT32_C(0x3) << 13)
	reserved: do not change
#define	MCCI_STM32L0_I2C_TIMEOUTR_RSV28   (UINT32_C(0x7) << 28)
	reserved: do not change
#define	MCCI_STM32L0_I2C_TIMEOUTR_TEXTEN   (UINT32_C(1) << 31)
	extended clock timeout enable
#define	MCCI_STM32L0_I2C_TIMEOUTR_TIDLE   (UINT32_C(1) << 12)
	idle clock timeout detection
#define	MCCI_STM32L0_I2C_TIMEOUTR_TIMEOUTA   (UINT32_C(0xFFF) << 0)
	bus timeout A [11:0]
#define	MCCI_STM32L0_I2C_TIMEOUTR_TIMEOUTB   (UINT32_C(0xFFF) << 16)
	bus timeout B [11:0]
#define	MCCI_STM32L0_I2C_TIMEOUTR_TIMOUTEN   (UINT32_C(1) << 15)
	clock timeout enable
I2C_ISR bits
#define	MCCI_STM32L0_I2C_ISR_ADDCODE   (UINT32_C(0x7F) << 17)
	address match code (slave) [6:0]
#define	MCCI_STM32L0_I2C_ISR_ADDR   (UINT32_C(1) << 3)
	address matched (slave)
#define	MCCI_STM32L0_I2C_ISR_ALERT   (UINT32_C(1) << 13)
	SMBus alert.
#define	MCCI_STM32L0_I2C_ISR_ARLO   (UINT32_C(1) << 9)
	arbitration lost
#define	MCCI_STM32L0_I2C_ISR_BERR   (UINT32_C(1) << 8)
	bus error
#define	MCCI_STM32L0_I2C_ISR_BUSY   (UINT32_C(1) << 15)
	bus busy
#define	MCCI_STM32L0_I2C_ISR_DIR   (UINT32_C(1) << 16)
	transfer direction (slave): 1=read, 0=write
#define	MCCI_STM32L0_I2C_ISR_NACKF   (UINT32_C(1) << 4)
	not acknowledge received flag
#define	MCCI_STM32L0_I2C_ISR_OVR   (UINT32_C(1) << 10)
	overrun/underrun (slave)
#define	MCCI_STM32L0_I2C_ISR_PECERR   (UINT32_C(1) << 11)
	PEC error in reception.
#define	MCCI_STM32L0_I2C_ISR_RSV14   (UINT32_C(1) << 14)
	reserved: do not change
#define	MCCI_STM32L0_I2C_ISR_RSV24   UINT32_C(0xFF000000)
	reserved: do not change
#define	MCCI_STM32L0_I2C_ISR_RXNE   (UINT32_C(1) << 2)
	receive data register not empty
#define	MCCI_STM32L0_I2C_ISR_STOPF   (UINT32_C(1) << 5)
	STOP detection flag.
#define	MCCI_STM32L0_I2C_ISR_TC   (UINT32_C(1) << 6)
	transfer complete (master)
#define	MCCI_STM32L0_I2C_ISR_TCR   (UINT32_C(1) << 7)
	transfer complete reload
#define	MCCI_STM32L0_I2C_ISR_TIMEOUT   (UINT32_C(1) << 12)
	timeout or tLOW detection flag
#define	MCCI_STM32L0_I2C_ISR_TXE   (UINT32_C(1) << 0)
	transmit data register empty
#define	MCCI_STM32L0_I2C_ISR_TXIS   (UINT32_C(1) << 1)
	transmit interrupt status
I2C_ICR bits
#define	MCCI_STM32L0_I2C_ICR_ADDRCF   (UINT32_C(1) << 3)
	address matched flag clear
#define	MCCI_STM32L0_I2C_ICR_ALERTCF   (UINT32_C(1) << 13)
	alert flag clear
#define	MCCI_STM32L0_I2C_ICR_ARLOCF   (UINT32_C(1) << 9)
	arbitration lost flag clear
#define	MCCI_STM32L0_I2C_ICR_BERRCF   (UINT32_C(1) << 8)
	bus error flag clear
#define	MCCI_STM32L0_I2C_ICR_NACKCF   (UINT32_C(1) << 4)
	not acknowledge flag clear
#define	MCCI_STM32L0_I2C_ICR_OVRCF   (UINT32_C(1) << 10)
	overrun/underrun flag clear
#define	MCCI_STM32L0_I2C_ICR_PECCF   (UINT32_C(1) << 11)
	PEC error flag clear.
#define	MCCI_STM32L0_I2C_ICR_RSV0   (UINT32_C(0x7) << 0)
	reserved: do not change
#define	MCCI_STM32L0_I2C_ICR_RSV14   UINT32_C(0xFFFFC000)
	reserved: do not change
#define	MCCI_STM32L0_I2C_ICR_RSV6   (UINT32_C(0x3) << 6)
	reserved: do not change
#define	MCCI_STM32L0_I2C_ICR_STOPCF   (UINT32_C(1) << 5)
	STOP detection flag clear.
#define	MCCI_STM32L0_I2C_ICR_TIMOUTCF   (UINT32_C(1) << 12)
	timeout detection flag clear

Macro Definition Documentation

_mcci_stm32l0xx_h_

#define _mcci_stm32l0xx_h_   /* prevent multiple includes */

Definition at line 23 of file mcci_stm32l0xx.h.

MCCI_STM32L0_FLASH_ADDRESS_GET_SECTOR

#define MCCI_STM32L0_FLASH_ADDRESS_GET_SECTOR

(

a

)

(((uint32_t)(a) - MCCI_STM32L0_MEMORY_FLASH) >> MCCI_BOOTLOADER_FIELD_SHIFT(MCCI_STM32L0_FLASH_SECTOR_SIZE))

given a flash address, convert to sector number

Definition at line 266 of file mcci_stm32l0xx.h.

MCCI_STM32L0_FLASH_HALF_PAGE_SIZE

#define MCCI_STM32L0_FLASH_HALF_PAGE_SIZE   UINT32_C(64)

size in bytes of a half-page

Definition at line 278 of file mcci_stm32l0xx.h.

MCCI_STM32L0_FLASH_OPTR_RDPROT_IS_L0

#define MCCI_STM32L0_FLASH_OPTR_RDPROT_IS_L0

(

v

)

((v) & MCCI_STM32L0_REG_FLASH_OPTR_RDPROT) == MCCI_STM32L0_REG_FLASH_OPTR_RDPROT_L0)

given image of FLASH_OPTR, return true if set for level 0 protection

Definition at line 252 of file mcci_stm32l0xx.h.

MCCI_STM32L0_FLASH_OPTR_RDPROT_IS_L1

#define MCCI_STM32L0_FLASH_OPTR_RDPROT_IS_L1

(

v

)

(! (MCCI_STM32L0_FLASH_OPTR_RDPROT_IS_L0(v) || MCCI_STM32L0_FLASH_OPTR_RDPROT_IS_L2(v)))

given image of FLASH_OPTR, return true if set for level 1 protection

Definition at line 258 of file mcci_stm32l0xx.h.

MCCI_STM32L0_FLASH_OPTR_RDPROT_IS_L2

#define MCCI_STM32L0_FLASH_OPTR_RDPROT_IS_L2

(

v

)

((v) & MCCI_STM32L0_REG_FLASH_OPTR_RDPROT) == MCCI_STM32L0_REG_FLASH_OPTR_RDPROT_L0)

given image of FLASH_OPTR, return true if set for level 2 protection

Definition at line 255 of file mcci_stm32l0xx.h.

MCCI_STM32L0_FLASH_PAGE_SIZE

#define MCCI_STM32L0_FLASH_PAGE_SIZE   UINT32_C(128)

size in bytes of a page

Definition at line 279 of file mcci_stm32l0xx.h.

MCCI_STM32L0_FLASH_SECTOR_SIZE

#define MCCI_STM32L0_FLASH_SECTOR_SIZE   UINT32_C(4096)

size in bytes of a flash sector

Definition at line 264 of file mcci_stm32l0xx.h.

MCCI_STM32L0_FLASH_WPROT_MASK_FOR_SECTOR

#define MCCI_STM32L0_FLASH_WPROT_MASK_FOR_SECTOR

(

s

)

(UINT32_C(1) << ((s) & 0x1F))

get mask for sector s.

Definition at line 273 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_AFRH

#define MCCI_STM32L0_GPIO_AFRH   UINT32_C(0x24)

Definition at line 869 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_AFRL

#define MCCI_STM32L0_GPIO_AFRL   UINT32_C(0x20)

Definition at line 868 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_AFRx_P

#define MCCI_STM32L0_GPIO_AFRx_P

(

p

)

(MCCI_STM32L0_GPIO_AFRL + (((p) / 8u) * 4u))

Definition at line 982 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_AFSEL_P

#define MCCI_STM32L0_GPIO_AFSEL_P

(

p

)

(UINT32_C(0xF) << (((p) & 7u) * 4u))

get AFRx mask for port bit p.

Normal use: MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_GPIO_AFSEL_P(bitnum), 0..15)

Definition at line 989 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_AFSEL_PV

#define MCCI_STM32L0_GPIO_AFSEL_PV	(		p,
			v
	)		(((v) & UINT32_C(0xF)) << (((p) & 7u) * 4u))

make a mask of AFRx value v for port bit p..

Definition at line 992 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_BRR

#define MCCI_STM32L0_GPIO_BRR   UINT32_C(0x28)

Definition at line 870 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_BSRR

#define MCCI_STM32L0_GPIO_BSRR   UINT32_C(0x18)

Definition at line 866 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_BSRR_BR

#define MCCI_STM32L0_GPIO_BSRR_BR   (UINT32_C(0xFFFF) << 16)

Definition at line 959 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_BSRR_BR0

#define MCCI_STM32L0_GPIO_BSRR_BR0   (UINT32_C(1) << 16)

Definition at line 958 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_BSRR_BR_P

#define MCCI_STM32L0_GPIO_BSRR_BR_P

(

p

)

(MCCI_STM32L0_GPIO_BSRR_BR0 << (p))

compute port-bit reset mask for bit p.

Definition at line 963 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_BSRR_BS

#define MCCI_STM32L0_GPIO_BSRR_BS   (UINT32_C(0xFFFF) << 0)

Definition at line 961 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_BSRR_BS0

#define MCCI_STM32L0_GPIO_BSRR_BS0   (UINT32_C(1) << 0)

Definition at line 960 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_BSRR_BS_P

#define MCCI_STM32L0_GPIO_BSRR_BS_P

(

p

)

(MCCI_STM32L0_GPIO_BSRR_BS0 << (p))

compute port-bit set mask for bit p.

Definition at line 965 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_IDR

#define MCCI_STM32L0_GPIO_IDR   UINT32_C(0x10)

Definition at line 864 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_LCKR

#define MCCI_STM32L0_GPIO_LCKR   UINT32_C(0x1C)

Definition at line 867 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_LCKR_LCK

#define MCCI_STM32L0_GPIO_LCKR_LCK   (UINT32_C(0xFFFF) << 0)

Definition at line 974 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_LCKR_LCK_P

#define MCCI_STM32L0_GPIO_LCKR_LCK_P

(

p

)

(UINT32_C(1) << (p))

compute GPIO lock bit fmask for bit p.

Definition at line 973 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_LCKR_LCKK

#define MCCI_STM32L0_GPIO_LCKR_LCKK   (UINT32_C(1) << 16)

Definition at line 971 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_LCKR_RSV17

#define MCCI_STM32L0_GPIO_LCKR_RSV17   UINT32_C(0xFFFE0000)

Definition at line 970 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_MODE_AF

#define MCCI_STM32L0_GPIO_MODE_AF   UINT32_C(2)

Definition at line 878 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_MODE_ANALOG

#define MCCI_STM32L0_GPIO_MODE_ANALOG   UINT32_C(3)

Definition at line 879 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_MODE_IN

#define MCCI_STM32L0_GPIO_MODE_IN   UINT32_C(0)

Definition at line 876 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_MODE_MASK

#define MCCI_STM32L0_GPIO_MODE_MASK   UINT32_C(3)

Definition at line 875 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_MODE_OUT

#define MCCI_STM32L0_GPIO_MODE_OUT   UINT32_C(1)

Definition at line 877 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_MODE_P

#define MCCI_STM32L0_GPIO_MODE_P

(

p

)

(UINT32_C(3) << (2 * (p)))

compute the mask for the mode bits for port bits 0..15

Normally we compute a mask using an expression like:

`MCCI_BOOTLOADER_FIELD_SET_VALUE(
    MCCI_STM32L0_GPIO_MODE_P(3),
    MCCI_STM32L0_GPIO_MODE_IN
    )`

Definition at line 891 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_MODER

#define MCCI_STM32L0_GPIO_MODER   UINT32_C(0x00)

Definition at line 860 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_ODR

#define MCCI_STM32L0_GPIO_ODR   UINT32_C(0x14)

Definition at line 865 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_OSPEED_HIGH

#define MCCI_STM32L0_GPIO_OSPEED_HIGH   UINT32_C(2)

Definition at line 922 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_OSPEED_LOW

#define MCCI_STM32L0_GPIO_OSPEED_LOW   UINT32_C(0)

Definition at line 920 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_OSPEED_MASK

#define MCCI_STM32L0_GPIO_OSPEED_MASK   UINT32_C(3)

Definition at line 919 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_OSPEED_MEDIUM

#define MCCI_STM32L0_GPIO_OSPEED_MEDIUM   UINT32_C(1)

Definition at line 921 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_OSPEED_P

#define MCCI_STM32L0_GPIO_OSPEED_P

(

p

)

(UINT32_C(3) << (2 * (p)))

compute the mask for the mode bits for port bits 0..15

Normally we compute a mask using an expression like:

`MCCI_BOOTLOADER_FIELD_SET_VALUE(
    MCCI_STM32L0_GPIO_OSPEED_P(3),
    MCCI_STM32L0_GPIO_OSPEED_IN
    )`

Definition at line 934 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_OSPEED_VHIGH

#define MCCI_STM32L0_GPIO_OSPEED_VHIGH   UINT32_C(3)

Definition at line 923 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_OSPEEDR

#define MCCI_STM32L0_GPIO_OSPEEDR   UINT32_C(0x08)

Definition at line 862 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_OTYPE_OD

#define MCCI_STM32L0_GPIO_OTYPE_OD   UINT32_C(1)

Definition at line 896 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_OTYPE_P

#define MCCI_STM32L0_GPIO_OTYPE_P

(

p

)

(UINT32_C(1) << (p))

compute the mask for the mode bits for port bits 0..15

Normally we compute a mask using an expression like:

`MCCI_BOOTLOADER_FIELD_SET_VALUE(
    MCCI_STM32L0_GPIO_OTYPE_P(3), // bit 3 in port
    MCCI_STM32L0_GPIO_OTYPE_PP
    )`

Definition at line 908 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_OTYPE_PP

#define MCCI_STM32L0_GPIO_OTYPE_PP   UINT32_C(0)

Definition at line 895 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_OTYPE_PV

#define MCCI_STM32L0_GPIO_OTYPE_PV	(		p,
			v
	)		(((v) & 1u) << (p))

directly compute a GPIO OTYPE mask

Parameters

p	is the bit number in the port
v	is the value (MCCI_STM32L0_GPIO_OTYPE_PP or MCCI_STM32L0_GPIO_OTYPE_OD)

Definition at line 915 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_OTYPER

#define MCCI_STM32L0_GPIO_OTYPER   UINT32_C(0x04)

Definition at line 861 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_PUPD_MASK

#define MCCI_STM32L0_GPIO_PUPD_MASK   UINT32_C(3)

Definition at line 939 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_PUPD_NONE

#define MCCI_STM32L0_GPIO_PUPD_NONE   UINT32_C(0)

Definition at line 940 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_PUPD_P

#define MCCI_STM32L0_GPIO_PUPD_P

(

p

)

(UINT32_C(3) << (2 * (p)))

compute the mask for the mode bits for port bits 0..15

Normally we compute a mask using an expression like:

`MCCI_BOOTLOADER_FIELD_SET_VALUE(
    MCCI_STM32L0_GPIO_PUPD_P(3),
    MCCI_STM32L0_GPIO_PUPD_PULLDOWN
    )`

Definition at line 953 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_PUPD_PULLDOWN

#define MCCI_STM32L0_GPIO_PUPD_PULLDOWN   UINT32_C(2)

Definition at line 942 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_PUPD_PULLUP

#define MCCI_STM32L0_GPIO_PUPD_PULLUP   UINT32_C(1)

Definition at line 941 of file mcci_stm32l0xx.h.

MCCI_STM32L0_GPIO_PUPDR

#define MCCI_STM32L0_GPIO_PUPDR   UINT32_C(0x0C)

Definition at line 863 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1

#define MCCI_STM32L0_I2C_CR1   UINT32_C(0x00)

Section 27.7.1: control register 1.

Definition at line 1104 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_ADDRIE

#define MCCI_STM32L0_I2C_CR1_ADDRIE   (UINT32_C(1) << 3)

address match interrupt enable (slave)

Definition at line 1137 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_ALERTEN

#define MCCI_STM32L0_I2C_CR1_ALERTEN   (UINT32_C(1) << 22)

SMBus alert enable.

Definition at line 1121 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_ANFOFF

#define MCCI_STM32L0_I2C_CR1_ANFOFF   (UINT32_C(1) << 12)

analog noise filter OFF

Definition at line 1131 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_DNF

#define MCCI_STM32L0_I2C_CR1_DNF   (UINT32_C(0xF) << 8)

digital noise filter [3:0]

Definition at line 1132 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_ERRIE

#define MCCI_STM32L0_I2C_CR1_ERRIE   (UINT32_C(1) << 7)

error interrupts enable

Definition at line 1133 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_GCEN

#define MCCI_STM32L0_I2C_CR1_GCEN   (UINT32_C(1) << 19)

general call enable

Definition at line 1124 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_NACKIE

#define MCCI_STM32L0_I2C_CR1_NACKIE   (UINT32_C(1) << 4)

NACK received interrupt enable.

Definition at line 1136 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_NOSTRETCH

#define MCCI_STM32L0_I2C_CR1_NOSTRETCH   (UINT32_C(1) << 17)

clock stretching disable

Definition at line 1126 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_PE

#define MCCI_STM32L0_I2C_CR1_PE   (UINT32_C(1) << 0)

peripheral enable

Definition at line 1140 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_PECEN

#define MCCI_STM32L0_I2C_CR1_PECEN   (UINT32_C(1) << 23)

PEC calculation enable.

Definition at line 1120 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_RSV13

#define MCCI_STM32L0_I2C_CR1_RSV13   (UINT32_C(1) << 13)

reserved: do not change

Definition at line 1130 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_RSV24

#define MCCI_STM32L0_I2C_CR1_RSV24   UINT32_C(0xFF000000)

reserved: do not change

Definition at line 1119 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_RXDMAEN

#define MCCI_STM32L0_I2C_CR1_RXDMAEN   (UINT32_C(1) << 15)

DMA reception requests enable.

Definition at line 1128 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_RXIE

#define MCCI_STM32L0_I2C_CR1_RXIE   (UINT32_C(1) << 2)

RX interrupt enable.

Definition at line 1138 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_SBC

#define MCCI_STM32L0_I2C_CR1_SBC   (UINT32_C(1) << 16)

slave byte control

Definition at line 1127 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_SMBDEN

#define MCCI_STM32L0_I2C_CR1_SMBDEN   (UINT32_C(1) << 21)

SMBus device default address enable.

Definition at line 1122 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_SMBHEN

#define MCCI_STM32L0_I2C_CR1_SMBHEN   (UINT32_C(1) << 20)

SMBus host address enable.

Definition at line 1123 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_STOPIE

#define MCCI_STM32L0_I2C_CR1_STOPIE   (UINT32_C(1) << 5)

STOP detection interrupt enable.

Definition at line 1135 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_TCIE

#define MCCI_STM32L0_I2C_CR1_TCIE   (UINT32_C(1) << 6)

transfer complete interrupt enable

Definition at line 1134 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_TXDMAEN

#define MCCI_STM32L0_I2C_CR1_TXDMAEN   (UINT32_C(1) << 14)

DMA transmission requests enable.

Definition at line 1129 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_TXIE

#define MCCI_STM32L0_I2C_CR1_TXIE   (UINT32_C(1) << 1)

TX interrupt enable.

Definition at line 1139 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR1_WUPEN

#define MCCI_STM32L0_I2C_CR1_WUPEN   (UINT32_C(1) << 18)

wakeup from Stop mode enable

Definition at line 1125 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR2

#define MCCI_STM32L0_I2C_CR2   UINT32_C(0x04)

Section 27.7.2: control register 2.

Definition at line 1105 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR2_ADD10

#define MCCI_STM32L0_I2C_CR2_ADD10   (UINT32_C(1) << 11)

10-bit addressing mode (master)

Definition at line 1154 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR2_AUTOEND

#define MCCI_STM32L0_I2C_CR2_AUTOEND   (UINT32_C(1) << 25)

automatic end mode (master)

Definition at line 1147 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR2_HEAD10R

#define MCCI_STM32L0_I2C_CR2_HEAD10R   (UINT32_C(1) << 12)

10-bit address header only read direction

Definition at line 1153 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR2_NACK

#define MCCI_STM32L0_I2C_CR2_NACK   (UINT32_C(1) << 15)

NACK generation (slave)

Definition at line 1150 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR2_NBYTES

#define MCCI_STM32L0_I2C_CR2_NBYTES   (UINT32_C(0xFF) << 16)

number of bytes [7:0]

Definition at line 1149 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR2_PECBYTE

#define MCCI_STM32L0_I2C_CR2_PECBYTE   (UINT32_C(1) << 26)

packet error checking byte

Definition at line 1146 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR2_RD_WRN

#define MCCI_STM32L0_I2C_CR2_RD_WRN   (UINT32_C(1) << 10)

transfer direction: 1=read, 0=write

Definition at line 1155 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR2_RELOAD

#define MCCI_STM32L0_I2C_CR2_RELOAD   (UINT32_C(1) << 24)

NBYTES reload mode.

Definition at line 1148 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR2_RSV27

#define MCCI_STM32L0_I2C_CR2_RSV27   UINT32_C(0xf8000000)

reserved: do not change

Definition at line 1145 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR2_SADD

#define MCCI_STM32L0_I2C_CR2_SADD   (UINT32_C(0x3FF) << 0)

slave address [9:0]

Definition at line 1156 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR2_START

#define MCCI_STM32L0_I2C_CR2_START   (UINT32_C(1) << 13)

START generation.

Definition at line 1152 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_CR2_STOP

#define MCCI_STM32L0_I2C_CR2_STOP   (UINT32_C(1) << 14)

STOP generation (master)

Definition at line 1151 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ICR

#define MCCI_STM32L0_I2C_ICR   UINT32_C(0x1C)

Section 27.7.8: interrupt clear register.

Definition at line 1111 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ICR_ADDRCF

#define MCCI_STM32L0_I2C_ICR_ADDRCF   (UINT32_C(1) << 3)

address matched flag clear

Definition at line 1234 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ICR_ALERTCF

#define MCCI_STM32L0_I2C_ICR_ALERTCF   (UINT32_C(1) << 13)

alert flag clear

Definition at line 1225 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ICR_ARLOCF

#define MCCI_STM32L0_I2C_ICR_ARLOCF   (UINT32_C(1) << 9)

arbitration lost flag clear

Definition at line 1229 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ICR_BERRCF

#define MCCI_STM32L0_I2C_ICR_BERRCF   (UINT32_C(1) << 8)

bus error flag clear

Definition at line 1230 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ICR_NACKCF

#define MCCI_STM32L0_I2C_ICR_NACKCF   (UINT32_C(1) << 4)

not acknowledge flag clear

Definition at line 1233 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ICR_OVRCF

#define MCCI_STM32L0_I2C_ICR_OVRCF   (UINT32_C(1) << 10)

overrun/underrun flag clear

Definition at line 1228 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ICR_PECCF

#define MCCI_STM32L0_I2C_ICR_PECCF   (UINT32_C(1) << 11)

PEC error flag clear.

Definition at line 1227 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ICR_RSV0

#define MCCI_STM32L0_I2C_ICR_RSV0   (UINT32_C(0x7) << 0)

reserved: do not change

Definition at line 1235 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ICR_RSV14

#define MCCI_STM32L0_I2C_ICR_RSV14   UINT32_C(0xFFFFC000)

reserved: do not change

Definition at line 1224 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ICR_RSV6

#define MCCI_STM32L0_I2C_ICR_RSV6   (UINT32_C(0x3) << 6)

reserved: do not change

Definition at line 1231 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ICR_STOPCF

#define MCCI_STM32L0_I2C_ICR_STOPCF   (UINT32_C(1) << 5)

STOP detection flag clear.

Definition at line 1232 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ICR_TIMOUTCF

#define MCCI_STM32L0_I2C_ICR_TIMOUTCF   (UINT32_C(1) << 12)

timeout detection flag clear

Definition at line 1226 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ISR

#define MCCI_STM32L0_I2C_ISR   UINT32_C(0x18)

Section 27.7.7: interrupt and status register.

Definition at line 1110 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ISR_ADDCODE

#define MCCI_STM32L0_I2C_ISR_ADDCODE   (UINT32_C(0x7F) << 17)

address match code (slave) [6:0]

Definition at line 1202 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ISR_ADDR

#define MCCI_STM32L0_I2C_ISR_ADDR   (UINT32_C(1) << 3)

address matched (slave)

Definition at line 1216 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ISR_ALERT

#define MCCI_STM32L0_I2C_ISR_ALERT   (UINT32_C(1) << 13)

SMBus alert.

Definition at line 1206 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ISR_ARLO

#define MCCI_STM32L0_I2C_ISR_ARLO   (UINT32_C(1) << 9)

arbitration lost

Definition at line 1210 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ISR_BERR

#define MCCI_STM32L0_I2C_ISR_BERR   (UINT32_C(1) << 8)

bus error

Definition at line 1211 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ISR_BUSY

#define MCCI_STM32L0_I2C_ISR_BUSY   (UINT32_C(1) << 15)

bus busy

Definition at line 1204 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ISR_DIR

#define MCCI_STM32L0_I2C_ISR_DIR   (UINT32_C(1) << 16)

transfer direction (slave): 1=read, 0=write

Definition at line 1203 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ISR_NACKF

#define MCCI_STM32L0_I2C_ISR_NACKF   (UINT32_C(1) << 4)

not acknowledge received flag

Definition at line 1215 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ISR_OVR

#define MCCI_STM32L0_I2C_ISR_OVR   (UINT32_C(1) << 10)

overrun/underrun (slave)

Definition at line 1209 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ISR_PECERR

#define MCCI_STM32L0_I2C_ISR_PECERR   (UINT32_C(1) << 11)

PEC error in reception.

Definition at line 1208 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ISR_RSV14

#define MCCI_STM32L0_I2C_ISR_RSV14   (UINT32_C(1) << 14)

reserved: do not change

Definition at line 1205 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ISR_RSV24

#define MCCI_STM32L0_I2C_ISR_RSV24   UINT32_C(0xFF000000)

reserved: do not change

Definition at line 1201 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ISR_RXNE

#define MCCI_STM32L0_I2C_ISR_RXNE   (UINT32_C(1) << 2)

receive data register not empty

Definition at line 1217 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ISR_STOPF

#define MCCI_STM32L0_I2C_ISR_STOPF   (UINT32_C(1) << 5)

STOP detection flag.

Definition at line 1214 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ISR_TC

#define MCCI_STM32L0_I2C_ISR_TC   (UINT32_C(1) << 6)

transfer complete (master)

Definition at line 1213 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ISR_TCR

#define MCCI_STM32L0_I2C_ISR_TCR   (UINT32_C(1) << 7)

transfer complete reload

Definition at line 1212 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ISR_TIMEOUT

#define MCCI_STM32L0_I2C_ISR_TIMEOUT   (UINT32_C(1) << 12)

timeout or tLOW detection flag

Definition at line 1207 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ISR_TXE

#define MCCI_STM32L0_I2C_ISR_TXE   (UINT32_C(1) << 0)

transmit data register empty

Definition at line 1219 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_ISR_TXIS

#define MCCI_STM32L0_I2C_ISR_TXIS   (UINT32_C(1) << 1)

transmit interrupt status

Definition at line 1218 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_OAR1

#define MCCI_STM32L0_I2C_OAR1   UINT32_C(0x08)

Section 27.7.3: own address register 1.

Definition at line 1106 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_OAR1_OA1

#define MCCI_STM32L0_I2C_OAR1_OA1   (UINT32_C(0x3FF) << 0)

own address 1 [9:0]

Definition at line 1165 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_OAR1_OA1EN

#define MCCI_STM32L0_I2C_OAR1_OA1EN   (UINT32_C(1) << 15)

own address 1 enable

Definition at line 1162 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_OAR1_OA1MODE

#define MCCI_STM32L0_I2C_OAR1_OA1MODE   (UINT32_C(1) << 10)

own address 1 10-bit mode

Definition at line 1164 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_OAR1_RSV11

#define MCCI_STM32L0_I2C_OAR1_RSV11   (UINT32_C(0xF) << 11)

reserved: do not change

Definition at line 1163 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_OAR1_RSV16

#define MCCI_STM32L0_I2C_OAR1_RSV16   UINT32_C(0xFFFF0000)

reserved: do not change

Definition at line 1161 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_OAR2

#define MCCI_STM32L0_I2C_OAR2   UINT32_C(0x0C)

Section 27.7.4: own address register 2.

Definition at line 1107 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_OAR2_OA2

#define MCCI_STM32L0_I2C_OAR2_OA2   (UINT32_C(0x7F) << 1)

own address 2 [7:1]

Definition at line 1174 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_OAR2_OA2EN

#define MCCI_STM32L0_I2C_OAR2_OA2EN   (UINT32_C(1) << 15)

own address 2 enable

Definition at line 1171 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_OAR2_OA2MSK

#define MCCI_STM32L0_I2C_OAR2_OA2MSK   (UINT32_C(0x7) << 8)

own address 2 masks [2:0]

Definition at line 1173 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_OAR2_RSV0

#define MCCI_STM32L0_I2C_OAR2_RSV0   (UINT32_C(1) << 0)

reserved: do not change

Definition at line 1175 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_OAR2_RSV11

#define MCCI_STM32L0_I2C_OAR2_RSV11   (UINT32_C(0xF) << 11)

reserved: do not change

Definition at line 1172 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_OAR2_RSV16

#define MCCI_STM32L0_I2C_OAR2_RSV16   UINT32_C(0xFFFF0000)

reserved: do not change

Definition at line 1170 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_PECR

#define MCCI_STM32L0_I2C_PECR   UINT32_C(0x20)

Section 27.7.9: PEC register.

Definition at line 1112 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_RXDR

#define MCCI_STM32L0_I2C_RXDR   UINT32_C(0x24)

Section 27.7.10: receive data register.

Definition at line 1113 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_TIMEOUTR

#define MCCI_STM32L0_I2C_TIMEOUTR   UINT32_C(0x14)

Section 27.7.6: timeout register.

Definition at line 1109 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_TIMEOUTR_RSV13

#define MCCI_STM32L0_I2C_TIMEOUTR_RSV13   (UINT32_C(0x3) << 13)

reserved: do not change

Definition at line 1194 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_TIMEOUTR_RSV28

#define MCCI_STM32L0_I2C_TIMEOUTR_RSV28   (UINT32_C(0x7) << 28)

reserved: do not change

Definition at line 1191 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_TIMEOUTR_TEXTEN

#define MCCI_STM32L0_I2C_TIMEOUTR_TEXTEN   (UINT32_C(1) << 31)

extended clock timeout enable

Definition at line 1190 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_TIMEOUTR_TIDLE

#define MCCI_STM32L0_I2C_TIMEOUTR_TIDLE   (UINT32_C(1) << 12)

idle clock timeout detection

Definition at line 1195 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_TIMEOUTR_TIMEOUTA

#define MCCI_STM32L0_I2C_TIMEOUTR_TIMEOUTA   (UINT32_C(0xFFF) << 0)

bus timeout A [11:0]

Definition at line 1196 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_TIMEOUTR_TIMEOUTB

#define MCCI_STM32L0_I2C_TIMEOUTR_TIMEOUTB   (UINT32_C(0xFFF) << 16)

bus timeout B [11:0]

Definition at line 1192 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_TIMEOUTR_TIMOUTEN

#define MCCI_STM32L0_I2C_TIMEOUTR_TIMOUTEN   (UINT32_C(1) << 15)

clock timeout enable

Definition at line 1193 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_TIMINGR

#define MCCI_STM32L0_I2C_TIMINGR   UINT32_C(0x10)

Section 27.7.5: timing register.

Definition at line 1108 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_TIMINGR_PRESC

#define MCCI_STM32L0_I2C_TIMINGR_PRESC   (UINT32_C(0xF) << 28)

timing prescaler [3:0]

Definition at line 1180 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_TIMINGR_RSV24

#define MCCI_STM32L0_I2C_TIMINGR_RSV24   (UINT32_C(0xF) << 24)

reserved: do not change

Definition at line 1181 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_TIMINGR_SCLDEL

#define MCCI_STM32L0_I2C_TIMINGR_SCLDEL   (UINT32_C(0xF) << 20)

data setup time [3:0]

Definition at line 1182 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_TIMINGR_SCLH

#define MCCI_STM32L0_I2C_TIMINGR_SCLH   (UINT32_C(0xFF) << 8)

SCL high period [7:0] (master)

Definition at line 1184 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_TIMINGR_SCLL

#define MCCI_STM32L0_I2C_TIMINGR_SCLL   (UINT32_C(0xFF) << 0)

SCL low period [7:0] (master)

Definition at line 1185 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_TIMINGR_SDADEL

#define MCCI_STM32L0_I2C_TIMINGR_SDADEL   (UINT32_C(0xF) << 16)

data hold time [3:0]

Definition at line 1183 of file mcci_stm32l0xx.h.

MCCI_STM32L0_I2C_TXDR

#define MCCI_STM32L0_I2C_TXDR   UINT32_C(0x28)

Section 27.7.11: transmit data register.

Definition at line 1114 of file mcci_stm32l0xx.h.

MCCI_STM32L0_MEMORY_EEPROM

#define MCCI_STM32L0_MEMORY_EEPROM   UINT32_C(0x08080000)

Data EEPROM (up to 6K)

Definition at line 50 of file mcci_stm32l0xx.h.

MCCI_STM32L0_MEMORY_FLASH

#define MCCI_STM32L0_MEMORY_FLASH   UINT32_C(0x08000000)

Flash program memory (up to 192K)

Definition at line 49 of file mcci_stm32l0xx.h.

MCCI_STM32L0_MEMORY_SRAM

#define MCCI_STM32L0_MEMORY_SRAM   UINT32_C(0x20000000)

SRAM (up to 20K)

Definition at line 54 of file mcci_stm32l0xx.h.

MCCI_STM32L0_MEMORY_SYSTEM

#define MCCI_STM32L0_MEMORY_SYSTEM   UINT32_C(0x1FF00000)

System memory (8K)

Definition at line 51 of file mcci_stm32l0xx.h.

MCCI_STM32L0_OPTIONS_FACTORY

#define MCCI_STM32L0_OPTIONS_FACTORY   UINT32_C(0x1FF80020)

Factory option bytes (96)

Definition at line 53 of file mcci_stm32l0xx.h.

MCCI_STM32L0_OPTIONS_MAKE_DWORD

#define MCCI_STM32L0_OPTIONS_MAKE_DWORD

(

v

)

((~(uint32_t)(v) << 16) | (uint16_t)(v))

create an option dword from a 16-bit value (high 16 bits inverted copy of low)

Definition at line 115 of file mcci_stm32l0xx.h.

MCCI_STM32L0_OPTIONS_SYSTEM_FLASH_SIZE_16

#define MCCI_STM32L0_OPTIONS_SYSTEM_FLASH_SIZE_16   UINT32_C(0x1FF8007C)

memory size in k bytes (16 bits)

Definition at line 120 of file mcci_stm32l0xx.h.

MCCI_STM32L0_OPTIONS_SYSTEM_FLASH_SIZE_TO_BYTES

#define MCCI_STM32L0_OPTIONS_SYSTEM_FLASH_SIZE_TO_BYTES

(

h

)

(((h) & UINT32_C(0xFFFF)) * 1024)

convert flash_size_16 value to bytes

Definition at line 123 of file mcci_stm32l0xx.h.

MCCI_STM32L0_OPTIONS_U_ID_0

#define MCCI_STM32L0_OPTIONS_U_ID_0   UINT32_C(0x1FF80050)

register address: unique ID bits 31:0

Definition at line 126 of file mcci_stm32l0xx.h.

MCCI_STM32L0_OPTIONS_U_ID_4

#define MCCI_STM32L0_OPTIONS_U_ID_4   (MCCI_STM32L0_OPTIONS_U_ID_0 + 0x04)

register address: unique ID bits 63:32

Definition at line 127 of file mcci_stm32l0xx.h.

MCCI_STM32L0_OPTIONS_U_ID_8

#define MCCI_STM32L0_OPTIONS_U_ID_8   (MCCI_STM32L0_OPTIONS_U_ID_0 + 0x014)

register address: unique ID bits 95:64

Definition at line 128 of file mcci_stm32l0xx.h.

MCCI_STM32L0_OPTIONS_USER

#define MCCI_STM32L0_OPTIONS_USER   UINT32_C(0x1FF80000)

User option bytes (32)

Definition at line 52 of file mcci_stm32l0xx.h.

MCCI_STM32L0_OPTIONS_USER_FLASH_OPTR_HIGH

#define MCCI_STM32L0_OPTIONS_USER_FLASH_OPTR_HIGH   (MCCI_STM32L0_OPTIONS_USER + 0x04)

Definition at line 109 of file mcci_stm32l0xx.h.

MCCI_STM32L0_OPTIONS_USER_FLASH_OPTR_LOW

#define MCCI_STM32L0_OPTIONS_USER_FLASH_OPTR_LOW   (MCCI_STM32L0_OPTIONS_USER + 0x00)

Definition at line 108 of file mcci_stm32l0xx.h.

MCCI_STM32L0_OPTIONS_USER_FLASH_WRPROT1_HIGH

#define MCCI_STM32L0_OPTIONS_USER_FLASH_WRPROT1_HIGH   (MCCI_STM32L0_OPTIONS_USER + 0x0C)

Definition at line 111 of file mcci_stm32l0xx.h.

MCCI_STM32L0_OPTIONS_USER_FLASH_WRPROT1_LOW

#define MCCI_STM32L0_OPTIONS_USER_FLASH_WRPROT1_LOW   (MCCI_STM32L0_OPTIONS_USER + 0x08)

Definition at line 110 of file mcci_stm32l0xx.h.

MCCI_STM32L0_OPTIONS_USER_FLASH_WRPROT2

#define MCCI_STM32L0_OPTIONS_USER_FLASH_WRPROT2   (MCCI_STM32L0_OPTIONS_USER + 0x10)

Definition at line 112 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_ADC1

#define MCCI_STM32L0_REG_ADC1   UINT32_C(0x40012400)

Section 14.12.12: ADC register map (1K)

Definition at line 81 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_AES

#define MCCI_STM32L0_REG_AES   UINT32_C(0x40026000)

Section 18.12.13: AES register map (1K)

Definition at line 91 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_CRC

#define MCCI_STM32L0_REG_CRC   UINT32_C(0x40023000)

Section 4.4.6: CRC register map (1K)

Definition at line 88 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_CRS

#define MCCI_STM32L0_REG_CRS   UINT32_C(0x40006C00)

Section 8.6.5: CRS register map (1K)

Definition at line 71 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_DAC1

#define MCCI_STM32L0_REG_DAC1   UINT32_C(0x40007400)

Section 15.10.15: DAC register map (1K)

Definition at line 73 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_DBG

#define MCCI_STM32L0_REG_DBG   UINT32_C(0x40015800)

Section 32.10: DBG register map (1K)

Definition at line 84 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_DMA1

#define MCCI_STM32L0_REG_DMA1   UINT32_C(0x40020000)

Section 11.4.8: DMA register map (1K)

Definition at line 85 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_EXTI

#define MCCI_STM32L0_REG_EXTI   UINT32_C(0x40010400)

Section 13.5.7: EXTI register map (1K)

Definition at line 77 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FIREWALL

#define MCCI_STM32L0_REG_FIREWALL   UINT32_C(0x40011C00)

Section 5.4.8: Firewall register map (1K)

Definition at line 80 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH

#define MCCI_STM32L0_REG_FLASH   UINT32_C(0x40022000)

Section 3.7.11: Flash register map (1K)

Definition at line 87 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_ACR

#define MCCI_STM32L0_REG_FLASH_ACR   (MCCI_STM32L0_REG_FLASH + 0x00)

Flash access control register.

Definition at line 139 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_ACR_DISAB_BUF

#define MCCI_STM32L0_REG_FLASH_ACR_DISAB_BUF   (UINT32_C(1) << 5)

Disable read buffer.

Definition at line 155 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_ACR_LATENCY

#define MCCI_STM32L0_REG_FLASH_ACR_LATENCY   (UINT32_C(1) << 0)

NVM latency: 1 wait state (not zero wait state)

Definition at line 160 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_ACR_PRE_READ

#define MCCI_STM32L0_REG_FLASH_ACR_PRE_READ   (UINT32_C(1) << 6)

Enable pre-read.

Definition at line 154 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_ACR_PRFTEN

#define MCCI_STM32L0_REG_FLASH_ACR_PRFTEN   (UINT32_C(1) << 1)

prefetch enable

Definition at line 159 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_ACR_RSV2

#define MCCI_STM32L0_REG_FLASH_ACR_RSV2   (UINT32_C(1) << 2)

Reserved, don't change.

Definition at line 158 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_ACR_RSV7

#define MCCI_STM32L0_REG_FLASH_ACR_RSV7   UINT32_C(0xFFFFFF80)

Reserved, don't change.

Definition at line 153 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_ACR_RUN_PD

#define MCCI_STM32L0_REG_FLASH_ACR_RUN_PD   (UINT32_C(1) << 4)

power-down in run mode

Definition at line 156 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_ACR_SLEEP_PD

#define MCCI_STM32L0_REG_FLASH_ACR_SLEEP_PD   (UINT32_C(1) << 3)

power-down in sleep mode

Definition at line 157 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTKEYR

#define MCCI_STM32L0_REG_FLASH_OPTKEYR   (MCCI_STM32L0_REG_FLASH + 0x14)

Flash option bytes unlock key register.

Definition at line 144 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTKEYR_UNLOCK1

#define MCCI_STM32L0_REG_FLASH_OPTKEYR_UNLOCK1   UINT32_C(0xFBEAD9C8)

unlock word 1 for option bytes

Definition at line 204 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTKEYR_UNLOCK2

#define MCCI_STM32L0_REG_FLASH_OPTKEYR_UNLOCK2   UINT32_C(0x24252627)

unlock word 2 for option bytes

Definition at line 205 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTR

#define MCCI_STM32L0_REG_FLASH_OPTR   (MCCI_STM32L0_REG_FLASH + 0x1C)

Flash option bytes register.

Definition at line 146 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTR_BFB2

#define MCCI_STM32L0_REG_FLASH_OPTR_BFB2   (UINT32_C(1) << 23)

Boot from system memory (not bank 2)

Definition at line 231 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV

#define MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV   (UINT32_C(0xF) << 16)

brown-out reset level

Definition at line 236 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV_1v8

#define MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV_1v8   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV, 8)

Level 1 (1.8 V)

Definition at line 237 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV_2v0

#define MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV_2v0   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV, 9)

Level 2 (2.0 V)

Definition at line 238 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV_2v5

#define MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV_2v5   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV, 10)

Level 3 (2.5 V)

Definition at line 239 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV_2v7

#define MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV_2v7   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV, 11)

Level 4 (2.7 V)

Definition at line 240 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV_3v0

#define MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV_3v0   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_BOR_LEV, 12)

Level 5 (3.0 V)

Definition at line 241 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTR_nBOOT1

#define MCCI_STM32L0_REG_FLASH_OPTR_nBOOT1   (UINT32_C(1) << 31)

If boot0, boot from system rom (not RAM)

Definition at line 229 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTR_nRST_STDBY

#define MCCI_STM32L0_REG_FLASH_OPTR_nRST_STDBY   (UINT32_C(1) << 22)

do not generate reset when entering standby

Definition at line 232 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTR_nRST_STOP

#define MCCI_STM32L0_REG_FLASH_OPTR_nRST_STOP   (UINT32_C(1) << 21)

do not generate reset when entering stop

Definition at line 233 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTR_RDPROT

#define MCCI_STM32L0_REG_FLASH_OPTR_RDPROT   (UINT32_C(0xFF) << 0)

Read protection level.

Definition at line 246 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTR_RDPROT_L0

#define MCCI_STM32L0_REG_FLASH_OPTR_RDPROT_L0   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_RDPROT, 0xAA)

Definition at line 247 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTR_RDPROT_L1

#define MCCI_STM32L0_REG_FLASH_OPTR_RDPROT_L1   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_RDPROT, 0x0)

Definition at line 249 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTR_RDPROT_L2

#define MCCI_STM32L0_REG_FLASH_OPTR_RDPROT_L2   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_FLASH_OPTR_RDPROT, 0xCC)

Definition at line 248 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTR_RSV24

#define MCCI_STM32L0_REG_FLASH_OPTR_RSV24   (UINT32_C(0x7F) << 24)

Reserved, don't change.

Definition at line 230 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTR_RSV9

#define MCCI_STM32L0_REG_FLASH_OPTR_RSV9   (UINT32_C(0x7F) << 9)

Reserved, don't change.

Definition at line 243 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTR_WDG_SW

#define MCCI_STM32L0_REG_FLASH_OPTR_WDG_SW   (UINT32_C(1) << 20)

software (not hardware) watchdog

Definition at line 234 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_OPTR_WPRMOD

#define MCCI_STM32L0_REG_FLASH_OPTR_WPRMOD   (UINT32_C(1) << 8)

PCROP enabled (use WPROT for read protection)

Definition at line 244 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PDKEYR

#define MCCI_STM32L0_REG_FLASH_PDKEYR   (MCCI_STM32L0_REG_FLASH + 0x08)

Flash power-down key register.

Definition at line 141 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PDKEYR_UNLOCK1

#define MCCI_STM32L0_REG_FLASH_PDKEYR_UNLOCK1   UINT32_C(0x04152637)

unlock word 1 for RUN_PD

Definition at line 186 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PDKEYR_UNLOCK2

#define MCCI_STM32L0_REG_FLASH_PDKEYR_UNLOCK2   UINT32_C(0xFAFBFCFD)

unlock word 2 for RUN_PD

Definition at line 187 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PECR

#define MCCI_STM32L0_REG_FLASH_PECR   (MCCI_STM32L0_REG_FLASH + 0x04)

Flash program and erase control register.

Definition at line 140 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PECR_DATA

#define MCCI_STM32L0_REG_FLASH_PECR_DATA   (UINT32_C(1) << 4)

Select data memory.

Definition at line 177 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PECR_EOPIE

#define MCCI_STM32L0_REG_FLASH_PECR_EOPIE   (UINT32_C(1) << 16)

End of programming interrupt enable.

Definition at line 170 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PECR_ERASE

#define MCCI_STM32L0_REG_FLASH_PECR_ERASE   (UINT32_C(1) << 9)

Erase operation requested/not requested.

Definition at line 174 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PECR_ERRIE

#define MCCI_STM32L0_REG_FLASH_PECR_ERRIE   (UINT32_C(1) << 17)

Error interrupt enable.

Definition at line 169 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PECR_FIX

#define MCCI_STM32L0_REG_FLASH_PECR_FIX   (UINT32_C(1) << 8)

Atomatically erase before programming EEPROM and options.

Definition at line 175 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PECR_FPRG

#define MCCI_STM32L0_REG_FLASH_PECR_FPRG   (UINT32_C(1) << 10)

Enable half-page programming mode.

Definition at line 173 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PECR_NZDISABLE

#define MCCI_STM32L0_REG_FLASH_PECR_NZDISABLE   (UINT32_C(1) << 23)

Disable non-zero check.

Definition at line 166 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PECR_OBL_LAUNCH

#define MCCI_STM32L0_REG_FLASH_PECR_OBL_LAUNCH   (UINT32_C(1) << 18)

Reload option bytes and reset system.

Definition at line 168 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PECR_OPTLOCK

#define MCCI_STM32L0_REG_FLASH_PECR_OPTLOCK   (UINT32_C(1) << 2)

Lock option bytes.

Definition at line 179 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PECR_PARALLELBANK

#define MCCI_STM32L0_REG_FLASH_PECR_PARALLELBANK   (UINT32_C(1) << 15)

Parallel bank programming enable.

Definition at line 171 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PECR_PELOCK

#define MCCI_STM32L0_REG_FLASH_PECR_PELOCK   (UINT32_C(1) << 0)

Lock the FLASH_PECR register.

Definition at line 181 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PECR_PRGLOCK

#define MCCI_STM32L0_REG_FLASH_PECR_PRGLOCK   (UINT32_C(1) << 1)

Lock program memory.

Definition at line 180 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PECR_PROG

#define MCCI_STM32L0_REG_FLASH_PECR_PROG   (UINT32_C(1) << 3)

Select program memory.

Definition at line 178 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PECR_RSV11

#define MCCI_STM32L0_REG_FLASH_PECR_RSV11   (UINT32_C(0xF) << 11)

Reserved, don't change.

Definition at line 172 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PECR_RSV19

#define MCCI_STM32L0_REG_FLASH_PECR_RSV19   (UINT32_C(0xF) << 19)

Reserved, don't change.

Definition at line 167 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PECR_RSV24

#define MCCI_STM32L0_REG_FLASH_PECR_RSV24   UINT32_C(0xFF000000)

Reserved, don't change.

Definition at line 165 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PECR_RSV5

#define MCCI_STM32L0_REG_FLASH_PECR_RSV5   (UINT32_C(7) << 5)

Reserved, don't change.

Definition at line 176 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PEKEYR

#define MCCI_STM32L0_REG_FLASH_PEKEYR   (MCCI_STM32L0_REG_FLASH + 0x0C)

Flash PECR unlock key register.

Definition at line 142 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PEKEYR_UNLOCK1

#define MCCI_STM32L0_REG_FLASH_PEKEYR_UNLOCK1   UINT32_C(0x89ABCDEF)

unlock word 1 for PECR

Definition at line 192 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PEKEYR_UNLOCK2

#define MCCI_STM32L0_REG_FLASH_PEKEYR_UNLOCK2   UINT32_C(0x02030405)

unlock word 2 for PECR

Definition at line 193 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PRGKEYR

#define MCCI_STM32L0_REG_FLASH_PRGKEYR   (MCCI_STM32L0_REG_FLASH + 0x10)

Flash program/erase key register.

Definition at line 143 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PRGKEYR_UNLOCK1

#define MCCI_STM32L0_REG_FLASH_PRGKEYR_UNLOCK1   UINT32_C(0x8C9DAEBF)

unlock word 1 for PRGKEYR

Definition at line 198 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_PRGKEYR_UNLOCK2

#define MCCI_STM32L0_REG_FLASH_PRGKEYR_UNLOCK2   UINT32_C(0x13141516)

unlock word 2 for PRGKEYR

Definition at line 199 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_SR

#define MCCI_STM32L0_REG_FLASH_SR   (MCCI_STM32L0_REG_FLASH + 0x18)

Flash status register.

Definition at line 145 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_SR_BSY

#define MCCI_STM32L0_REG_FLASH_SR_BSY   (UINT32_C(1) << 0)

Busy doing write/erase.

Definition at line 224 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_SR_ENDHV

#define MCCI_STM32L0_REG_FLASH_SR_ENDHV   (UINT32_C(1) << 2)

High voltage is off (not on), not active.

Definition at line 222 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_SR_EOP

#define MCCI_STM32L0_REG_FLASH_SR_EOP   (UINT32_C(1) << 1)

End of program.

Definition at line 223 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_SR_FWWERR

#define MCCI_STM32L0_REG_FLASH_SR_FWWERR   (UINT32_C(1) << 17)

Write/erase aborted for fetch.

Definition at line 211 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_SR_NOTZEROERR

#define MCCI_STM32L0_REG_FLASH_SR_NOTZEROERR   (UINT32_C(1) << 16)

Attempt to program non-zero area.

Definition at line 212 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_SR_OPTVERR

#define MCCI_STM32L0_REG_FLASH_SR_OPTVERR   (UINT32_C(1) << 11)

Option valid error.

Definition at line 216 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_SR_PGAERR

#define MCCI_STM32L0_REG_FLASH_SR_PGAERR   (UINT32_C(1) << 9)

Programming alignment error.

Definition at line 218 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_SR_RDERR

#define MCCI_STM32L0_REG_FLASH_SR_RDERR   (UINT32_C(1) << 13)

Read-protection error.

Definition at line 214 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_SR_READY

#define MCCI_STM32L0_REG_FLASH_SR_READY   (UINT32_C(1) << 3)

NVM is ready.

Definition at line 221 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_SR_RSV12

#define MCCI_STM32L0_REG_FLASH_SR_RSV12   (UINT32_C(1) << 12)

Reserved, don't change.

Definition at line 215 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_SR_RSV14

#define MCCI_STM32L0_REG_FLASH_SR_RSV14   (UINT32_C(3) << 14)

Reserved, don't change.

Definition at line 213 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_SR_RSV18

#define MCCI_STM32L0_REG_FLASH_SR_RSV18   UINT32_C(0xFFFC0000)

Reserved, don't change.

Definition at line 210 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_SR_RSV4

#define MCCI_STM32L0_REG_FLASH_SR_RSV4   (UINT32_C(0xF) << 4)

Reserved, don't change.

Definition at line 220 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_SR_SIZERR

#define MCCI_STM32L0_REG_FLASH_SR_SIZERR   (UINT32_C(1) << 10)

Size error when programming.

Definition at line 217 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_SR_WRPERR

#define MCCI_STM32L0_REG_FLASH_SR_WRPERR   (UINT32_C(1) << 8)

write protection error.

Definition at line 219 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_WPROT1

#define MCCI_STM32L0_REG_FLASH_WPROT1   (MCCI_STM32L0_REG_FLASH + 0x20)

Flash write proection register 1.

Definition at line 147 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_WPROT2

#define MCCI_STM32L0_REG_FLASH_WPROT2   (MCCI_STM32L0_REG_FLASH + 0x80)

Flash write protection register 2.

Definition at line 148 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_FLASH_WPROTx_FOR_SECTOR

#define MCCI_STM32L0_REG_FLASH_WPROTx_FOR_SECTOR

(

s

)

((s) < 32 ? MCCI_STM32L0_REG_FLASH_WPROT1 : MCCI_STM32L0_REG_FLASH_WPROT2)

get reg offset for protection bit for sector s

Definition at line 270 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_GPIOA

#define MCCI_STM32L0_REG_GPIOA   UINT32_C(0x50000000)

Section 9.4.12: GPIO register map (1K)

Definition at line 92 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_GPIOB

#define MCCI_STM32L0_REG_GPIOB   UINT32_C(0x50000400)

Section 9.4.12: GPIO register map (1K)

Definition at line 93 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_GPIOC

#define MCCI_STM32L0_REG_GPIOC   UINT32_C(0x50000800)

Section 9.4.12: GPIO register map (1K)

Definition at line 94 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_GPIOD

#define MCCI_STM32L0_REG_GPIOD   UINT32_C(0x50000C00)

Section 9.4.12: GPIO register map (1K)

Definition at line 95 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_GPIOE

#define MCCI_STM32L0_REG_GPIOE   UINT32_C(0x50001000)

Section 9.4.12: GPIO register map (1K)

Definition at line 96 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_GPIOH

#define MCCI_STM32L0_REG_GPIOH   UINT32_C(0x50001C00)

Section 9.4.12: GPIO register map (1K)

Definition at line 97 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_I2C1

#define MCCI_STM32L0_REG_I2C1   UINT32_C(0x40005400)

Section 27.7.12: I2C register map (1K)

Definition at line 67 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_I2C2

#define MCCI_STM32L0_REG_I2C2   UINT32_C(0x40005800)

Section 27.7.12: I2C register map (1K)

Definition at line 68 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_I2C3

#define MCCI_STM32L0_REG_I2C3   UINT32_C(0x40007800)

Section 27.7.12: I2C register map (1K)

Definition at line 74 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_IWDG

#define MCCI_STM32L0_REG_IWDG   UINT32_C(0x40003000)

Section 24.4.6: IWDG register map (1K)

Definition at line 61 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_LPTIM1

#define MCCI_STM32L0_REG_LPTIM1   UINT32_C(0x40007C00)

Section 23.6.9: LPTIM register map (1K)

Definition at line 75 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_LPUART1

#define MCCI_STM32L0_REG_LPUART1   UINT32_C(0x40004800)

Section 29.7.10: LPUART register map (1K)

Definition at line 64 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR

#define MCCI_STM32L0_REG_PWR   UINT32_C(0x40007000)

Section 6.4.3: PWR register map (1K)

Definition at line 72 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR

#define MCCI_STM32L0_REG_PWR_CR   (MCCI_STM32L0_REG_PWR + 0x0)

Definition at line 290 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_CSBF

#define MCCI_STM32L0_REG_PWR_CR_CSBF   (UINT32_C(1) << 3)

clear the SBF standby flag

Definition at line 320 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_CWUF

#define MCCI_STM32L0_REG_PWR_CR_CWUF   (UINT32_C(1) << 2)

clear the wakeup flag

Definition at line 321 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_DBP

#define MCCI_STM32L0_REG_PWR_CR_DBP   (UINT32_C(1) << 8)

disable backup write protection

Definition at line 307 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_DS_EE_KOFF

#define MCCI_STM32L0_REG_PWR_CR_DS_EE_KOFF   (UINT32_C(1) << 13)

deep sleep mode with nv mem off

Definition at line 297 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_FWU

#define MCCI_STM32L0_REG_PWR_CR_FWU   (UINT32_C(1) << 10)

fast wakeup

Definition at line 305 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_LPRUN

#define MCCI_STM32L0_REG_PWR_CR_LPRUN   (UINT32_C(1) << 14)

Low power run mode.

Definition at line 296 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_LPSDSR

#define MCCI_STM32L0_REG_PWR_CR_LPSDSR   (UINT32_C(1) << 0)

low-power deep sleep/sleep/low-power run

Definition at line 323 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_PDDS

#define MCCI_STM32L0_REG_PWR_CR_PDDS   (UINT32_C(1) << 1)

power-down deep sleep

Definition at line 322 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_PLS

#define MCCI_STM32L0_REG_PWR_CR_PLS   (UINT32_C(7) << 5)

power voltage detector level

Definition at line 309 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_PLS_1V9

#define MCCI_STM32L0_REG_PWR_CR_PLS_1V9   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 0)

1.9 V

Definition at line 310 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_PLS_2V1

#define MCCI_STM32L0_REG_PWR_CR_PLS_2V1   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 1)

2.1 V

Definition at line 311 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_PLS_2V3

#define MCCI_STM32L0_REG_PWR_CR_PLS_2V3   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 2)

2.3 V

Definition at line 312 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_PLS_2V5

#define MCCI_STM32L0_REG_PWR_CR_PLS_2V5   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 3)

2.5 V

Definition at line 313 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_PLS_2V7

#define MCCI_STM32L0_REG_PWR_CR_PLS_2V7   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 4)

2.7 V

Definition at line 314 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_PLS_2V9

#define MCCI_STM32L0_REG_PWR_CR_PLS_2V9   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 5)

2.9 V

Definition at line 315 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_PLS_3V1

#define MCCI_STM32L0_REG_PWR_CR_PLS_3V1   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 6)

3.1 V

Definition at line 316 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_PLS_EXT

#define MCCI_STM32L0_REG_PWR_CR_PLS_EXT   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLS, 7)

Vrefint.

Definition at line 317 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_PVDE

#define MCCI_STM32L0_REG_PWR_CR_PVDE   (UINT32_C(1) << 4)

power voltage detector enabled

Definition at line 319 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_ULP

#define MCCI_STM32L0_REG_PWR_CR_ULP   (UINT32_C(1) << 9)

ultra low-power mode

Definition at line 306 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_VOS

#define MCCI_STM32L0_REG_PWR_CR_VOS   (UINT32_C(3) << 11)

voltage scaling range

Definition at line 299 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_VOS_1V2

#define MCCI_STM32L0_REG_PWR_CR_VOS_1V2   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_VOS, 3)

1.2V

Definition at line 303 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_VOS_1V5

#define MCCI_STM32L0_REG_PWR_CR_VOS_1V5   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_VOS, 2)

1.5V

Definition at line 302 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_VOS_1V8

#define MCCI_STM32L0_REG_PWR_CR_VOS_1V8   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_VOS, 1)

1.8V

Definition at line 301 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CR_VOS_NC

#define MCCI_STM32L0_REG_PWR_CR_VOS_NC   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_VOS, 0)

no change / not allowed

Definition at line 300 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CSR

#define MCCI_STM32L0_REG_PWR_CSR   (MCCI_STM32L0_REG_PWR + 0x4)

Definition at line 291 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CSR_EWUP1

#define MCCI_STM32L0_REG_PWR_CSR_EWUP1   (UINT32_C(1) << 8)

Enable WKUP pin 1.

Definition at line 331 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CSR_EWUP2

#define MCCI_STM32L0_REG_PWR_CSR_EWUP2   (UINT32_C(1) << 9)

Enable WKUP pin 2.

Definition at line 330 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CSR_EWUP3

#define MCCI_STM32L0_REG_PWR_CSR_EWUP3   (UINT32_C(1) << 10)

Enable WKUP pin 3.

Definition at line 329 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CSR_PVDO

#define MCCI_STM32L0_REG_PWR_CSR_PVDO   (UINT32_C(1) << 2)

PVD output.

Definition at line 336 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CSR_REGLPF

#define MCCI_STM32L0_REG_PWR_CSR_REGLPF   (UINT32_C(1) << 5)

Regulator low-power flag.

Definition at line 333 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CSR_RSV11

#define MCCI_STM32L0_REG_PWR_CSR_RSV11   UINT32C(0xFFFFF800)

reserved, do not change

Definition at line 328 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CSR_RSV6

#define MCCI_STM32L0_REG_PWR_CSR_RSV6   (UINT32_C(3) << 6)

Reserved, do not change.

Definition at line 332 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CSR_SBF

#define MCCI_STM32L0_REG_PWR_CSR_SBF   (UINT32_C(1) << 1)

Standby flag.

Definition at line 337 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CSR_VOSF

#define MCCI_STM32L0_REG_PWR_CSR_VOSF   (UINT32_C(1) << 4)

Voltage scaling select flag.

Definition at line 334 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CSR_VREFINTRDYF

#define MCCI_STM32L0_REG_PWR_CSR_VREFINTRDYF   (UINT32_C(1) << 3)

Vrefint ready flag.

Definition at line 335 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_PWR_CSR_WUF

#define MCCI_STM32L0_REG_PWR_CSR_WUF   (UINT32_C(1) << 0)

Wakeup flag.

Definition at line 338 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC

#define MCCI_STM32L0_REG_RCC   UINT32_C(0x40021000)

Section 7.3.22: RCC register map (1K)

Definition at line 86 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBENR

#define MCCI_STM32L0_REG_RCC_AHBENR   (MCCI_STM32L0_REG_RCC + 0x30)

AHB peripheral clock enable.

Definition at line 361 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBENR_CRCEN

#define MCCI_STM32L0_REG_RCC_AHBENR_CRCEN   (UINT32_C(1) << 12)

Definition at line 643 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBENR_CRYPEN

#define MCCI_STM32L0_REG_RCC_AHBENR_CRYPEN   (UINT32_C(1) << 24)

Definition at line 637 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBENR_DMAEN

#define MCCI_STM32L0_REG_RCC_AHBENR_DMAEN   (UINT32_C(1) << 0)

Definition at line 647 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBENR_MIFEN

#define MCCI_STM32L0_REG_RCC_AHBENR_MIFEN   (UINT32_C(1) << 8)

Definition at line 645 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBENR_RNGEN

#define MCCI_STM32L0_REG_RCC_AHBENR_RNGEN   (UINT32_C(1) << 20)

Definition at line 639 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBENR_RSV1

#define MCCI_STM32L0_REG_RCC_AHBENR_RSV1   (UINT32_C(0x7F) << 1)

Definition at line 646 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBENR_RSV13

#define MCCI_STM32L0_REG_RCC_AHBENR_RSV13   (UINT32_C(7) << 13)

Definition at line 642 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBENR_RSV17

#define MCCI_STM32L0_REG_RCC_AHBENR_RSV17   (UINT32_C(7) << 17)

Definition at line 640 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBENR_RSV21

#define MCCI_STM32L0_REG_RCC_AHBENR_RSV21   (UINT32_C(7) << 21)

Definition at line 638 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBENR_RSV25

#define MCCI_STM32L0_REG_RCC_AHBENR_RSV25   (UINT32_C(0x7F) << 25)

Definition at line 636 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBENR_RSV9

#define MCCI_STM32L0_REG_RCC_AHBENR_RSV9   (UINT32_C(7) << 9)

Definition at line 644 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBENR_TSCEN

#define MCCI_STM32L0_REG_RCC_AHBENR_TSCEN   (UINT32_C(1) << 16)

Definition at line 641 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBRSTR

#define MCCI_STM32L0_REG_RCC_AHBRSTR   (MCCI_STM32L0_REG_RCC + 0x20)

AHB peripheral reset.

Definition at line 357 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBRSTR_CRCRST

#define MCCI_STM32L0_REG_RCC_AHBRSTR_CRCRST   (UINT32_C(1) << 12)

Definition at line 570 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBRSTR_CRYPRST

#define MCCI_STM32L0_REG_RCC_AHBRSTR_CRYPRST   (UINT32_C(1) << 24)

Definition at line 564 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBRSTR_DMARST

#define MCCI_STM32L0_REG_RCC_AHBRSTR_DMARST   (UINT32_C(1) << 0)

Definition at line 574 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBRSTR_MIFRST

#define MCCI_STM32L0_REG_RCC_AHBRSTR_MIFRST   (UINT32_C(1) << 8)

Definition at line 572 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBRSTR_RNGRST

#define MCCI_STM32L0_REG_RCC_AHBRSTR_RNGRST   (UINT32_C(1) << 20)

Definition at line 566 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBRSTR_RSV1

#define MCCI_STM32L0_REG_RCC_AHBRSTR_RSV1   (UINT32_C(0x7F) << 1)

Definition at line 573 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBRSTR_RSV13

#define MCCI_STM32L0_REG_RCC_AHBRSTR_RSV13   (UINT32_C(7) << 13)

Definition at line 569 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBRSTR_RSV17

#define MCCI_STM32L0_REG_RCC_AHBRSTR_RSV17   (UINT32_C(7) << 17)

Definition at line 567 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBRSTR_RSV21

#define MCCI_STM32L0_REG_RCC_AHBRSTR_RSV21   (UINT32_C(7) << 21)

Definition at line 565 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBRSTR_RSV25

#define MCCI_STM32L0_REG_RCC_AHBRSTR_RSV25   (UINT32_C(0x7F) << 25)

Definition at line 563 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBRSTR_RSV9

#define MCCI_STM32L0_REG_RCC_AHBRSTR_RSV9   (UINT32_C(7) << 9)

Definition at line 571 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBRSTR_TSCRST

#define MCCI_STM32L0_REG_RCC_AHBRSTR_TSCRST   (UINT32_C(1) << 16)

Definition at line 568 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBSMENR

#define MCCI_STM32L0_REG_RCC_AHBSMENR   (MCCI_STM32L0_REG_RCC + 0x40)

AHB peripheral clock enable in sleep.

Definition at line 365 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBSMENR_CRCSMEN

#define MCCI_STM32L0_REG_RCC_AHBSMENR_CRCSMEN   (UINT32_C(1) << 12)

Definition at line 716 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBSMENR_CRYPSMEN

#define MCCI_STM32L0_REG_RCC_AHBSMENR_CRYPSMEN   (UINT32_C(1) << 24)

Definition at line 710 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBSMENR_DMASMEN

#define MCCI_STM32L0_REG_RCC_AHBSMENR_DMASMEN   (UINT32_C(1) << 0)

Definition at line 721 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBSMENR_MIFSMEN

#define MCCI_STM32L0_REG_RCC_AHBSMENR_MIFSMEN   (UINT32_C(1) << 8)

Definition at line 719 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBSMENR_RNGSMEN

#define MCCI_STM32L0_REG_RCC_AHBSMENR_RNGSMEN   (UINT32_C(1) << 20)

Definition at line 712 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBSMENR_RSV1

#define MCCI_STM32L0_REG_RCC_AHBSMENR_RSV1   (UINT32_C(0x7F) << 1)

Definition at line 720 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBSMENR_RSV10

#define MCCI_STM32L0_REG_RCC_AHBSMENR_RSV10   (UINT32_C(3) << 10)

Definition at line 717 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBSMENR_RSV13

#define MCCI_STM32L0_REG_RCC_AHBSMENR_RSV13   (UINT32_C(7) << 13)

Definition at line 715 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBSMENR_RSV17

#define MCCI_STM32L0_REG_RCC_AHBSMENR_RSV17   (UINT32_C(7) << 17)

Definition at line 713 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBSMENR_RSV21

#define MCCI_STM32L0_REG_RCC_AHBSMENR_RSV21   (UINT32_C(7) << 21)

Definition at line 711 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBSMENR_RSV25

#define MCCI_STM32L0_REG_RCC_AHBSMENR_RSV25   (UINT32_C(0x7F) << 25)

Definition at line 709 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBSMENR_SRAMSMEN

#define MCCI_STM32L0_REG_RCC_AHBSMENR_SRAMSMEN   (UINT32_C(1) << 9)

Definition at line 718 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_AHBSMENR_TSCSMEN

#define MCCI_STM32L0_REG_RCC_AHBSMENR_TSCSMEN   (UINT32_C(1) << 16)

Definition at line 714 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR

#define MCCI_STM32L0_REG_RCC_APB1ENR   (MCCI_STM32L0_REG_RCC + 0x38)

APB1 peripheral clock enable.

Definition at line 363 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_CRSEN

#define MCCI_STM32L0_REG_RCC_APB1ENR_CRSEN   (UINT32_C(1) << 27)

Definition at line 674 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_DACREN

#define MCCI_STM32L0_REG_RCC_APB1ENR_DACREN   (UINT32_C(1) << 29)

Definition at line 672 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_I2C1EN

#define MCCI_STM32L0_REG_RCC_APB1ENR_I2C1EN   (UINT32_C(1) << 21)

Definition at line 678 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_I2C2EN

#define MCCI_STM32L0_REG_RCC_APB1ENR_I2C2EN   (UINT32_C(1) << 22)

Definition at line 677 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_I2C3EN

#define MCCI_STM32L0_REG_RCC_APB1ENR_I2C3EN   (UINT32_C(1) << 30)

Definition at line 671 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_LPTIM1EN

#define MCCI_STM32L0_REG_RCC_APB1ENR_LPTIM1EN   (UINT32_C(1) << 31)

Definition at line 670 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_LPUART1EN

#define MCCI_STM32L0_REG_RCC_APB1ENR_LPUART1EN   (UINT32_C(1) << 18)

Definition at line 681 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_PWREN

#define MCCI_STM32L0_REG_RCC_APB1ENR_PWREN   (UINT32_C(1) << 28)

Definition at line 673 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_RSV12

#define MCCI_STM32L0_REG_RCC_APB1ENR_RSV12   (UINT32_C(3) << 12)

Definition at line 685 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_RSV15

#define MCCI_STM32L0_REG_RCC_APB1ENR_RSV15   (UINT32_C(3) << 15)

Definition at line 683 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_RSV2

#define MCCI_STM32L0_REG_RCC_APB1ENR_RSV2   (UINT32_C(3) << 2)

Definition at line 690 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_RSV24

#define MCCI_STM32L0_REG_RCC_APB1ENR_RSV24   (UINT32_C(7) << 24)

Definition at line 675 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_RSV6

#define MCCI_STM32L0_REG_RCC_APB1ENR_RSV6   (UINT32_C(0x1F) << 6)

Definition at line 687 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_SPI2EN

#define MCCI_STM32L0_REG_RCC_APB1ENR_SPI2EN   (UINT32_C(1) << 14)

Definition at line 684 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_TIM2

#define MCCI_STM32L0_REG_RCC_APB1ENR_TIM2   (UINT32_C(1) << 0)

Definition at line 692 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_TIM3

#define MCCI_STM32L0_REG_RCC_APB1ENR_TIM3   (UINT32_C(1) << 1)

Definition at line 691 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_TIM6EN

#define MCCI_STM32L0_REG_RCC_APB1ENR_TIM6EN   (UINT32_C(1) << 4)

Definition at line 689 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_TIM7EN

#define MCCI_STM32L0_REG_RCC_APB1ENR_TIM7EN   (UINT32_C(1) << 5)

Definition at line 688 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_USART2EN

#define MCCI_STM32L0_REG_RCC_APB1ENR_USART2EN   (UINT32_C(1) << 17)

Definition at line 682 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_USART4EN

#define MCCI_STM32L0_REG_RCC_APB1ENR_USART4EN   (UINT32_C(1) << 19)

Definition at line 680 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_USART5EN

#define MCCI_STM32L0_REG_RCC_APB1ENR_USART5EN   (UINT32_C(1) << 20)

Definition at line 679 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_USBEN

#define MCCI_STM32L0_REG_RCC_APB1ENR_USBEN   (UINT32_C(1) << 23)

Definition at line 676 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1ENR_WWDGEN

#define MCCI_STM32L0_REG_RCC_APB1ENR_WWDGEN   (UINT32_C(1) << 11)

Definition at line 686 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR

#define MCCI_STM32L0_REG_RCC_APB1RSTR   (MCCI_STM32L0_REG_RCC + 0x28)

APB1 peripheral reset.

Definition at line 359 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_CRSRST

#define MCCI_STM32L0_REG_RCC_APB1RSTR_CRSRST   (UINT32_C(1) << 27)

Definition at line 601 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_DACRRST

#define MCCI_STM32L0_REG_RCC_APB1RSTR_DACRRST   (UINT32_C(1) << 29)

Definition at line 599 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_I2C1RST

#define MCCI_STM32L0_REG_RCC_APB1RSTR_I2C1RST   (UINT32_C(1) << 21)

Definition at line 605 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_I2C2RST

#define MCCI_STM32L0_REG_RCC_APB1RSTR_I2C2RST   (UINT32_C(1) << 22)

Definition at line 604 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_I2C3RST

#define MCCI_STM32L0_REG_RCC_APB1RSTR_I2C3RST   (UINT32_C(1) << 30)

Definition at line 598 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_LPTIM1RST

#define MCCI_STM32L0_REG_RCC_APB1RSTR_LPTIM1RST   (UINT32_C(1) << 31)

Definition at line 597 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_LPUART1RST

#define MCCI_STM32L0_REG_RCC_APB1RSTR_LPUART1RST   (UINT32_C(1) << 18)

Definition at line 608 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_PWRRST

#define MCCI_STM32L0_REG_RCC_APB1RSTR_PWRRST   (UINT32_C(1) << 28)

Definition at line 600 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_RSV12

#define MCCI_STM32L0_REG_RCC_APB1RSTR_RSV12   (UINT32_C(3) << 12)

Definition at line 612 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_RSV15

#define MCCI_STM32L0_REG_RCC_APB1RSTR_RSV15   (UINT32_C(3) << 15)

Definition at line 610 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_RSV2

#define MCCI_STM32L0_REG_RCC_APB1RSTR_RSV2   (UINT32_C(3) << 2)

Definition at line 617 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_RSV24

#define MCCI_STM32L0_REG_RCC_APB1RSTR_RSV24   (UINT32_C(7) << 24)

Definition at line 602 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_RSV6

#define MCCI_STM32L0_REG_RCC_APB1RSTR_RSV6   (UINT32_C(0x1F) << 6)

Definition at line 614 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_SPI2RST

#define MCCI_STM32L0_REG_RCC_APB1RSTR_SPI2RST   (UINT32_C(1) << 14)

Definition at line 611 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_TIM2

#define MCCI_STM32L0_REG_RCC_APB1RSTR_TIM2   (UINT32_C(1) << 0)

Definition at line 619 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_TIM3

#define MCCI_STM32L0_REG_RCC_APB1RSTR_TIM3   (UINT32_C(1) << 1)

Definition at line 618 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_TIM6RST

#define MCCI_STM32L0_REG_RCC_APB1RSTR_TIM6RST   (UINT32_C(1) << 4)

Definition at line 616 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_TIM7RST

#define MCCI_STM32L0_REG_RCC_APB1RSTR_TIM7RST   (UINT32_C(1) << 5)

Definition at line 615 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_USART2RST

#define MCCI_STM32L0_REG_RCC_APB1RSTR_USART2RST   (UINT32_C(1) << 17)

Definition at line 609 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_USART4RST

#define MCCI_STM32L0_REG_RCC_APB1RSTR_USART4RST   (UINT32_C(1) << 19)

Definition at line 607 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_USART5RST

#define MCCI_STM32L0_REG_RCC_APB1RSTR_USART5RST   (UINT32_C(1) << 20)

Definition at line 606 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_USBRST

#define MCCI_STM32L0_REG_RCC_APB1RSTR_USBRST   (UINT32_C(1) << 23)

Definition at line 603 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1RSTR_WWDGRST

#define MCCI_STM32L0_REG_RCC_APB1RSTR_WWDGRST   (UINT32_C(1) << 11)

Definition at line 613 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR

#define MCCI_STM32L0_REG_RCC_APB1SMENR   (MCCI_STM32L0_REG_RCC + 0x48)

APB1 peripheral clock enable in sleep.

Definition at line 367 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_CRSSMEN

#define MCCI_STM32L0_REG_RCC_APB1SMENR_CRSSMEN   (UINT32_C(1) << 27)

Definition at line 748 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_DACRSMEN

#define MCCI_STM32L0_REG_RCC_APB1SMENR_DACRSMEN   (UINT32_C(1) << 29)

Definition at line 746 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_I2C1SMEN

#define MCCI_STM32L0_REG_RCC_APB1SMENR_I2C1SMEN   (UINT32_C(1) << 21)

Definition at line 752 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_I2C2SMEN

#define MCCI_STM32L0_REG_RCC_APB1SMENR_I2C2SMEN   (UINT32_C(1) << 22)

Definition at line 751 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_I2C3SMEN

#define MCCI_STM32L0_REG_RCC_APB1SMENR_I2C3SMEN   (UINT32_C(1) << 30)

Definition at line 745 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_LPTIM1SMEN

#define MCCI_STM32L0_REG_RCC_APB1SMENR_LPTIM1SMEN   (UINT32_C(1) << 31)

Definition at line 744 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_LPUART1SMEN

#define MCCI_STM32L0_REG_RCC_APB1SMENR_LPUART1SMEN   (UINT32_C(1) << 18)

Definition at line 755 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_PWRSMEN

#define MCCI_STM32L0_REG_RCC_APB1SMENR_PWRSMEN   (UINT32_C(1) << 28)

Definition at line 747 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_RSV12

#define MCCI_STM32L0_REG_RCC_APB1SMENR_RSV12   (UINT32_C(3) << 12)

Definition at line 759 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_RSV15

#define MCCI_STM32L0_REG_RCC_APB1SMENR_RSV15   (UINT32_C(3) << 15)

Definition at line 757 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_RSV2

#define MCCI_STM32L0_REG_RCC_APB1SMENR_RSV2   (UINT32_C(3) << 2)

Definition at line 764 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_RSV24

#define MCCI_STM32L0_REG_RCC_APB1SMENR_RSV24   (UINT32_C(7) << 24)

Definition at line 749 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_RSV6

#define MCCI_STM32L0_REG_RCC_APB1SMENR_RSV6   (UINT32_C(0x1F) << 6)

Definition at line 761 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_SPI2SMEN

#define MCCI_STM32L0_REG_RCC_APB1SMENR_SPI2SMEN   (UINT32_C(1) << 14)

Definition at line 758 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_TIM2

#define MCCI_STM32L0_REG_RCC_APB1SMENR_TIM2   (UINT32_C(1) << 0)

Definition at line 766 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_TIM3

#define MCCI_STM32L0_REG_RCC_APB1SMENR_TIM3   (UINT32_C(1) << 1)

Definition at line 765 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_TIM6SMEN

#define MCCI_STM32L0_REG_RCC_APB1SMENR_TIM6SMEN   (UINT32_C(1) << 4)

Definition at line 763 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_TIM7SMEN

#define MCCI_STM32L0_REG_RCC_APB1SMENR_TIM7SMEN   (UINT32_C(1) << 5)

Definition at line 762 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_USART2SMEN

#define MCCI_STM32L0_REG_RCC_APB1SMENR_USART2SMEN   (UINT32_C(1) << 17)

Definition at line 756 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_USART4SMEN

#define MCCI_STM32L0_REG_RCC_APB1SMENR_USART4SMEN   (UINT32_C(1) << 19)

Definition at line 754 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_USART5SMEN

#define MCCI_STM32L0_REG_RCC_APB1SMENR_USART5SMEN   (UINT32_C(1) << 20)

Definition at line 753 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_USBSMEN

#define MCCI_STM32L0_REG_RCC_APB1SMENR_USBSMEN   (UINT32_C(1) << 23)

Definition at line 750 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB1SMENR_WWDGSMEN

#define MCCI_STM32L0_REG_RCC_APB1SMENR_WWDGSMEN   (UINT32_C(1) << 11)

Definition at line 760 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2ENR

#define MCCI_STM32L0_REG_RCC_APB2ENR   (MCCI_STM32L0_REG_RCC + 0x34)

APB2 peripheral clock enable.

Definition at line 362 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2ENR_ADCEN

#define MCCI_STM32L0_REG_RCC_APB2ENR_ADCEN   (UINT32_C(1) << 9)

ADC enable.

Definition at line 659 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2ENR_DBGEN

#define MCCI_STM32L0_REG_RCC_APB2ENR_DBGEN   (UINT32_C(1) << 22)

Debug enable.

Definition at line 653 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2ENR_RSV1

#define MCCI_STM32L0_REG_RCC_APB2ENR_RSV1   (UINT32_C(1) << 1)

reserved, don't change

Definition at line 664 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2ENR_RSV10

#define MCCI_STM32L0_REG_RCC_APB2ENR_RSV10   (UINT32_C(3) << 10)

reserved, don't change

Definition at line 658 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2ENR_RSV13

#define MCCI_STM32L0_REG_RCC_APB2ENR_RSV13   (UINT32_C(1) << 13)

reserved, don't change

Definition at line 656 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2ENR_RSV15

#define MCCI_STM32L0_REG_RCC_APB2ENR_RSV15   (UINT32_C(0x7F) << 15)

reserved, don't change

Definition at line 654 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2ENR_RSV23

#define MCCI_STM32L0_REG_RCC_APB2ENR_RSV23   UINT32_C(0xFF800000)

reserved, don't change

Definition at line 652 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2ENR_RSV3

#define MCCI_STM32L0_REG_RCC_APB2ENR_RSV3   (UINT32_C(3) << 3)

reserved, don't change

Definition at line 662 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2ENR_RSV6

#define MCCI_STM32L0_REG_RCC_APB2ENR_RSV6   (UINT32_C(7) << 6)

reserved, don't change

Definition at line 660 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2ENR_SPI1EN

#define MCCI_STM32L0_REG_RCC_APB2ENR_SPI1EN   (UINT32_C(1) << 12)

SPI1 enable.

Definition at line 657 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2ENR_SYSCFEN

#define MCCI_STM32L0_REG_RCC_APB2ENR_SYSCFEN   (UINT32_C(1) << 0)

SYSCFG enable.

Definition at line 665 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2ENR_TIM21EN

#define MCCI_STM32L0_REG_RCC_APB2ENR_TIM21EN   (UINT32_C(1) << 2)

TIM21 enable.

Definition at line 663 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2ENR_TIM22EN

#define MCCI_STM32L0_REG_RCC_APB2ENR_TIM22EN   (UINT32_C(1) << 5)

TIM22 enable.

Definition at line 661 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2ENR_USART1EN

#define MCCI_STM32L0_REG_RCC_APB2ENR_USART1EN   (UINT32_C(1) << 14)

USART1 enable.

Definition at line 655 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2RSTR

#define MCCI_STM32L0_REG_RCC_APB2RSTR   (MCCI_STM32L0_REG_RCC + 0x24)

APB2 peripheral reset.

Definition at line 358 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2RSTR_ADCRST

#define MCCI_STM32L0_REG_RCC_APB2RSTR_ADCRST   (UINT32_C(1) << 9)

ADC reset.

Definition at line 586 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2RSTR_DBGRST

#define MCCI_STM32L0_REG_RCC_APB2RSTR_DBGRST   (UINT32_C(1) << 22)

Debug reset.

Definition at line 580 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2RSTR_RSV1

#define MCCI_STM32L0_REG_RCC_APB2RSTR_RSV1   (UINT32_C(1) << 1)

reserved, don't change

Definition at line 591 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2RSTR_RSV10

#define MCCI_STM32L0_REG_RCC_APB2RSTR_RSV10   (UINT32_C(3) << 10)

reserved, don't change

Definition at line 585 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2RSTR_RSV13

#define MCCI_STM32L0_REG_RCC_APB2RSTR_RSV13   (UINT32_C(1) << 13)

reserved, don't change

Definition at line 583 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2RSTR_RSV15

#define MCCI_STM32L0_REG_RCC_APB2RSTR_RSV15   (UINT32_C(0x7F) << 15)

reserved, don't change

Definition at line 581 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2RSTR_RSV23

#define MCCI_STM32L0_REG_RCC_APB2RSTR_RSV23   UINT32_C(0xFF800000)

reserved, don't change

Definition at line 579 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2RSTR_RSV3

#define MCCI_STM32L0_REG_RCC_APB2RSTR_RSV3   (UINT32_C(3) << 3)

reserved, don't change

Definition at line 589 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2RSTR_RSV6

#define MCCI_STM32L0_REG_RCC_APB2RSTR_RSV6   (UINT32_C(7) << 6)

reserved, don't change

Definition at line 587 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2RSTR_SPI1RST

#define MCCI_STM32L0_REG_RCC_APB2RSTR_SPI1RST   (UINT32_C(1) << 12)

SPI1 reset.

Definition at line 584 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2RSTR_SYSCFRST

#define MCCI_STM32L0_REG_RCC_APB2RSTR_SYSCFRST   (UINT32_C(1) << 0)

SYSCFG reset.

Definition at line 592 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2RSTR_TIM21RST

#define MCCI_STM32L0_REG_RCC_APB2RSTR_TIM21RST   (UINT32_C(1) << 2)

TIM21 reset.

Definition at line 590 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2RSTR_TIM22RST

#define MCCI_STM32L0_REG_RCC_APB2RSTR_TIM22RST   (UINT32_C(1) << 5)

TIM22 reset.

Definition at line 588 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2RSTR_USART1RST

#define MCCI_STM32L0_REG_RCC_APB2RSTR_USART1RST   (UINT32_C(1) << 14)

USART1 reset.

Definition at line 582 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2SMENR

#define MCCI_STM32L0_REG_RCC_APB2SMENR   (MCCI_STM32L0_REG_RCC + 0x44)

APB2 peripheral clock enable in sleep.

Definition at line 366 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2SMENR_ADCSMEN

#define MCCI_STM32L0_REG_RCC_APB2SMENR_ADCSMEN   (UINT32_C(1) << 9)

ADC sleep-mode enable.

Definition at line 733 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2SMENR_DBGSMEN

#define MCCI_STM32L0_REG_RCC_APB2SMENR_DBGSMEN   (UINT32_C(1) << 22)

Debug sleep-mode enable.

Definition at line 727 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2SMENR_RSV1

#define MCCI_STM32L0_REG_RCC_APB2SMENR_RSV1   (UINT32_C(1) << 1)

reserved, don't change

Definition at line 738 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2SMENR_RSV10

#define MCCI_STM32L0_REG_RCC_APB2SMENR_RSV10   (UINT32_C(3) << 10)

reserved, don't change

Definition at line 732 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2SMENR_RSV13

#define MCCI_STM32L0_REG_RCC_APB2SMENR_RSV13   (UINT32_C(1) << 13)

reserved, don't change

Definition at line 730 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2SMENR_RSV15

#define MCCI_STM32L0_REG_RCC_APB2SMENR_RSV15   (UINT32_C(0x7F) << 15)

reserved, don't change

Definition at line 728 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2SMENR_RSV23

#define MCCI_STM32L0_REG_RCC_APB2SMENR_RSV23   UINT32_C(0xFF800000)

reserved, don't change

Definition at line 726 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2SMENR_RSV3

#define MCCI_STM32L0_REG_RCC_APB2SMENR_RSV3   (UINT32_C(3) << 3)

reserved, don't change

Definition at line 736 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2SMENR_RSV6

#define MCCI_STM32L0_REG_RCC_APB2SMENR_RSV6   (UINT32_C(7) << 6)

reserved, don't change

Definition at line 734 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2SMENR_SPI1SMEN

#define MCCI_STM32L0_REG_RCC_APB2SMENR_SPI1SMEN   (UINT32_C(1) << 12)

SPI1 sleep-mode enable.

Definition at line 731 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2SMENR_SYSCFSMEN

#define MCCI_STM32L0_REG_RCC_APB2SMENR_SYSCFSMEN   (UINT32_C(1) << 0)

SYSCFG sleep-mode enable.

Definition at line 739 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2SMENR_TIM21SMEN

#define MCCI_STM32L0_REG_RCC_APB2SMENR_TIM21SMEN   (UINT32_C(1) << 2)

TIM21 sleep-mode enable.

Definition at line 737 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2SMENR_TIM22SMEN

#define MCCI_STM32L0_REG_RCC_APB2SMENR_TIM22SMEN   (UINT32_C(1) << 5)

TIM22 sleep-mode enable.

Definition at line 735 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_APB2SMENR_USART1SMEN

#define MCCI_STM32L0_REG_RCC_APB2SMENR_USART1SMEN   (UINT32_C(1) << 14)

USART1 sleep-mode enable.

Definition at line 729 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR

#define MCCI_STM32L0_REG_RCC_CCIPR   (MCCI_STM32L0_REG_RCC + 0x4C)

Clock configuration CCIPR.

Definition at line 368 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_HSI48SEL

#define MCCI_STM32L0_REG_RCC_CCIPR_HSI48SEL   (UINT32_C(1) << 26)

Definition at line 772 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL

#define MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL   (UINT32_C(3) << 12)

Definition at line 787 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL_APB

#define MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL_APB   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL, 0)

Definition at line 788 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL_HSI16

#define MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL, 2)

Definition at line 790 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL_LSI

#define MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL_LSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_I2C1SEL, 1)

Definition at line 789 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL

#define MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL   (UINT32_C(3) << 16)

Definition at line 781 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL_APB

#define MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL_APB   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL, 0)

Definition at line 782 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL_HSI16

#define MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL, 2)

Definition at line 784 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL_LSI

#define MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL_LSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_I2C3SEL, 1)

Definition at line 783 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL

#define MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL   (UINT32_C(3) << 18)

Definition at line 775 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL_APB

#define MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL_APB   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL, 0)

Definition at line 776 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL_HSI16

#define MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL, 2)

Definition at line 778 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL_LSE

#define MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL_LSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL, 3)

Definition at line 779 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL_LSI

#define MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL_LSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPTIM1SEL, 1)

Definition at line 777 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL

#define MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL   (UINT32_C(3) << 10)

Definition at line 792 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL_APB

#define MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL_APB   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL, 0)

Definition at line 793 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL_HSI16

#define MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL, 2)

Definition at line 795 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL_LSE

#define MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL_LSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL, 3)

Definition at line 796 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL_LSI

#define MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL_LSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_LPUART1SEL, 1)

Definition at line 794 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_RSV14

#define MCCI_STM32L0_REG_RCC_CCIPR_RSV14   (UINT32_C(3) << 14)

Definition at line 786 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_RSV20

#define MCCI_STM32L0_REG_RCC_CCIPR_RSV20   (UINT32_C(0x3F) << 20)

Definition at line 773 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_RSV27

#define MCCI_STM32L0_REG_RCC_CCIPR_RSV27   (UINT32_C(0x1F) << 27)

Definition at line 771 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_RSV4

#define MCCI_STM32L0_REG_RCC_CCIPR_RSV4   (UINT32_C(0x3F) << 4)

Definition at line 798 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL

#define MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL   (UINT32_C(3) << 0)

Definition at line 806 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL_APB

#define MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL_APB   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL, 0)

Definition at line 807 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL_HSI16

#define MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL, 2)

Definition at line 809 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL_LSE

#define MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL_LSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL, 3)

Definition at line 810 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL_LSI

#define MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL_LSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART1SEL, 1)

Definition at line 808 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL

#define MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL   (UINT32_C(3) << 2)

Definition at line 800 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL_APB

#define MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL_APB   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL, 0)

Definition at line 801 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL_HSI16

#define MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL, 2)

Definition at line 803 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL_LSE

#define MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL_LSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL, 3)

Definition at line 804 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL_LSI

#define MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL_LSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CCIPR_USART2SEL, 1)

Definition at line 802 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR

#define MCCI_STM32L0_REG_RCC_CFGR   (MCCI_STM32L0_REG_RCC + 0x0C)

Clock configuration.

Definition at line 352 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_HPRE

#define MCCI_STM32L0_REG_RCC_CFGR_HPRE   (UINT32_C(0xF) << 4)

Definition at line 486 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_HPRE_1

#define MCCI_STM32L0_REG_RCC_CFGR_HPRE_1   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 0)

Definition at line 487 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_HPRE_128

#define MCCI_STM32L0_REG_RCC_CFGR_HPRE_128   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 13)

Definition at line 493 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_HPRE_16

#define MCCI_STM32L0_REG_RCC_CFGR_HPRE_16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 11)

Definition at line 491 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_HPRE_2

#define MCCI_STM32L0_REG_RCC_CFGR_HPRE_2   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 8)

Definition at line 488 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_HPRE_256

#define MCCI_STM32L0_REG_RCC_CFGR_HPRE_256   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 14)

Definition at line 494 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_HPRE_4

#define MCCI_STM32L0_REG_RCC_CFGR_HPRE_4   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 9)

Definition at line 489 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_HPRE_512

#define MCCI_STM32L0_REG_RCC_CFGR_HPRE_512   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 15)

Definition at line 495 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_HPRE_64

#define MCCI_STM32L0_REG_RCC_CFGR_HPRE_64   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 12)

Definition at line 492 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_HPRE_8

#define MCCI_STM32L0_REG_RCC_CFGR_HPRE_8   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_HPRE, 10)

Definition at line 490 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_MCOPRE

#define MCCI_STM32L0_REG_RCC_CFGR_MCOPRE   (UINT32_C(7) << 28)

Definition at line 431 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_MCOPRE_1

#define MCCI_STM32L0_REG_RCC_CFGR_MCOPRE_1   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOPRE, 0)

Definition at line 432 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_MCOPRE_16

#define MCCI_STM32L0_REG_RCC_CFGR_MCOPRE_16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOPRE, 4)

Definition at line 436 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_MCOPRE_2

#define MCCI_STM32L0_REG_RCC_CFGR_MCOPRE_2   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOPRE, 1)

Definition at line 433 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_MCOPRE_4

#define MCCI_STM32L0_REG_RCC_CFGR_MCOPRE_4   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOPRE, 2)

Definition at line 434 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_MCOPRE_8

#define MCCI_STM32L0_REG_RCC_CFGR_MCOPRE_8   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOPRE, 3)

Definition at line 435 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_MCOSEL

#define MCCI_STM32L0_REG_RCC_CFGR_MCOSEL   (UINT32_C(0xF) << 24)

Definition at line 438 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_HSE

#define MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_HSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 4)

Definition at line 443 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_HSI16

#define MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 2)

Definition at line 441 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_HSI48

#define MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_HSI48   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 8)

Definition at line 447 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_LSE

#define MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_LSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 7)

Definition at line 446 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_LSI

#define MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_LSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 6)

Definition at line 445 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_MSI

#define MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_MSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 3)

Definition at line 442 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_OFF

#define MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_OFF   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 0)

Definition at line 439 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_PLL

#define MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_PLL   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 5)

Definition at line 444 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_SYSCLK

#define MCCI_STM32L0_REG_RCC_CFGR_MCOSEL_SYSCLK   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_MCOSEL, 1)

Definition at line 440 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PLLDIV

#define MCCI_STM32L0_REG_RCC_CFGR_PLLDIV   (UINT32_C(3) << 22)

Definition at line 449 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PLLDIV_2

#define MCCI_STM32L0_REG_RCC_CFGR_PLLDIV_2   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLDIV, 1)

Definition at line 450 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PLLDIV_3

#define MCCI_STM32L0_REG_RCC_CFGR_PLLDIV_3   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLDIV, 2)

Definition at line 451 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PLLDIV_4

#define MCCI_STM32L0_REG_RCC_CFGR_PLLDIV_4   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLDIV, 3)

Definition at line 452 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PLLMUL

#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL   (UINT32_C(0xF) << 18)

Definition at line 453 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_12

#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_12   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 4)

Definition at line 458 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_16

#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 5)

Definition at line 459 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_24

#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_24   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 6)

Definition at line 460 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_3

#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_3   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 0)

Definition at line 454 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_32

#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_32   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 7)

Definition at line 461 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_4

#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_4   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 1)

Definition at line 455 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_48

#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_48   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 8)

Definition at line 462 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_6

#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_6   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 2)

Definition at line 456 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_8

#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_8   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLMUL, 3)

Definition at line 457 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_HSE

#define MCCI_STM32L0_REG_RCC_CFGR_PLLMUL_HSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLSRC, 1)

Definition at line 467 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PLLSRC

#define MCCI_STM32L0_REG_RCC_CFGR_PLLSRC   (UINT32_C(1) << 16)

Definition at line 465 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PLLSRC_HSI16

#define MCCI_STM32L0_REG_RCC_CFGR_PLLSRC_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PLLSRC, 0)

Definition at line 466 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PPRE1

#define MCCI_STM32L0_REG_RCC_CFGR_PPRE1   (UINT32_C(7) << 8)

Definition at line 480 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PPRE1_1

#define MCCI_STM32L0_REG_RCC_CFGR_PPRE1_1   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE1, 0)

Definition at line 481 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PPRE1_16

#define MCCI_STM32L0_REG_RCC_CFGR_PPRE1_16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE1, 7)

Definition at line 485 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PPRE1_2

#define MCCI_STM32L0_REG_RCC_CFGR_PPRE1_2   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE1, 4)

Definition at line 482 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PPRE1_4

#define MCCI_STM32L0_REG_RCC_CFGR_PPRE1_4   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE1, 5)

Definition at line 483 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PPRE1_8

#define MCCI_STM32L0_REG_RCC_CFGR_PPRE1_8   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE1, 6)

Definition at line 484 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PPRE2

#define MCCI_STM32L0_REG_RCC_CFGR_PPRE2   (UINT32_C(7) << 11)

Definition at line 474 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PPRE2_1

#define MCCI_STM32L0_REG_RCC_CFGR_PPRE2_1   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE2, 0)

Definition at line 475 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PPRE2_16

#define MCCI_STM32L0_REG_RCC_CFGR_PPRE2_16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE2, 7)

Definition at line 479 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PPRE2_2

#define MCCI_STM32L0_REG_RCC_CFGR_PPRE2_2   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE2, 4)

Definition at line 476 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PPRE2_4

#define MCCI_STM32L0_REG_RCC_CFGR_PPRE2_4   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE2, 5)

Definition at line 477 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_PPRE2_8

#define MCCI_STM32L0_REG_RCC_CFGR_PPRE2_8   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_PPRE2, 6)

Definition at line 478 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_RSV14

#define MCCI_STM32L0_REG_RCC_CFGR_RSV14   (UINT32_C(1) << 14)

Definition at line 473 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_RSV17

#define MCCI_STM32L0_REG_RCC_CFGR_RSV17   (UINT32_C(1) << 17)

Definition at line 463 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_RSV31

#define MCCI_STM32L0_REG_RCC_CFGR_RSV31   (UINT32_C(1) << 31)

Definition at line 429 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_STOPWUCK

#define MCCI_STM32L0_REG_RCC_CFGR_STOPWUCK   (UINT32_C(1) << 15)

Definition at line 469 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_STOPWUCK_HSI16

#define MCCI_STM32L0_REG_RCC_CFGR_STOPWUCK_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_STOPWUCK, 1)

Definition at line 471 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_STOPWUCK_MSI

#define MCCI_STM32L0_REG_RCC_CFGR_STOPWUCK_MSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_STOPWUCK, 0)

Definition at line 470 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_SW

#define MCCI_STM32L0_REG_RCC_CFGR_SW   (UINT32_C(3) << 0)

Definition at line 501 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_SW_HSE

#define MCCI_STM32L0_REG_RCC_CFGR_SW_HSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SW, 2)

Definition at line 504 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_SW_HSI16

#define MCCI_STM32L0_REG_RCC_CFGR_SW_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SW, 1)

Definition at line 503 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_SW_MSI

#define MCCI_STM32L0_REG_RCC_CFGR_SW_MSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SW, 0)

Definition at line 502 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_SW_PLL

#define MCCI_STM32L0_REG_RCC_CFGR_SW_PLL   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SW, 3)

Definition at line 505 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_SWS

#define MCCI_STM32L0_REG_RCC_CFGR_SWS   (UINT32_C(3) << 2)

Definition at line 496 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_SWS_HSE

#define MCCI_STM32L0_REG_RCC_CFGR_SWS_HSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SWS, 2)

Definition at line 499 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_SWS_HSI16

#define MCCI_STM32L0_REG_RCC_CFGR_SWS_HSI16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SWS, 1)

Definition at line 498 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_SWS_MSI

#define MCCI_STM32L0_REG_RCC_CFGR_SWS_MSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SWS, 0)

Definition at line 497 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CFGR_SWS_PLL

#define MCCI_STM32L0_REG_RCC_CFGR_SWS_PLL   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CFGR_SWS, 3)

Definition at line 500 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CICR

#define MCCI_STM32L0_REG_RCC_CICR   (MCCI_STM32L0_REG_RCC + 0x18)

Clock interrupt clear.

Definition at line 355 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CICR_CSSHSEC

#define MCCI_STM32L0_REG_RCC_CICR_CSSHSEC   (UINT32_C(1) << 8)

Definition at line 538 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CICR_CSSLSEC

#define MCCI_STM32L0_REG_RCC_CICR_CSSLSEC   (UINT32_C(1) << 7)

Definition at line 539 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CICR_HSERDYC

#define MCCI_STM32L0_REG_RCC_CICR_HSERDYC   (UINT32_C(1) << 3)

Definition at line 543 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CICR_HSI16RDYC

#define MCCI_STM32L0_REG_RCC_CICR_HSI16RDYC   (UINT32_C(1) << 2)

Definition at line 544 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CICR_HSI48RDYC

#define MCCI_STM32L0_REG_RCC_CICR_HSI48RDYC   (UINT32_C(1) << 6)

Definition at line 540 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CICR_LSERDYC

#define MCCI_STM32L0_REG_RCC_CICR_LSERDYC   (UINT32_C(1) << 1)

Definition at line 545 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CICR_LSIRDYC

#define MCCI_STM32L0_REG_RCC_CICR_LSIRDYC   (UINT32_C(1) << 0)

Definition at line 546 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CICR_MSIRDYC

#define MCCI_STM32L0_REG_RCC_CICR_MSIRDYC   (UINT32_C(1) << 5)

Definition at line 541 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CICR_PLLRDYC

#define MCCI_STM32L0_REG_RCC_CICR_PLLRDYC   (UINT32_C(1) << 4)

Definition at line 542 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CICR_RSV9

#define MCCI_STM32L0_REG_RCC_CICR_RSV9   UINT32_C(0xFFFFFE00)

Definition at line 537 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIER

#define MCCI_STM32L0_REG_RCC_CIER   (MCCI_STM32L0_REG_RCC + 0x10)

Clock interrupt enable.

Definition at line 353 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIER_CSSLSE

#define MCCI_STM32L0_REG_RCC_CIER_CSSLSE   (UINT32_C(1) << 7)

Definition at line 511 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIER_HSERDYIE

#define MCCI_STM32L0_REG_RCC_CIER_HSERDYIE   (UINT32_C(1) << 3)

Definition at line 515 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIER_HSI16RDYIE

#define MCCI_STM32L0_REG_RCC_CIER_HSI16RDYIE   (UINT32_C(1) << 2)

Definition at line 516 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIER_HSI48RDYIE

#define MCCI_STM32L0_REG_RCC_CIER_HSI48RDYIE   (UINT32_C(1) << 6)

Definition at line 512 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIER_LSERDYIE

#define MCCI_STM32L0_REG_RCC_CIER_LSERDYIE   (UINT32_C(1) << 1)

Definition at line 517 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIER_LSIRDYIE

#define MCCI_STM32L0_REG_RCC_CIER_LSIRDYIE   (UINT32_C(1) << 0)

Definition at line 518 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIER_MSIRDYIE

#define MCCI_STM32L0_REG_RCC_CIER_MSIRDYIE   (UINT32_C(1) << 5)

Definition at line 513 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIER_PLLRDYIE

#define MCCI_STM32L0_REG_RCC_CIER_PLLRDYIE   (UINT32_C(1) << 4)

Definition at line 514 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIER_RSV8

#define MCCI_STM32L0_REG_RCC_CIER_RSV8   UINT32_C(0xFFFFFF00)

Definition at line 510 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIFR

#define MCCI_STM32L0_REG_RCC_CIFR   (MCCI_STM32L0_REG_RCC + 0x14)

Clock interrupt flag.

Definition at line 354 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIFR_CSSHSEF

#define MCCI_STM32L0_REG_RCC_CIFR_CSSHSEF   (UINT32_C(1) << 8)

Definition at line 524 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIFR_CSSLSEF

#define MCCI_STM32L0_REG_RCC_CIFR_CSSLSEF   (UINT32_C(1) << 7)

Definition at line 525 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIFR_HSERDYF

#define MCCI_STM32L0_REG_RCC_CIFR_HSERDYF   (UINT32_C(1) << 3)

Definition at line 529 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIFR_HSI16RDYF

#define MCCI_STM32L0_REG_RCC_CIFR_HSI16RDYF   (UINT32_C(1) << 2)

Definition at line 530 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIFR_HSI48RDYF

#define MCCI_STM32L0_REG_RCC_CIFR_HSI48RDYF   (UINT32_C(1) << 6)

Definition at line 526 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIFR_LSERDYF

#define MCCI_STM32L0_REG_RCC_CIFR_LSERDYF   (UINT32_C(1) << 1)

Definition at line 531 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIFR_LSIRDYF

#define MCCI_STM32L0_REG_RCC_CIFR_LSIRDYF   (UINT32_C(1) << 0)

Definition at line 532 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIFR_MSIRDYF

#define MCCI_STM32L0_REG_RCC_CIFR_MSIRDYF   (UINT32_C(1) << 5)

Definition at line 527 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIFR_PLLRDYF

#define MCCI_STM32L0_REG_RCC_CIFR_PLLRDYF   (UINT32_C(1) << 4)

Definition at line 528 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CIFR_RSV9

#define MCCI_STM32L0_REG_RCC_CIFR_RSV9   UINT32_C(0xFFFFFE00)

Definition at line 523 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR

#define MCCI_STM32L0_REG_RCC_CR   (MCCI_STM32L0_REG_RCC + 0x00)

Clock control.

Definition at line 349 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_CSSHSEON

#define MCCI_STM32L0_REG_RCC_CR_CSSHSEON   (UINT32_C(1) << 19)

Definition at line 383 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_HSEBYP

#define MCCI_STM32L0_REG_RCC_CR_HSEBYP   (UINT32_C(1) << 18)

Definition at line 384 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_HSEON

#define MCCI_STM32L0_REG_RCC_CR_HSEON   (UINT32_C(1) << 16)

Definition at line 386 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_HSERDY

#define MCCI_STM32L0_REG_RCC_CR_HSERDY   (UINT32_C(1) << 17)

Definition at line 385 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_HSI16DIVEN

#define MCCI_STM32L0_REG_RCC_CR_HSI16DIVEN   (UINT32_C(1) << 3)

Definition at line 393 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_HSI16DIVF

#define MCCI_STM32L0_REG_RCC_CR_HSI16DIVF   (UINT32_C(1) << 4)

Definition at line 392 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_HSI16KERON

#define MCCI_STM32L0_REG_RCC_CR_HSI16KERON   (UINT32_C(1) << 1)

Definition at line 395 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_HSI16ON

#define MCCI_STM32L0_REG_RCC_CR_HSI16ON   (UINT32_C(1) << 0)

Definition at line 396 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_HSI16OUTEN

#define MCCI_STM32L0_REG_RCC_CR_HSI16OUTEN   (UINT32_C(1) << 5)

Definition at line 391 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_HSI16RDYF

#define MCCI_STM32L0_REG_RCC_CR_HSI16RDYF   (UINT32_C(1) << 2)

Definition at line 394 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_MSION

#define MCCI_STM32L0_REG_RCC_CR_MSION   (UINT32_C(1) << 8)

Definition at line 389 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_MSIRDY

#define MCCI_STM32L0_REG_RCC_CR_MSIRDY   (UINT32_C(1) << 9)

Definition at line 388 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_PLLON

#define MCCI_STM32L0_REG_RCC_CR_PLLON   (UINT32_C(1) << 24)

Definition at line 376 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_PLLRDY

#define MCCI_STM32L0_REG_RCC_CR_PLLRDY   (UINT32_C(1) << 25)

Definition at line 375 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_RSV10

#define MCCI_STM32L0_REG_RCC_CR_RSV10   UINT32_C(0x0000FC00)

Definition at line 387 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_RSV22

#define MCCI_STM32L0_REG_RCC_CR_RSV22   (UINT32_C(3) << 22)

Definition at line 377 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_RSV26

#define MCCI_STM32L0_REG_RCC_CR_RSV26   UINT32_C(0xFC000000)

Definition at line 374 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_RSV6

#define MCCI_STM32L0_REG_RCC_CR_RSV6   (UINT32_C(3) << 6)

Definition at line 390 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_RTCPRE

#define MCCI_STM32L0_REG_RCC_CR_RTCPRE   (UINT32_C(3) << 20)

Definition at line 378 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_RTCPRE_16

#define MCCI_STM32L0_REG_RCC_CR_RTCPRE_16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLSMCCI_STM32L0_REG_RCC_CR_RTCPRE, 3)

Definition at line 382 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_RTCPRE_2

#define MCCI_STM32L0_REG_RCC_CR_RTCPRE_2   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLSMCCI_STM32L0_REG_RCC_CR_RTCPRE, 0)

Definition at line 379 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_RTCPRE_4

#define MCCI_STM32L0_REG_RCC_CR_RTCPRE_4   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLSMCCI_STM32L0_REG_RCC_CR_RTCPRE, 1)

Definition at line 380 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CR_RTCPRE_8

#define MCCI_STM32L0_REG_RCC_CR_RTCPRE_8   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_PWR_CR_PLSMCCI_STM32L0_REG_RCC_CR_RTCPRE, 2)

Definition at line 381 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CRRCR

#define MCCI_STM32L0_REG_RCC_CRRCR   (MCCI_STM32L0_REG_RCC + 0x08)

Clock recovery RC.

Definition at line 351 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CRRCR_HSI48CAL

#define MCCI_STM32L0_REG_RCC_CRRCR_HSI48CAL   (UINT32_C(0xFF) << 8)

Definition at line 420 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CRRCR_HSI48DIVEN

#define MCCI_STM32L0_REG_RCC_CRRCR_HSI48DIVEN   (UINT32_C(1) << 2)

Definition at line 422 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CRRCR_HSI48ON

#define MCCI_STM32L0_REG_RCC_CRRCR_HSI48ON   (UINT32_C(1) << 0)

Definition at line 424 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CRRCR_HSI48RDY

#define MCCI_STM32L0_REG_RCC_CRRCR_HSI48RDY   (UINT32_C(1) << 1)

Definition at line 423 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CRRCR_RSV16

#define MCCI_STM32L0_REG_RCC_CRRCR_RSV16   UINT32_C(0xFFFF0000)

Definition at line 419 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CRRCR_RSV3

#define MCCI_STM32L0_REG_RCC_CRRCR_RSV3   UINT32_C(0xF8)

Definition at line 421 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR

#define MCCI_STM32L0_REG_RCC_CSR   (MCCI_STM32L0_REG_RCC + 0x50)

Control/status.

Definition at line 369 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_CSSLSED

#define MCCI_STM32L0_REG_RCC_CSR_CSSLSED   (UINT32_C(1) << 14)

Definition at line 835 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_CSSLSEON

#define MCCI_STM32L0_REG_RCC_CSR_CSSLSEON   (UINT32_C(1) << 13)

Definition at line 836 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_FWRSTF

#define MCCI_STM32L0_REG_RCC_CSR_FWRSTF   (UINT32_C(1) << 24)

Definition at line 822 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_IWDGRSTF

#define MCCI_STM32L0_REG_RCC_CSR_IWDGRSTF   (UINT32_C(1) << 29)

Definition at line 817 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_LPWRRSTF

#define MCCI_STM32L0_REG_RCC_CSR_LPWRRSTF   (UINT32_C(1) << 31)

Definition at line 815 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_LSEBYP

#define MCCI_STM32L0_REG_RCC_CSR_LSEBYP   (UINT32_C(1) << 10)

Definition at line 844 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_LSEDRV

#define MCCI_STM32L0_REG_RCC_CSR_LSEDRV   (UINT32_C(3) << 11)

Definition at line 838 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_LSEDRV_HIGH

#define MCCI_STM32L0_REG_RCC_CSR_LSEDRV_HIGH   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_LSEDRV, 3)

Definition at line 842 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_LSEDRV_LOW

#define MCCI_STM32L0_REG_RCC_CSR_LSEDRV_LOW   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_LSEDRV, 0)

Definition at line 839 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_LSEDRV_M1

#define MCCI_STM32L0_REG_RCC_CSR_LSEDRV_M1   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_LSEDRV, 1)

Definition at line 840 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_LSEDRV_M2

#define MCCI_STM32L0_REG_RCC_CSR_LSEDRV_M2   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_LSEDRV, 2)

Definition at line 841 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_LSEON

#define MCCI_STM32L0_REG_RCC_CSR_LSEON   (UINT32_C(1) << 8)

Definition at line 846 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_LSERDY

#define MCCI_STM32L0_REG_RCC_CSR_LSERDY   (UINT32_C(1) << 9)

Definition at line 845 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_LSION

#define MCCI_STM32L0_REG_RCC_CSR_LSION   (UINT32_C(1) << 0)

Definition at line 849 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_LSIRDY

#define MCCI_STM32L0_REG_RCC_CSR_LSIRDY   (UINT32_C(1) << 1)

Definition at line 848 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_OBLRSTF

#define MCCI_STM32L0_REG_RCC_CSR_OBLRSTF   (UINT32_C(1) << 25)

Definition at line 821 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_PINRSTF

#define MCCI_STM32L0_REG_RCC_CSR_PINRSTF   (UINT32_C(1) << 26)

Definition at line 820 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_PORRSTF

#define MCCI_STM32L0_REG_RCC_CSR_PORRSTF   (UINT32_C(1) << 27)

Definition at line 819 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_RMVF

#define MCCI_STM32L0_REG_RCC_CSR_RMVF   (UINT32_C(1) << 23)

Definition at line 823 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_RSV15

#define MCCI_STM32L0_REG_RCC_CSR_RSV15   (UINT32_C(1) << 15)

Definition at line 834 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_RSV2

#define MCCI_STM32L0_REG_RCC_CSR_RSV2   (UINT32_C(0x3F) << 2)

Definition at line 847 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_RSV20

#define MCCI_STM32L0_REG_RCC_CSR_RSV20   (UINT32_C(7) << 20)

Definition at line 824 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_RTCEN

#define MCCI_STM32L0_REG_RCC_CSR_RTCEN   (UINT32_C(1) << 18)

Definition at line 826 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_RTCRST

#define MCCI_STM32L0_REG_RCC_CSR_RTCRST   (UINT32_C(1) << 19)

Definition at line 825 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_RTCSEL

#define MCCI_STM32L0_REG_RCC_CSR_RTCSEL   (UINT32_C(3) << 16)

Definition at line 828 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_RTCSEL_HSE

#define MCCI_STM32L0_REG_RCC_CSR_RTCSEL_HSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_RTCSEL, 0)

Definition at line 832 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_RTCSEL_LSE

#define MCCI_STM32L0_REG_RCC_CSR_RTCSEL_LSE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_RTCSEL, 0)

Definition at line 830 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_RTCSEL_LSI

#define MCCI_STM32L0_REG_RCC_CSR_RTCSEL_LSI   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_RTCSEL, 0)

Definition at line 831 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_RTCSEL_NONE

#define MCCI_STM32L0_REG_RCC_CSR_RTCSEL_NONE   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_CSR_RTCSEL, 0)

Definition at line 829 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_SFTRSTF

#define MCCI_STM32L0_REG_RCC_CSR_SFTRSTF   (UINT32_C(1) << 28)

Definition at line 818 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_CSR_WWDGRSTF

#define MCCI_STM32L0_REG_RCC_CSR_WWDGRSTF   (UINT32_C(1) << 30)

Definition at line 816 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_ICSCR

#define MCCI_STM32L0_REG_RCC_ICSCR   (MCCI_STM32L0_REG_RCC + 0x04)

Internal clock sources calibration.

Definition at line 350 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_ICSCR_HSI16CAL

#define MCCI_STM32L0_REG_RCC_ICSCR_HSI16CAL   (UINT32_C(0xFF) << 0)

Definition at line 414 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_ICSCR_HSI16TRIM

#define MCCI_STM32L0_REG_RCC_ICSCR_HSI16TRIM   (UINT32_C(0x1F) << 8)

Definition at line 413 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_ICSCR_MSICAL

#define MCCI_STM32L0_REG_RCC_ICSCR_MSICAL   (UINT32_C(0xFF) << 16)

Definition at line 402 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE

#define MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE   (UINT32_C(7) << 13)

Definition at line 404 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_1048k

#define MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_1048k   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 4)

Definition at line 409 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_131k

#define MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_131k   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 1)

Definition at line 406 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_2097k

#define MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_2097k   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 5)

Definition at line 410 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_262k

#define MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_262k   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 2)

Definition at line 407 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_4194k

#define MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_4194k   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 6)

Definition at line 411 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_524k

#define MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_524k   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 3)

Definition at line 408 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_65k

#define MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE_65k   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_REG_RCC_ICSCR_MSIRANGE, 0)

Definition at line 405 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_ICSCR_MSITRIM

#define MCCI_STM32L0_REG_RCC_ICSCR_MSITRIM   (UINT32_C(0xFF) << 24)

Definition at line 401 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPENR

#define MCCI_STM32L0_REG_RCC_IOPENR   (MCCI_STM32L0_REG_RCC + 0x2C)

GPIO clock enable.

Definition at line 360 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPENR_IOPAEN

#define MCCI_STM32L0_REG_RCC_IOPENR_IOPAEN   (UINT32_C(1) << 0)

Definition at line 631 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPENR_IOPBEN

#define MCCI_STM32L0_REG_RCC_IOPENR_IOPBEN   (UINT32_C(1) << 1)

Definition at line 630 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPENR_IOPCEN

#define MCCI_STM32L0_REG_RCC_IOPENR_IOPCEN   (UINT32_C(1) << 2)

Definition at line 629 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPENR_IOPDEN

#define MCCI_STM32L0_REG_RCC_IOPENR_IOPDEN   (UINT32_C(1) << 3)

Definition at line 628 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPENR_IOPEEN

#define MCCI_STM32L0_REG_RCC_IOPENR_IOPEEN   (UINT32_C(1) << 4)

Definition at line 627 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPENR_IOPHEN

#define MCCI_STM32L0_REG_RCC_IOPENR_IOPHEN   (UINT32_C(1) << 7)

Definition at line 625 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPENR_RSV5

#define MCCI_STM32L0_REG_RCC_IOPENR_RSV5   (UINT32_C(3) << 5)

Definition at line 626 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPENR_RSV8

#define MCCI_STM32L0_REG_RCC_IOPENR_RSV8   UINT32_C(0xFFFFFF00)

Definition at line 624 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPRSTR

#define MCCI_STM32L0_REG_RCC_IOPRSTR   (MCCI_STM32L0_REG_RCC + 0x1C)

GPIO reset.

Definition at line 356 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPRSTR_IOPARST

#define MCCI_STM32L0_REG_RCC_IOPRSTR_IOPARST   (UINT32_C(1) << 0)

Definition at line 558 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPRSTR_IOPBRST

#define MCCI_STM32L0_REG_RCC_IOPRSTR_IOPBRST   (UINT32_C(1) << 1)

Definition at line 557 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPRSTR_IOPCRST

#define MCCI_STM32L0_REG_RCC_IOPRSTR_IOPCRST   (UINT32_C(1) << 2)

Definition at line 556 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPRSTR_IOPDRST

#define MCCI_STM32L0_REG_RCC_IOPRSTR_IOPDRST   (UINT32_C(1) << 3)

Definition at line 555 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPRSTR_IOPERST

#define MCCI_STM32L0_REG_RCC_IOPRSTR_IOPERST   (UINT32_C(1) << 4)

Definition at line 554 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPRSTR_IOPHRST

#define MCCI_STM32L0_REG_RCC_IOPRSTR_IOPHRST   (UINT32_C(1) << 7)

Definition at line 552 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPRSTR_RSV5

#define MCCI_STM32L0_REG_RCC_IOPRSTR_RSV5   (UINT32_C(3) << 5)

Definition at line 553 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPRSTR_RSV8

#define MCCI_STM32L0_REG_RCC_IOPRSTR_RSV8   UINT32_C(0xFFFFFF00)

Definition at line 551 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPSMEN

#define MCCI_STM32L0_REG_RCC_IOPSMEN   (MCCI_STM32L0_REG_RCC + 0x3C)

GPIO clock enable in sleep.

Definition at line 364 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPSMENR_IOPASMEN

#define MCCI_STM32L0_REG_RCC_IOPSMENR_IOPASMEN   (UINT32_C(1) << 0)

Definition at line 704 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPSMENR_IOPBSMEN

#define MCCI_STM32L0_REG_RCC_IOPSMENR_IOPBSMEN   (UINT32_C(1) << 1)

Definition at line 703 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPSMENR_IOPCSMEN

#define MCCI_STM32L0_REG_RCC_IOPSMENR_IOPCSMEN   (UINT32_C(1) << 2)

Definition at line 702 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPSMENR_IOPDSMEN

#define MCCI_STM32L0_REG_RCC_IOPSMENR_IOPDSMEN   (UINT32_C(1) << 3)

Definition at line 701 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPSMENR_IOPESMEN

#define MCCI_STM32L0_REG_RCC_IOPSMENR_IOPESMEN   (UINT32_C(1) << 4)

Definition at line 700 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPSMENR_IOPHSMEN

#define MCCI_STM32L0_REG_RCC_IOPSMENR_IOPHSMEN   (UINT32_C(1) << 7)

Definition at line 698 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPSMENR_RSV5

#define MCCI_STM32L0_REG_RCC_IOPSMENR_RSV5   (UINT32_C(3) << 5)

Definition at line 699 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RCC_IOPSMENR_RSV8

#define MCCI_STM32L0_REG_RCC_IOPSMENR_RSV8   UINT32_C(0xFFFFFF00)

Definition at line 697 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RNG

#define MCCI_STM32L0_REG_RNG   UINT32_C(0x40025000)

Section 19.8.4: RNG register map (1K)

Definition at line 90 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_RTC

#define MCCI_STM32L0_REG_RTC   UINT32_C(0x40002800)

Section 26.7.21: RTC + BKUP register map (1K)

Definition at line 59 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_SPI1

#define MCCI_STM32L0_REG_SPI1   UINT32_C(0x40013000)

Section 30.7.10: SPI register map (1K)

Definition at line 82 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_SPI2

#define MCCI_STM32L0_REG_SPI2   UINT32_C(0x40003800)

Section 30.7.10: SPI register map (1K)

Definition at line 62 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_SYSCFG_COMP

#define MCCI_STM32L0_REG_SYSCFG_COMP   UINT32_C(0x40010000)

Section 10.2.8: SYSCFG register map, Section 16.5.3: COMP register map (1K)

Definition at line 76 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_TIM21

#define MCCI_STM32L0_REG_TIM21   UINT32_C(0x40010800)

Section 21.4.16: TIM21/22 register map (1K)

Definition at line 78 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_TIM22

#define MCCI_STM32L0_REG_TIM22   UINT32_C(0x40011400)

Section 21.4.16: TIM21/22 register map (1K)

Definition at line 79 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_TIMER2

#define MCCI_STM32L0_REG_TIMER2   UINT32_C(0x40000000)

Section 20.5: TIMx register map (1K)

Definition at line 55 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_TIMER3

#define MCCI_STM32L0_REG_TIMER3   UINT32_C(0x40000400)

Section 20.5: TIMx register map (1K)

Definition at line 56 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_TIMER6

#define MCCI_STM32L0_REG_TIMER6   UINT32_C(0x40001000)

Section 22.4.9: TIM6/7 register map (1K)

Definition at line 57 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_TIMER7

#define MCCI_STM32L0_REG_TIMER7   UINT32_C(0x40001400)

Section 22.4.9: TIM6/7 register map (1K)

Definition at line 58 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_TSC

#define MCCI_STM32L0_REG_TSC   UINT32_C(0x40024000)

Section 17.6.11: TSC register map (1K)

Definition at line 89 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_USART1

#define MCCI_STM32L0_REG_USART1   UINT32_C(0x40013800)

Section 28.8.12: USART register map (1K)

Definition at line 83 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_USART2

#define MCCI_STM32L0_REG_USART2   UINT32_C(0x40004400)

Section 28.8.12: USART register map (1K)

Definition at line 63 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_USART4

#define MCCI_STM32L0_REG_USART4   UINT32_C(0x40004C00)

Section 28.8.12: USART register map (1K)

Definition at line 65 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_USART5

#define MCCI_STM32L0_REG_USART5   UINT32_C(0x40005000)

Section 28.8.12: USART register map (1K)

Definition at line 66 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_USB_FS

#define MCCI_STM32L0_REG_USB_FS   UINT32_C(0x40005C00)

Section 31.6.3: USB register map (1K)

Definition at line 69 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_USB_SRAM

#define MCCI_STM32L0_REG_USB_SRAM   UINT32_C(0x40006000)

USB (SRAM 512x16bit) (2K)

Definition at line 70 of file mcci_stm32l0xx.h.

MCCI_STM32L0_REG_WWDG

#define MCCI_STM32L0_REG_WWDG   UINT32_C(0x40002C00)

Section 25.4.4: WWDG register map (1K)

Definition at line 60 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1

#define MCCI_STM32L0_SPI_CR1   UINT32_C(0x00)

offset to SPI control register 1

Definition at line 1003 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_BIDIMODE

#define MCCI_STM32L0_SPI_CR1_BIDIMODE   (UINT32_C(1) << 15)

Bidirectional mode.

Definition at line 1017 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_BIDIOE

#define MCCI_STM32L0_SPI_CR1_BIDIOE   (UINT32_C(1) << 14)

Bidirectional output enable.

Definition at line 1018 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_BR

#define MCCI_STM32L0_SPI_CR1_BR   (UINT32_C(7) << 3)

baud rate control (PCLK divisor)

Definition at line 1028 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_BR_128

#define MCCI_STM32L0_SPI_CR1_BR_128   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 6)

PCLK/128.

Definition at line 1035 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_BR_16

#define MCCI_STM32L0_SPI_CR1_BR_16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 3)

PCLK/16.

Definition at line 1032 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_BR_2

#define MCCI_STM32L0_SPI_CR1_BR_2   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 0)

PCLK/2.

Definition at line 1029 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_BR_256

#define MCCI_STM32L0_SPI_CR1_BR_256   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 7)

PCLK/256.

Definition at line 1036 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_BR_32

#define MCCI_STM32L0_SPI_CR1_BR_32   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 4)

PCLK/32.

Definition at line 1033 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_BR_4

#define MCCI_STM32L0_SPI_CR1_BR_4   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 1)

PCLK/4.

Definition at line 1030 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_BR_64

#define MCCI_STM32L0_SPI_CR1_BR_64   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 5)

PCLK/64.

Definition at line 1034 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_BR_8

#define MCCI_STM32L0_SPI_CR1_BR_8   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_CR1_BR, 2)

PCLK/8.

Definition at line 1031 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_CPHA

#define MCCI_STM32L0_SPI_CR1_CPHA   (UINT32_C(1) << 0)

Clock phase: second clock transaction captures (not first)

Definition at line 1040 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_CPOL

#define MCCI_STM32L0_SPI_CR1_CPOL   (UINT32_C(1) << 1)

Clk to 1 when idle (not zero)

Definition at line 1039 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_CRCEN

#define MCCI_STM32L0_SPI_CR1_CRCEN   (UINT32_C(1) << 13)

CRC enabled.

Definition at line 1019 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_CRCNEXT

#define MCCI_STM32L0_SPI_CR1_CRCNEXT   (UINT32_C(1) << 12)

CRC is next.

Definition at line 1020 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_DFF

#define MCCI_STM32L0_SPI_CR1_DFF   (UINT32_C(1) << 11)

Data frame format (16 bit / not 8 bit)

Definition at line 1021 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_LSBFIRST

#define MCCI_STM32L0_SPI_CR1_LSBFIRST   (UINT32_C(1) << 7)

LSB first (not MSB)

Definition at line 1025 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_MSTR

#define MCCI_STM32L0_SPI_CR1_MSTR   (UINT32_C(1) << 2)

Master (not slave)

Definition at line 1038 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_RSV16

#define MCCI_STM32L0_SPI_CR1_RSV16   UINT32_C(0xFFFF0000)

reserved

Definition at line 1016 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_RXONLY

#define MCCI_STM32L0_SPI_CR1_RXONLY   (UINT32_C(1) << 10)

Receive-only mode.

Definition at line 1022 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_SPE

#define MCCI_STM32L0_SPI_CR1_SPE   (UINT32_C(1) << 6)

SPI enabled.

Definition at line 1026 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_SSI

#define MCCI_STM32L0_SPI_CR1_SSI   (UINT32_C(1) << 8)

internal slave select

Definition at line 1024 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR1_SSM

#define MCCI_STM32L0_SPI_CR1_SSM   (UINT32_C(1) << 9)

software slave management

Definition at line 1023 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR2

#define MCCI_STM32L0_SPI_CR2   UINT32_C(0x04)

offset to SPI control register 2

Definition at line 1004 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR2_ERRIE

#define MCCI_STM32L0_SPI_CR2_ERRIE   (UINT32_C(1) << 5)

error interrupt enable

Definition at line 1048 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR2_FRF

#define MCCI_STM32L0_SPI_CR2_FRF   (UINT32_C(1) << 4)

frame format TI (not Motorola)

Definition at line 1049 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR2_RSV3

#define MCCI_STM32L0_SPI_CR2_RSV3   (UINT32_C(1) << 3)

reserved, zero

Definition at line 1050 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR2_RSV8

#define MCCI_STM32L0_SPI_CR2_RSV8   UINT32_C(0xFFFFFF00)

reserved

Definition at line 1045 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR2_RXDMAEN

#define MCCI_STM32L0_SPI_CR2_RXDMAEN   (UINT32_C(1) << 0)

rx DMA enable

Definition at line 1053 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR2_RXNEIE

#define MCCI_STM32L0_SPI_CR2_RXNEIE   (UINT32_C(1) << 6)

rx not empty interrupt enable

Definition at line 1047 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR2_SSOE

#define MCCI_STM32L0_SPI_CR2_SSOE   (UINT32_C(1) << 2)

enable SS in master mode

Definition at line 1051 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR2_TXDMAEN

#define MCCI_STM32L0_SPI_CR2_TXDMAEN   (UINT32_C(1) << 1)

tx DMA enable

Definition at line 1052 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CR2_TXEIE

#define MCCI_STM32L0_SPI_CR2_TXEIE   (UINT32_C(1) << 7)

tx empty interrupt enable

Definition at line 1046 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_CRCPR

#define MCCI_STM32L0_SPI_CRCPR   UINT32_C(0x10)

offset to SPI CRC polynomial

Definition at line 1007 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_DR

#define MCCI_STM32L0_SPI_DR   UINT32_C(0x0C)

offset to SPI data register

Definition at line 1006 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR

#define MCCI_STM32L0_SPI_I2SCFGR   UINT32_C(0x1C)

offset to SPI I2S config register

Definition at line 1010 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_CHLEN

#define MCCI_STM32L0_SPI_I2SCFGR_CHLEN   (UINT32_C(1) << 0)

channel 32-bits wide (not 16)

Definition at line 1093 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_CKPOL

#define MCCI_STM32L0_SPI_I2SCFGR_CKPOL   (UINT32_C(1) << 3)

steady state clock polarity high (not low)

Definition at line 1087 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_DATLEN

#define MCCI_STM32L0_SPI_I2SCFGR_DATLEN   (UINT32_C(3) << 1)

data length

Definition at line 1088 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_DATLEN_16

#define MCCI_STM32L0_SPI_I2SCFGR_DATLEN_16   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_DATLEN, 0)

16-bit data

Definition at line 1089 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_DATLEN_24

#define MCCI_STM32L0_SPI_I2SCFGR_DATLEN_24   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_DATLEN, 1)

24-bit data

Definition at line 1090 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_DATLEN_32

#define MCCI_STM32L0_SPI_I2SCFGR_DATLEN_32   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_DATLEN, 2)

32-bit data

Definition at line 1091 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_DATLEN_XX

#define MCCI_STM32L0_SPI_I2SCFGR_DATLEN_XX   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_DATLEN, 3)

invalid data length

Definition at line 1092 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_I2SCFG

#define MCCI_STM32L0_SPI_I2SCFGR_I2SCFG   (UINT32_C(3) << 8)

I2S configuration mode.

Definition at line 1075 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_I2SCFG_MRX

#define MCCI_STM32L0_SPI_I2SCFGR_I2SCFG_MRX   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SCFG, 3)

I2S master receive.

Definition at line 1079 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_I2SCFG_MTX

#define MCCI_STM32L0_SPI_I2SCFGR_I2SCFG_MTX   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SCFG, 2)

I2S master transmit.

Definition at line 1078 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_I2SCFG_SRX

#define MCCI_STM32L0_SPI_I2SCFGR_I2SCFG_SRX   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SCFG, 1)

I2S slave receive.

Definition at line 1077 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_I2SCFG_STX

#define MCCI_STM32L0_SPI_I2SCFGR_I2SCFG_STX   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SCFG, 0)

I2S slave transmit.

Definition at line 1076 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_I2SE

#define MCCI_STM32L0_SPI_I2SCFGR_I2SE   (UINT32_C(1) << 10)

I2S enable.

Definition at line 1074 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_I2SMOD

#define MCCI_STM32L0_SPI_I2SCFGR_I2SMOD   (UINT32_C(1) << 11)

I2S mode (not SPI)

Definition at line 1073 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_I2SSTD

#define MCCI_STM32L0_SPI_I2SCFGR_I2SSTD   (UINT32_C(3) << 4)

I2S standard selection.

Definition at line 1082 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_I2SSTD_LEFT

#define MCCI_STM32L0_SPI_I2SCFGR_I2SSTD_LEFT   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SSTD, 1)

MSB justified.

Definition at line 1084 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_I2SSTD_PCM

#define MCCI_STM32L0_SPI_I2SCFGR_I2SSTD_PCM   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SSTD, 3)

PCM standard.

Definition at line 1086 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_I2SSTD_PHILIPS

#define MCCI_STM32L0_SPI_I2SCFGR_I2SSTD_PHILIPS   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SSTD, 0)

Philips standard.

Definition at line 1083 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_I2SSTD_RIGHT

#define MCCI_STM32L0_SPI_I2SCFGR_I2SSTD_RIGHT   MCCI_BOOTLOADER_FIELD_SET_VALUE(MCCI_STM32L0_SPI_I2SCFGR_I2SSTD, 2)

LSB justified.

Definition at line 1085 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_PCMSYNC

#define MCCI_STM32L0_SPI_I2SCFGR_PCMSYNC   (UINT32_C(1) << 7)

Long (not short) PCM frame synchronization.

Definition at line 1080 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_RSV13

#define MCCI_STM32L0_SPI_I2SCFGR_RSV13   UINT32_C(0xFFFFE000)

reserved (do not change)

Definition at line 1072 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SCFGR_RSV6

#define MCCI_STM32L0_SPI_I2SCFGR_RSV6   (UINT32_C(1) << 6)

reserved, zero

Definition at line 1081 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_I2SPR

#define MCCI_STM32L0_SPI_I2SPR   UINT32_C(0x20)

offset to SPI I2S prescaler

Definition at line 1011 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_RXCRCR

#define MCCI_STM32L0_SPI_RXCRCR   UINT32_C(0x14)

offset to SPI receive CRC

Definition at line 1008 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_SR

#define MCCI_STM32L0_SPI_SR   UINT32_C(0x08)

offset to SPI status register

Definition at line 1005 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_SR_BSY

#define MCCI_STM32L0_SPI_SR_BSY   (UINT32_C(1) << 7)

busy

Definition at line 1060 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_SR_CHSIDE

#define MCCI_STM32L0_SPI_SR_CHSIDE   (UINT32_C(1) << 2)

channel right (not left)

Definition at line 1065 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_SR_CRCERR

#define MCCI_STM32L0_SPI_SR_CRCERR   (UINT32_C(1) << 4)

CRC error (write zero to clear)

Definition at line 1063 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_SR_FRE

#define MCCI_STM32L0_SPI_SR_FRE   (UINT32_C(1) << 8)

frame error (read to clear)

Definition at line 1059 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_SR_MODF

#define MCCI_STM32L0_SPI_SR_MODF   (UINT32_C(1) << 5)

mode fault

Definition at line 1062 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_SR_OVR

#define MCCI_STM32L0_SPI_SR_OVR   (UINT32_C(1) << 6)

overrun

Definition at line 1061 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_SR_RSV9

#define MCCI_STM32L0_SPI_SR_RSV9   UINT32_C(0xFFFFFE00)

reserved, zero

Definition at line 1058 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_SR_RXNE

#define MCCI_STM32L0_SPI_SR_RXNE   (UINT32_C(1) << 0)

RX buffer not-empty.

Definition at line 1067 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_SR_TXE

#define MCCI_STM32L0_SPI_SR_TXE   (UINT32_C(1) << 1)

TX buffer empty.

Definition at line 1066 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_SR_UDR

#define MCCI_STM32L0_SPI_SR_UDR   (UINT32_C(1) << 3)

underrun

Definition at line 1064 of file mcci_stm32l0xx.h.

MCCI_STM32L0_SPI_TXCRCR

#define MCCI_STM32L0_SPI_TXCRCR   UINT32_C(0x18)

offset to SPI transmit CRC

Definition at line 1009 of file mcci_stm32l0xx.h.