MCCI Trusted Bootloader
Simple trusted bootloader and tools for small embedded systems
mcci_stm32h7xx.h
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/*
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Module: mcci_stm32h7xx.h
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Function:
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Register definitions for STM32H7xx CPUs
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Copyright and License:
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This file copyright (C) 2021 by
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MCCI Corporation
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3520 Krums Corners Road
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Ithaca, NY 14850
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See accompanying LICENSE file for copyright and license information.
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Author:
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Terry Moore, MCCI Corporation March 2021
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*/
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#ifndef _mcci_stm32h7xx_h_
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#define _mcci_stm32h7xx_h_
/* prevent multiple includes */
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#pragma once
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#ifndef _mcci_bootloader_bits_h_
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# include "
mcci_bootloader_bits.h
"
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#endif
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#ifndef _mcci_arm_cm7_h_
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# include "
mcci_arm_cm7.h
"
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#endif
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#include <stdint.h>
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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/****************************************************************************\
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|
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| Register addresses
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|
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\****************************************************************************/
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/// \name STM32H7xx top-level address breakdown
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/// @{
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#define MCCI_STM32H7_MEMORY_FLASH UINT32_C(0x08000000)
///< Flash program memory (up to 2M)
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#define MCCI_STM32H7_MEMORY_FLASH1 UINT32_C(0x08000000)
///< Flash program memory (up to 1M)
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#define MCCI_STM32H7_MEMORY_FLASH2 UINT32_C(0x08100000)
///< Flash program memory (up to 1M)
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#define MCCI_STM32H7_MEMORY_FLASH_END UINT32_C(0x081FFFFF)
///< End of Flash program memory
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#define MCCI_STM32H7_MEMORY_SYSTEM UINT32_C(0x1FF00000)
///< System memory (128K)
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#define MCCI_STM32H7_MEMORY_SYSTEM_END UINT32_C(0x1FF1FFFF)
///< End of System memory
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#define MCCI_STM32H7_MEMORY_OTP UINT32_C(0x08FFF000)
///< OTP Area (1K)
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#define MCCI_STM32H7_MEMORY_OTP_END UINT32_C(0x08FFF3FF)
///< End of OTP Area
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#define MCCI_STM32H7_MEMORY_READ_ONLY UINT32_C(0x08FFF800)
///< read-only area (512)
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#define MCCI_STM32H7_MEMORY_ITCM_RAM UINT32_C(0x00000000)
///< ITCM RAM (64K)
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#define MCCI_STM32H7_MEMORY_DTCM_RAM UINT32_C(0x20000000)
///< DTCM RAM (128K)
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#define MCCI_STM32H7_MEMORY_AXI_SRAM1 UINT32_C(0x24000000)
///< AXI SRAM1 (up to 256K)
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#define MCCI_STM32H7_MEMORY_AXI_SRAM2 UINT32_C(0x24040000)
///< AXI SRAM2 (up to 384K)
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#define MCCI_STM32H7_MEMORY_AXI_SRAM3 UINT32_C(0x240A0000)
///< AXI SRAM3 (up to 384K)
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#define MCCI_STM32H7_MEMORY_AHB_SRAM1 UINT32_C(0x30000000)
///< AHB SRAM1 (up to 64K)
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#define MCCI_STM32H7_MEMORY_AHB_SRAM2 UINT32_C(0x30010000)
///< AHB SRAM2 (up to 64K)
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#define MCCI_STM32H7_MEMORY_SRD_SRAM UINT32_C(0x38000000)
///< SRD SRAM (up to 32K)
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#define MCCI_STM32H7_MEMORY_SRD_BKPSRAM UINT32_C(0x38800000)
///< SRD Backup SRAM (up to 4K)
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#define MCCI_STM32H7_REG_TIMER2 UINT32_C(0x40000000)
///< Section 43.4: TIMx register map (1K)
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#define MCCI_STM32H7_REG_TIMER3 UINT32_C(0x40000400)
///< Section 43.4: TIMx register map (1K)
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#define MCCI_STM32H7_REG_TIMER4 UINT32_C(0x40000800)
///< Section 43.4: TIMx register map (1K)
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#define MCCI_STM32H7_REG_TIMER5 UINT32_C(0x40000C00)
///< Section 43.4: TIMx register map (1K)
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#define MCCI_STM32H7_REG_TIMER6 UINT32_C(0x40001000)
///< Section 46.4: TIM6/7 register map (1K)
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#define MCCI_STM32H7_REG_TIMER7 UINT32_C(0x40001400)
///< Section 46.4: TIM6/7 register map (1K)
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#define MCCI_STM32H7_REG_TIMER12 UINT32_C(0x40001800)
///< Section 43.4: TIM6/7 register map (1K)
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#define MCCI_STM32H7_REG_TIMER13 UINT32_C(0x40001C00)
///< Section 43.4: TIM6/7 register map (1K)
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#define MCCI_STM32H7_REG_TIMER14 UINT32_C(0x40002000)
///< Section 43.4: TIM6/7 register map (1K)
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#define MCCI_STM32H7_REG_LPTIM1 UINT32_C(0x40002400)
///< Section 47.7: LPTIM register map (1K)
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#define MCCI_STM32H7_REG_SPI2 UINT32_C(0x40003800)
///< Section 55.11: SPI register map (1K)
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#define MCCI_STM32H7_REG_SPI3 UINT32_C(0x40003C00)
///< Section 55.11: SPI register map (1K)
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#define MCCI_STM32H7_REG_SPDIFRX1 UINT32_C(0x40004000)
///< Section 57.5: SPDIFRX interface register map (1K)
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#define MCCI_STM32H7_REG_USART2 UINT32_C(0x40004400)
///< Section 53.7: USART register map (1K)
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#define MCCI_STM32H7_REG_USART3 UINT32_C(0x40004800)
///< Section 53.7: USART register map (1K)
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#define MCCI_STM32H7_REG_UART4 UINT32_C(0x40004C00)
///< Section 53.7: USART register map (1K)
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#define MCCI_STM32H7_REG_UART5 UINT32_C(0x40005000)
///< Section 53.7: USART register map (1K)
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#define MCCI_STM32H7_REG_I2C1 UINT32_C(0x40005400)
///< Section 52.7: I2C register map (1K)
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#define MCCI_STM32H7_REG_I2C2 UINT32_C(0x40005800)
///< Section 52.7: I2C register map (1K)
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#define MCCI_STM32H7_REG_I2C3 UINT32_C(0x40005C00)
///< Section 52.7: I2C register map (1K)
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#define MCCI_STM32H7_REG_HDMI_CEC UINT32_C(0x40006C00)
///< Section 63.7: HDMI-CEC register map (1K)
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#define MCCI_STM32H7_REG_DAC1 UINT32_C(0x40007400)
///< Section 29.7: DAC register map (1K)
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#define MCCI_STM32H7_REG_UART7 UINT32_C(0x40007800)
///< Section 53.7: USART register map (1K)
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#define MCCI_STM32H7_REG_UART8 UINT32_C(0x40007C00)
///< Section 53.7: USART register map (1K)
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#define MCCI_STM32H7_REG_CRS UINT32_C(0x40008400)
///< Section 9.8: CRS register map (1K)
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#define MCCI_STM32H7_REG_SWPMI UINT32_C(0x40008800)
///< Section 58.6: SWPMI register map (1K)
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#define MCCI_STM32H7_REG_OPAMP UINT32_C(0x40009000)
///< Section 32.6: OPAMP register map (1K)
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#define MCCI_STM32H7_REG_MDIOS UINT32_C(0x40009400)
///< Section 59.4: MDIOS register map (1K)
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#define MCCI_STM32H7_REG_TT_FDCAN UINT32_C(0x4000A000)
///< Section 61.5: FDCAN register map (1K)
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#define MCCI_STM32H7_REG_FDCAN UINT32_C(0x4000A400)
///< Section 61.5: FDCAN register map (1K)
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#define MCCI_STM32H7_REG_CAN_CCU UINT32_C(0x4000A800)
///< Section 61.5: FDCAN register map (1K)
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#define MCCI_STM32H7_REG_CAN_MSG_RAM UINT32_C(0x4000AC00)
///< Section 61.5: FDCAN register map (1K)
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#define MCCI_STM32H7_REG_TIMER1 UINT32_C(0x40010000)
///< Section 42.4: TIMx register map (1K)
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#define MCCI_STM32H7_REG_TIMER8 UINT32_C(0x40010400)
///< Section 42.4: TIMx register map (1K)
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#define MCCI_STM32H7_REG_USART1 UINT32_C(0x40011000)
///< Section 53.7: USART register map (1K)
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#define MCCI_STM32H7_REG_USART6 UINT32_C(0x40011400)
///< Section 53.7: USART register map (1K)
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#define MCCI_STM32H7_REG_UART9 UINT32_C(0x40011800)
///< Section 53.7: USART register map (1K)
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#define MCCI_STM32H7_REG_USART10 UINT32_C(0x40011C00)
///< Section 53.7: USART register map (1K)
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#define MCCI_STM32H7_REG_SPI1 UINT32_C(0x40013000)
///< Section 55.11: SPI register map (1K)
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#define MCCI_STM32H7_REG_I2S1 UINT32_C(0x40013000)
///< Section 55.11: SPI register map (1K)
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#define MCCI_STM32H7_REG_SPI4 UINT32_C(0x40013400)
///< Section 55.11: SPI register map (1K)
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#define MCCI_STM32H7_REG_TIMER15 UINT32_C(0x40014000)
///< Section 45.5: TIMx register map (1K)
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#define MCCI_STM32H7_REG_TIMER16 UINT32_C(0x40014400)
///< Section 45.5: TIMx register map (1K)
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#define MCCI_STM32H7_REG_TIMER17 UINT32_C(0x40014800)
///< Section 45.5: TIMx register map (1K)
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#define MCCI_STM32H7_REG_SPI5 UINT32_C(0x40015000)
///< Section 55.11: SPI register map (1K)
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#define MCCI_STM32H7_REG_SAI1 UINT32_C(0x40015800)
///< Section 56.6: SAI register map (1K)
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#define MCCI_STM32H7_REG_SAI2 UINT32_C(0x40015C00)
///< Section 56.6: SAI register map (1K)
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#define MCCI_STM32H7_REG_DFSDM1 UINT32_C(0x40017800)
///< Section 33.7: 33.8: DFSDM register map (1K)
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#define MCCI_STM32H7_REG_DMA1 UINT32_C(0x40020000)
///< Section 15.5: DMA register map (1K)
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#define MCCI_STM32H7_REG_DMA2 UINT32_C(0x40020400)
///< Section 15.5: DMA register map (1K)
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#define MCCI_STM32H7_REG_DMAMUX1 UINT32_C(0x40020800)
///< Section 17.6: DMAMUX register map (1K)
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#define MCCI_STM32H7_REG_ADC1 UINT32_C(0x40022000)
///< Section 27.7: ADC register map (1K)
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#define MCCI_STM32H7_REG_CRC UINT32_C(0x40023000)
///< Section 22.4: CRC register map (1K)
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#define MCCI_STM32H7_REG_OTG_HS UINT32_C(0x40040000)
///< Section 62.14: OTG_HS register map (1K)
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#define MCCI_STM32H7_REG_DCMI UINT32_C(0x48020000)
///< Section 34.5: DCMI register map (1K)
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#define MCCI_STM32H7_REG_PSSI UINT32_C(0x48020400)
///< Section 35.5: PSSI register map (1K)
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#define MCCI_STM32H7_REG_HSEM UINT32_C(0x48020800)
///< Section 10.4: HSEM register map (1K)
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#define MCCI_STM32H7_REG_CRYPTO UINT32_C(0x48021000)
///< Section 39.7: CRYPTO register map (1K)
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#define MCCI_STM32H7_REG_HASH UINT32_C(0x48021400)
///< Section 40.7: HASH register map (1K)
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#define MCCI_STM32H7_REG_RNG UINT32_C(0x48021800)
///< Section 38.7: RNG register map (1K)
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#define MCCI_STM32H7_REG_SDMMC2 UINT32_C(0x48022400)
///< Section 60.10: SDMMC register map (1K)
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#define MCCI_STM32H7_REG_DLYB_SDMMC2 UINT32_C(0x48022800)
///< Section 26.4: DLYB register map (1K)
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#define MCCI_STM32H7_REG_BDMA1 UINT32_C(0x48022C00)
///< Section 16.6: BDMA register map (1K)
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#define MCCI_STM32H7_REG_LTDC UINT32_C(0x50001000)
///< Section 36.7: LTDC register map (4K)
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#define MCCI_STM32H7_REG_WWDG UINT32_C(0x50003000)
///< Section 48.4: WWDG register map (4K)
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#define MCCI_STM32H7_REG_GPV UINT32_C(0x51000000)
///< Section 2.2.4: AXI interconnect register map (1M)
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#define MCCI_STM32H7_REG_MDMA UINT32_C(0x52000000)
///< Section 14.5: MDMA register map (4K)
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#define MCCI_STM32H7_REG_DMA2D UINT32_C(0x52001000)
///< Section 18.5: DMA2D register map (4K)
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#define MCCI_STM32H7_REG_FLASH UINT32_C(0x52002000)
///< Section 4.9: FLASH register map (4K)
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#define MCCI_STM32H7_REG_JPEG UINT32_C(0x52003000)
///< Section 4.9: JPEG register map (4K)
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#define MCCI_STM32H7_REG_FMC UINT32_C(0x52004000)
///< Section 23.7.6: 23.8.7: 23.9.5: FMC register map (4K)
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#define MCCI_STM32H7_REG_OCTOSPI1 UINT32_C(0x52005000)
///< Section 24.7: OCTOSPI register map (4K)
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#define MCCI_STM32H7_REG_DLYB_OCTOSPI1 UINT32_C(0x52006000)
///< Section 26.4: DLYB register map (4K)
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#define MCCI_STM32H7_REG_SDMMC1 UINT32_C(0x52007000)
///< Section 60.10: SDMMC register map (4K)
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#define MCCI_STM32H7_REG_DLYB_SDMMC1 UINT32_C(0x52008000)
///< Section 26.4: DLYB register map (1K)
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#define MCCI_STM32H7_REG_RAMECC UINT32_C(0x52009000)
///< Section 3.4: RAMECC register map (1K)
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#define MCCI_STM32H7_REG_OCTOSPI2 UINT32_C(0x5200A000)
///< Section 24.7: OCTOSPI register map (4K)
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#define MCCI_STM32H7_REG_DLYB_OCTOSPI2 UINT32_C(0x5200B000)
///< Section 26.4: DLYB register map (1K)
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#define MCCI_STM32H7_REG_OTCOSPIM UINT32_C(0x5200B400)
///< Section 25.4: OTCOSPIM register map (1K)
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#define MCCI_STM32H7_REG_OTFDEC1 UINT32_C(0x5200B800)
///< Section 41.6: OTFDEC register map (1K)
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#define MCCI_STM32H7_REG_OTFDEC2 UINT32_C(0x5200BC00)
///< Section 41.6: OTFDEC register map (1K)
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#define MCCI_STM32H7_REG_GFXMMU UINT32_C(0x5200C000)
///< Section 21.5: GFXMMU register map (8K)
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#define MCCI_STM32H7_REG_EXTI UINT32_C(0x58000000)
///< Section 20.6: EXTI register map (1K)
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#define MCCI_STM32H7_REG_SYSCFG UINT32_C(0x58000400)
///< Section 12.4: SYSCFG register map (1K)
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#define MCCI_STM32H7_REG_LPUART1 UINT32_C(0x58000C00)
///< Section 54.6: LPUART register map (1K)
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#define MCCI_STM32H7_REG_SPI6 UINT32_C(0x58001400)
///< Section 55.11: SPI register map (1K)
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#define MCCI_STM32H7_REG_I2S6 UINT32_C(0x58001400)
///< Section 55.11: I2S register map (1K)
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#define MCCI_STM32H7_REG_I2C4 UINT32_C(0x58001C00)
///< Section 52.7: I2C register map (1K)
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#define MCCI_STM32H7_REG_LPTIM2 UINT32_C(0x58002400)
///< Section 47.7: LPTIM register map (1K)
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#define MCCI_STM32H7_REG_LPTIM3 UINT32_C(0x58002800)
///< Section 47.7: LPTIM register map (1K)
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#define MCCI_STM32H7_REG_DAC2 UINT32_C(0x58003400)
///< Section 29.7: DAC register map (1K)
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#define MCCI_STM32H7_REG_COMP UINT32_C(0x58003800)
///< Section 31.6: COMP register map (1K)
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#define MCCI_STM32H7_REG_VREF UINT32_C(0x58003C00)
///< Section 30.3: VREF register map (1K)
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#define MCCI_STM32H7_REG_RTC UINT32_C(0x58004000)
///< Section 50.6: RTC register map (1K)
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#define MCCI_STM32H7_REG_TAMP UINT32_C(0x58004400)
///< Section 51.6: TAMP register map (1K)
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#define MCCI_STM32H7_REG_IWDG UINT32_C(0x58004800)
///< Section 49.4: IWDG register map (1K)
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#define MCCI_STM32H7_REG_DTS UINT32_C(0x58006800)
///< Section 28.6: DTS register map (1K)
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#define MCCI_STM32H7_REG_DFSDM2 UINT32_C(0x58006C00)
///< Section 33.7: DFSDM register map (1K)
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#define MCCI_STM32H7_REG_GPIOA UINT32_C(0x58020000)
///< Section 11.4: GPIO register map (1K)
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#define MCCI_STM32H7_REG_GPIOB UINT32_C(0x58020400)
///< Section 11.4: GPIO register map (1K)
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#define MCCI_STM32H7_REG_GPIOC UINT32_C(0x58020800)
///< Section 11.4: GPIO register map (1K)
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#define MCCI_STM32H7_REG_GPIOD UINT32_C(0x58020C00)
///< Section 11.4: GPIO register map (1K)
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#define MCCI_STM32H7_REG_GPIOE UINT32_C(0x58021000)
///< Section 11.4: GPIO register map (1K)
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#define MCCI_STM32H7_REG_GPIOF UINT32_C(0x58021400)
///< Section 11.4: GPIO register map (1K)
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#define MCCI_STM32H7_REG_GPIOG UINT32_C(0x58021800)
///< Section 11.4: GPIO register map (1K)
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#define MCCI_STM32H7_REG_GPIOH UINT32_C(0x58021C00)
///< Section 11.4: GPIO register map (1K)
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#define MCCI_STM32H7_REG_GPIOI UINT32_C(0x58022000)
///< Section 11.4: GPIO register map (1K)
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#define MCCI_STM32H7_REG_GPIOJ UINT32_C(0x58022400)
///< Section 11.4: GPIO register map (1K)
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#define MCCI_STM32H7_REG_GPIOK UINT32_C(0x58022800)
///< Section 11.4: GPIO register map (1K)
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#define MCCI_STM32H7_REG_RCC UINT32_C(0x58024400)
///< Section 8.7: RCC register map (1K)
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#define MCCI_STM32H7_REG_PWR UINT32_C(0x58024800)
///< Section 6.8: PWR register map (1K)
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#define MCCI_STM32H7_REG_BDMA2 UINT32_C(0x58025400)
///< Section 16.6: BDMA register map (1K)
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#define MCCI_STM32H7_REG_DMAMUX2 UINT32_C(0x58025800)
///< Section 17.6: DMAMUX register map (1K)
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/// @}
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/****************************************************************************\
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|
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| Option bytes, etc
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|
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\****************************************************************************/
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/// \name System values in system option memory
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/// @{
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#define MCCI_STM32H7_OPTIONS_U_ID_0 UINT32_C(0x08FFF800)
///< register address: unique ID bits 31:0
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#define MCCI_STM32H7_OPTIONS_U_ID_4 (MCCI_STM32H7_OPTIONS_U_ID_0 + 0x04)
///< register address: unique ID bits 63:32
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#define MCCI_STM32H7_OPTIONS_U_ID_8 (MCCI_STM32H7_OPTIONS_U_ID_0 + 0x08)
///< register address: unique ID bits 95:64
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#define MCCI_STM32H7_OPTIONS_SYSTEM_FLASH_SIZE UINT32_C(0x08FFF80C)
///< memory size in k bytes (16 bits)
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/// \brief convert flash_size_16 value to bytes
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#define MCCI_STM32H7_OPTIONS_SYSTEM_FLASH_SIZE_TO_BYTES(h) \
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((h) & UINT32_C(0xFFFF)) == UINT32_C(0xFFFF) \
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? UINT32_C(0x200000) \
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: ((h) & UINT32_C(0xFFFF)) == UINT32_C(0) \
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? UINT32_C(0x200000) \
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: (((h) & UINT32_C(0xFFFF)) * 1024)
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#define MCCI_STM32H7_OPTIONS_PACKAGE_DATA UINT32_C(0x08FFF80E)
///< package data (16 bits)
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/// @}
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/****************************************************************************\
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|
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| Flash Control Registers (3.7)
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|
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\****************************************************************************/
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/// \name FLASH registers
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/// @{
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#define MCCI_STM32H7_REG_FLASH_ACR (MCCI_STM32H7_REG_FLASH + 0x000)
///< Flash access control register
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#define MCCI_STM32H7_REG_FLASH_KEYR1 (MCCI_STM32H7_REG_FLASH + 0x004)
///< Flash key register for bank 1
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#define MCCI_STM32H7_REG_FLASH_OPTKEYR (MCCI_STM32H7_REG_FLASH + 0x008)
///< Flash option key register
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#define MCCI_STM32H7_REG_FLASH_CR1 (MCCI_STM32H7_REG_FLASH + 0x00C)
///< Flash control register for bank 1
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#define MCCI_STM32H7_REG_FLASH_SR1 (MCCI_STM32H7_REG_FLASH + 0x010)
///< Flash status register for bank 1
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#define MCCI_STM32H7_REG_FLASH_CCR1 (MCCI_STM32H7_REG_FLASH + 0x014)
///< Flash clear control register for bank 1
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#define MCCI_STM32H7_REG_FLASH_OPTCR (MCCI_STM32H7_REG_FLASH + 0x018)
///< Flash option control register
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#define MCCI_STM32H7_REG_FLASH_OPTSR_CUR (MCCI_STM32H7_REG_FLASH + 0x01C)
///< Flash option status register
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#define MCCI_STM32H7_REG_FLASH_OPTSR_PRG (MCCI_STM32H7_REG_FLASH + 0x020)
///< Flash option status register
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#define MCCI_STM32H7_REG_FLASH_OPTCCR (MCCI_STM32H7_REG_FLASH + 0x024)
///< Flash option clear control register
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#define MCCI_STM32H7_REG_FLASH_PRAR_CUR1 (MCCI_STM32H7_REG_FLASH + 0x028)
///< Flash protection address for bank 1
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#define MCCI_STM32H7_REG_FLASH_PRAR_PRG1 (MCCI_STM32H7_REG_FLASH + 0x02C)
///< Flash protection address for bank 1
227
#define MCCI_STM32H7_REG_FLASH_SCAR_CUR1 (MCCI_STM32H7_REG_FLASH + 0x030)
///< Flash secure address for bank 1
228
#define MCCI_STM32H7_REG_FLASH_SCAR_PRG1 (MCCI_STM32H7_REG_FLASH + 0x034)
///< Flash secure address for bank 1
229
#define MCCI_STM32H7_REG_FLASH_WPSGN_CUR1 (MCCI_STM32H7_REG_FLASH + 0x038)
///< Flash write sector group protection for bank 1
230
#define MCCI_STM32H7_REG_FLASH_WPSGN_PRG1 (MCCI_STM32H7_REG_FLASH + 0x03C)
///< Flash write sector group protection for bank 1
231
#define MCCI_STM32H7_REG_FLASH_BOOT_CUR (MCCI_STM32H7_REG_FLASH + 0x040)
///< Flash boot address
232
#define MCCI_STM32H7_REG_FLASH_BOOT_PRG (MCCI_STM32H7_REG_FLASH + 0x044)
///< Flash boot address
233
#define MCCI_STM32H7_REG_FLASH_CRCCR1 (MCCI_STM32H7_REG_FLASH + 0x050)
///< Flash CRC control register for bank 1
234
#define MCCI_STM32H7_REG_FLASH_CRCSADD1 (MCCI_STM32H7_REG_FLASH + 0x054)
///< Flash CRC start address register for bank 1
235
#define MCCI_STM32H7_REG_FLASH_CRCEADD1 (MCCI_STM32H7_REG_FLASH + 0x058)
///< Flash CRC end address register for bank 1
236
#define MCCI_STM32H7_REG_FLASH_CRCDATA (MCCI_STM32H7_REG_FLASH + 0x05C)
///< Flash CRC data register
237
#define MCCI_STM32H7_REG_FLASH_ECC_FA1 (MCCI_STM32H7_REG_FLASH + 0x060)
///< Flash ECC fail address for bank 1
238
#define MCCI_STM32H7_REG_FLASH_OTPBL_CUR (MCCI_STM32H7_REG_FLASH + 0x068)
///< Flash OTP block lock
239
#define MCCI_STM32H7_REG_FLASH_OTPBL_PRG (MCCI_STM32H7_REG_FLASH + 0x06C)
///< Flash OTP block lock
240
#define MCCI_STM32H7_REG_FLASH_KEYR2 (MCCI_STM32H7_REG_FLASH + 0x104)
///< Flash key register for bank 2
241
#define MCCI_STM32H7_REG_FLASH_CR2 (MCCI_STM32H7_REG_FLASH + 0x10C)
///< Flash control register for bank 2
242
#define MCCI_STM32H7_REG_FLASH_SR2 (MCCI_STM32H7_REG_FLASH + 0x110)
///< Flash status register for bank 2
243
#define MCCI_STM32H7_REG_FLASH_CCR2 (MCCI_STM32H7_REG_FLASH + 0x114)
///< Flash clear control register for bank 2
244
#define MCCI_STM32H7_REG_FLASH_PRAR_CUR2 (MCCI_STM32H7_REG_FLASH + 0x128)
///< Flash protection address for bank 2
245
#define MCCI_STM32H7_REG_FLASH_PRAR_PRG2 (MCCI_STM32H7_REG_FLASH + 0x12C)
///< Flash protection address for bank 2
246
#define MCCI_STM32H7_REG_FLASH_SCAR_CUR2 (MCCI_STM32H7_REG_FLASH + 0x130)
///< Flash secure address for bank 2
247
#define MCCI_STM32H7_REG_FLASH_SCAR_PRG2 (MCCI_STM32H7_REG_FLASH + 0x134)
///< Flash secure address for bank 2
248
#define MCCI_STM32H7_REG_FLASH_WPSGN_CUR2 (MCCI_STM32H7_REG_FLASH + 0x138)
///< Flash write sector group protection for bank 2
249
#define MCCI_STM32H7_REG_FLASH_WPSGN_PRG2 (MCCI_STM32H7_REG_FLASH + 0x13C)
///< Flash write sector group protection for bank 2
250
#define MCCI_STM32H7_REG_FLASH_CRCCR2 (MCCI_STM32H7_REG_FLASH + 0x150)
///< Flash CRC control register for bank 2
251
#define MCCI_STM32H7_REG_FLASH_CRCSADD2 (MCCI_STM32H7_REG_FLASH + 0x154)
///< Flash CRC start address register for bank 2
252
#define MCCI_STM32H7_REG_FLASH_CRCEADD2 (MCCI_STM32H7_REG_FLASH + 0x158)
///< Flash CRC end address register for bank 2
253
#define MCCI_STM32H7_REG_FLASH_ECC_FA2 (MCCI_STM32H7_REG_FLASH + 0x160)
///< Flash ECC fail address for bank 2
254
/// @}
255
256
/// \name FLASH_ACR bits
257
/// @{
258
#define MCCI_STM32H7_REG_FLASH_ACR_RSV6 UINT32_C(0xFFFFFFC0)
///< Reserved, don't change
259
#define MCCI_STM32H7_REG_FLASH_ACR_WRHIGHFREQ (UINT32_C(3) << 4)
///< Flash signal delay
260
#define MCCI_STM32H7_REG_FLASH_ACR_WRHIGHFREQ_V(n) (UINT32_C(n) << 4)
///< Flash signal delay
261
#define MCCI_STM32H7_REG_FLASH_ACR_LATENCY (UINT32_C(0xF) << 0)
///< Read latency:
262
#define MCCI_STM32H7_REG_FLASH_ACR_LATENCY_V(n) (UINT32_C(n) << 0)
///< Read latency: n wait state
263
/// @}
264
265
/// \name FLASH_KEYR1, FLASH_KEYR2 bits
266
/// @{
267
#define MCCI_STM32H7_REG_FLASH_KEYR_UNLOCK1 UINT32_C(0x45670123)
///< unlock word 1 for FLASH_CR1
268
#define MCCI_STM32H7_REG_FLASH_KEYR_UNLOCK2 UINT32_C(0xCDEF89AB)
///< unlock word 2 for FLASH_CR1
269
/// @}
270
271
/// \name FLASH_OPTKEYR bits
272
/// @{
273
#define MCCI_STM32H7_REG_FLASH_OPTKEYR_UNLOCK1 UINT32_C(0x08192A3B)
///< unlock word 1 for option bytes
274
#define MCCI_STM32H7_REG_FLASH_OPTKEYR_UNLOCK2 UINT32_C(0x4C5D6E7F)
///< unlock word 2 for option bytes
275
/// @}
276
277
/// \name FLASH_CR1, FLASH_CR2 bits
278
/// @{
279
#define MCCI_STM32H7_REG_FLASH_CR_RSV29 (UINT32_C(7) << 29)
///< Reserved, don't change
280
#define MCCI_STM32H7_REG_FLASH_CR_CRCRDERRIE (UINT32_C(1) << 28)
///< ECC CRC read error interrupt enable
281
#define MCCI_STM32H7_REG_FLASH_CR_CRCENDIE (UINT32_C(1) << 27)
///< CRC end of calculation interrupt enable
282
#define MCCI_STM32H7_REG_FLASH_CR_DBECCERRIE (UINT32_C(1) << 26)
///< ECC double detection error interrupt enable
283
#define MCCI_STM32H7_REG_FLASH_CR_SNECCERRIE (UINT32_C(1) << 25)
///< ECC single correction error interrupt enable
284
#define MCCI_STM32H7_REG_FLASH_CR_RDSERRIE (UINT32_C(1) << 24)
///< secure error interrupt enable
285
#define MCCI_STM32H7_REG_FLASH_CR_RDPERRIE (UINT32_C(1) << 23)
///< read protection error interrupt enable
286
#define MCCI_STM32H7_REG_FLASH_CR_RSV22 (UINT32_C(1) << 22)
///< Reserved, don't change
287
#define MCCI_STM32H7_REG_FLASH_CR_INCERRIE (UINT32_C(1) << 21)
///< inconsistency error interrupt enable
288
#define MCCI_STM32H7_REG_FLASH_CR_RSV20 (UINT32_C(1) << 20)
///< Reserved, don't change
289
#define MCCI_STM32H7_REG_FLASH_CR_STRBERRIE (UINT32_C(1) << 19)
///< strobe error interrupt enable
290
#define MCCI_STM32H7_REG_FLASH_CR_PGSERRIE (UINT32_C(1) << 18)
///< programming sequence error interrupt enable
291
#define MCCI_STM32H7_REG_FLASH_CR_WRPERRIE (UINT32_C(1) << 17)
///< write protection error interrupt enable
292
#define MCCI_STM32H7_REG_FLASH_CR_EOPIE (UINT32_C(1) << 16)
///< End-of-program interrupt control
293
#define MCCI_STM32H7_REG_FLASH_CR_CRC_EN (UINT32_C(1) << 15)
///< CRC control
294
#define MCCI_STM32H7_REG_FLASH_CR_RSV13 (UINT32_C(3) << 13)
///< Reserved, don't change
295
#define MCCI_STM32H7_REG_FLASH_CR_SSN (UINT32_C(0x7F) << 6)
///< Sector erase selection number
296
#define MCCI_STM32H7_REG_FLASH_CR_SSN_N(n) ((n) << 6)
///< Sector erase selection number
297
#define MCCI_STM32H7_REG_FLASH_CR_START (UINT32_C(1) << 5)
///< Erase start control
298
#define MCCI_STM32H7_REG_FLASH_CR_FW (UINT32_C(1) << 4)
///< Write forcing control
299
#define MCCI_STM32H7_REG_FLASH_CR_BER (UINT32_C(1) << 3)
///< Bank erase request
300
#define MCCI_STM32H7_REG_FLASH_CR_SER (UINT32_C(1) << 2)
///< Sector erase request
301
#define MCCI_STM32H7_REG_FLASH_CR_PG (UINT32_C(1) << 1)
///< Internal buffer control
302
#define MCCI_STM32H7_REG_FLASH_CR_LOCK (UINT32_C(1) << 0)
///< Lock the FLASH_CR register
303
/// @}
304
305
/// \name FLASH_SR1, FLASH_SR2 bits
306
/// @{
307
#define MCCI_STM32H7_REG_FLASH_SR_RSV29 (UINT32_C(7) << 29)
///< Reserved, don't change.
308
#define MCCI_STM32H7_REG_FLASH_SR_CRCRDERR (UINT32_C(1) << 28)
///< ECC CRC read error flag
309
#define MCCI_STM32H7_REG_FLASH_SR_CRCEND (UINT32_C(1) << 27)
///< CRC end of calculation flag
310
#define MCCI_STM32H7_REG_FLASH_SR_DBECCERR (UINT32_C(1) << 26)
///< ECC double detection error flag
311
#define MCCI_STM32H7_REG_FLASH_SR_SNECCERR (UINT32_C(1) << 25)
///< ECC single correction error flag
312
#define MCCI_STM32H7_REG_FLASH_SR_RDSERR (UINT32_C(1) << 24)
///< secure error flag
313
#define MCCI_STM32H7_REG_FLASH_SR_RDPERR (UINT32_C(1) << 23)
///< read protection error flag
314
#define MCCI_STM32H7_REG_FLASH_SR_RSV22 (UINT32_C(1) << 22)
///< Reserved, don't change
315
#define MCCI_STM32H7_REG_FLASH_SR_INCERR (UINT32_C(1) << 21)
///< inconsistency error flag
316
#define MCCI_STM32H7_REG_FLASH_SR_RSV20 (UINT32_C(1) << 20)
///< Reserved, don't change
317
#define MCCI_STM32H7_REG_FLASH_SR_STRBERR (UINT32_C(1) << 19)
///< strobe error flag
318
#define MCCI_STM32H7_REG_FLASH_SR_PGSERR (UINT32_C(1) << 18)
///< programming sequence error flag
319
#define MCCI_STM32H7_REG_FLASH_SR_WRPERR (UINT32_C(1) << 17)
///< write protection error flag
320
#define MCCI_STM32H7_REG_FLASH_SR_EOP (UINT32_C(1) << 16)
///< End-of-program flag
321
#define MCCI_STM32H7_REG_FLASH_SR_RSV4 (UINT32_C(0xFFF) << 4)
///< Reserved, don't change.
322
#define MCCI_STM32H7_REG_FLASH_SR_CRC_BUSY (UINT32_C(1) << 3)
///< CRC busy flag
323
#define MCCI_STM32H7_REG_FLASH_SR_QW (UINT32_C(1) << 2)
///< wait queue flag
324
#define MCCI_STM32H7_REG_FLASH_SR_WBNE (UINT32_C(1) << 1)
///< write buffer not empty flag
325
#define MCCI_STM32H7_REG_FLASH_SR_BSY (UINT32_C(1) << 0)
///< Busy flag
326
/// @}
327
328
/// \name FLASH_CCR1, FLASH_CCR2 bits
329
/// @{
330
#define MCCI_STM32H7_REG_FLASH_CCR_RSV29 (UINT32_C(7) << 29)
///< Reserved, don't change
331
#define MCCI_STM32H7_REG_FLASH_CCR_CRCRDERR (UINT32_C(1) << 28)
///< CRCRDERR flag clear
332
#define MCCI_STM32H7_REG_FLASH_CCR_CRCEND (UINT32_C(1) << 27)
///< CRCEND flag clear
333
#define MCCI_STM32H7_REG_FLASH_CCR_DBECCERR (UINT32_C(1) << 26)
///< DBECCERR flag clear
334
#define MCCI_STM32H7_REG_FLASH_CCR_SNECCERR (UINT32_C(1) << 25)
///< SNECCERR flag clear
335
#define MCCI_STM32H7_REG_FLASH_CCR_RDSERR (UINT32_C(1) << 24)
///< RDSERR flag clear
336
#define MCCI_STM32H7_REG_FLASH_CCR_RDPERR (UINT32_C(1) << 23)
///< RDPERR flag clear
337
#define MCCI_STM32H7_REG_FLASH_CCR_RSV22 (UINT32_C(1) << 22)
///< Reserved, don't change
338
#define MCCI_STM32H7_REG_FLASH_CCR_INCERR (UINT32_C(1) << 21)
///< INCERR flag clear
339
#define MCCI_STM32H7_REG_FLASH_CCR_RSV20 (UINT32_C(1) << 20)
///< Reserved, don't change
340
#define MCCI_STM32H7_REG_FLASH_CCR_STRBERR (UINT32_C(1) << 19)
///< STRBERR flag clear
341
#define MCCI_STM32H7_REG_FLASH_CCR_PGSERR (UINT32_C(1) << 18)
///< PGSERR flag clear
342
#define MCCI_STM32H7_REG_FLASH_CCR_EOP (UINT32_C(1) << 16)
///< EOP flag clear
343
#define MCCI_STM32H7_REG_FLASH_CCR_RSV0 (UINT32_C(0xFFFF) << 0)
///< Reserved, don't change
344
/// @}
345
346
/// \name FLASH_OPTCR bits
347
/// @{
348
#define MCCI_STM32H7_REG_FLASH_OPTCR_SWAP_BANK (UINT32_C(1) << 31)
///< Bank swapping option configuration
349
#define MCCI_STM32H7_REG_FLASH_OPTCR_OPTCHANGEERRIE (UINT32_C(1) << 30)
///< Option byte change error interrupt enable
350
#define MCCI_STM32H7_REG_FLASH_OPTCR_RSV29 (UINT32_C(1) << 29)
///< Reserved, don't change
351
#define MCCI_STM32H7_REG_FLASH_OPTCR_PG_OTP (UINT32_C(1) << 5)
///< OTP program control
352
#define MCCI_STM32H7_REG_FLASH_OPTCR_MER (UINT32_C(1) << 4)
///< mass erase request
353
#define MCCI_STM32H7_REG_FLASH_OPTCR_RSV22 (UINT32_C(3) << 2)
///< Reserved, don't change
354
#define MCCI_STM32H7_REG_FLASH_OPTCR_OPTSTART (UINT32_C(1) << 1)
///< Option byte start change option configuration
355
#define MCCI_STM32H7_REG_FLASH_OPTCR_OPTLOCK (UINT32_C(1) << 0)
///< FLASH_OPTCR lock option configuration
356
/// @}
357
358
/// \name FLASH_OPTSR_CUR, FLASH_OPTSR_PRG bits
359
/// @{
360
#define MCCI_STM32H7_REG_FLASH_OPTSR_SWAP_BANK_OPT (UINT32_C(1) << 31)
///< Bank swapping option status
361
#define MCCI_STM32H7_REG_FLASH_OPTSR_OPTCHANGEERR (UINT32_C(1) << 30)
///< Option byte change error flag
362
#define MCCI_STM32H7_REG_FLASH_OPTSR_VDDIO_HSLV (UINT32_C(1) << 29)
///< VDD I/O high-speed at low-voltage status
363
#define MCCI_STM32H7_REG_FLASH_OPTSR_RSV26 (UINT32_C(7) << 26)
///< Reserved, don't change
364
#define MCCI_STM32H7_REG_FLASH_OPTSR_RSV22 (UINT32_C(0xF) << 22)
///< Reserved, don't change
365
#define MCCI_STM32H7_REG_FLASH_OPTSR_SECURITY (UINT32_C(1) << 21)
///< Security enable option status
366
#define MCCI_STM32H7_REG_FLASH_OPTSR_ST_RAM_SIZE (UINT32_C(3) << 19)
///< ST RAM size option
367
#define MCCI_STM32H7_REG_FLASH_OPTSR_ST_RAM_SIZE_2KB (UINT32_C(0) << 19)
///< 2KB reserved to ST code
368
#define MCCI_STM32H7_REG_FLASH_OPTSR_ST_RAM_SIZE_4KB (UINT32_C(1) << 19)
///< 2KB reserved to ST code
369
#define MCCI_STM32H7_REG_FLASH_OPTSR_ST_RAM_SIZE_8KB (UINT32_C(2) << 19)
///< 2KB reserved to ST code
370
#define MCCI_STM32H7_REG_FLASH_OPTSR_ST_RAM_SIZE_16KB (UINT32_C(3) << 19)
///< 2KB reserved to ST code
371
#define MCCI_STM32H7_REG_FLASH_OPTSR_IWDG_FZ_SDBY (UINT32_C(1) << 18)
///< IWDG Standby mode freeze option status
372
#define MCCI_STM32H7_REG_FLASH_OPTSR_IWDG_FZ_STOP (UINT32_C(1) << 17)
///< IWDG Stop mode freeze option status
373
#define MCCI_STM32H7_REG_FLASH_OPTSR_VDDMMC_HSLV (UINT32_C(1) << 16)
///< VDDMMC I/O high-speed at low-voltage status
374
#define MCCI_STM32H7_REG_FLASH_OPTSR_RDP (UINT32_C(0xFF) << 8)
///< Readout protection level option status
375
#define MCCI_STM32H7_REG_FLASH_OPTSR_RDP_LEVEL_0 (UINT32_C(0xAA) << 8)
///< global readout protection level 0
376
#define MCCI_STM32H7_REG_FLASH_OPTSR_RDP_LEVEL_2 (UINT32_C(0xCC) << 8)
///< global readout protection level 2
377
#define MCCI_STM32H7_REG_FLASH_OPTSR_RDP_LEVEL_1 (UINT32_C(0xBB) << 8)
///< others values: global readout protection level 1
378
#define MCCI_STM32H7_REG_FLASH_OPTSR_NRST_STDY (UINT32_C(1) << 7)
///< Core domain Standby entry reset option status
379
#define MCCI_STM32H7_REG_FLASH_OPTSR_NRST_STOP (UINT32_C(1) << 6)
///< Core domain DStop entry reset option status
380
#define MCCI_STM32H7_REG_FLASH_OPTSR_RSV5 (UINT32_C(1) << 5)
///< Reserved, don't change
381
#define MCCI_STM32H7_REG_FLASH_OPTSR_IWDG_SW (UINT32_C(1) << 4)
///< IWDG control mode option status
382
#define MCCI_STM32H7_REG_FLASH_OPTSR_BOR_LEV (UINT32_C(3) << 2)
///< Brownout level option status
383
#define MCCI_STM32H7_REG_FLASH_OPTSR_BOR_LEV_OFF (UINT32_C(0) << 2)
///< BOR OFF
384
#define MCCI_STM32H7_REG_FLASH_OPTSR_BOR_LEV_1 (UINT32_C(1) << 2)
///< BOR Level 1, the threshold level is low (around 2.1 V)
385
#define MCCI_STM32H7_REG_FLASH_OPTSR_BOR_LEV_2 (UINT32_C(2) << 2)
///< BOR Level 2, the threshold level is medium (around 2.4 V)
386
#define MCCI_STM32H7_REG_FLASH_OPTSR_BOR_LEV_3 (UINT32_C(3) << 2)
///< BOR Level 3, the threshold level is high (around 2.7 V)
387
#define MCCI_STM32H7_REG_FLASH_OPTSR_RSV1 (UINT32_C(1) << 1)
///< Reserved, don't change
388
#define MCCI_STM32H7_REG_FLASH_OPTSR_OPT_BUSY (UINT32_C(1) << 0)
///< Option byte change ongoing flag
389
/// @}
390
391
/// \name FLASH_OPTCCR bits
392
/// @{
393
#define MCCI_STM32H7_REG_FLASH_OPTCCR_RSV31 (UINT32_C(1) << 31)
///< Reserved, don't change
394
#define MCCI_STM32H7_REG_FLASH_OPTCCR_OPTCHANGEERR (UINT32_C(1) << 30)
///< OPTCHANGEERR reset
395
#define MCCI_STM32H7_REG_FLASH_OPTCCR_RSV0 (0x3FFFFFFF)
///< Reserved, don't change
396
/// @}
397
398
/// \name FLASH_PRAR_CUR1, FLASH_PRAR_PRG1, FLASH_PRAR_CUR2, FLASH_PRAR_PRG2 bits
399
/// @{
400
#define MCCI_STM32H7_REG_FLASH_PRAR_DMEP (UINT32_C(1) << 31)
///< PCROP protected erase enable option status
401
#define MCCI_STM32H7_REG_FLASH_PRAR_RSV28 (UINT32_C(7) << 28)
///< Reserved, don't change
402
#define MCCI_STM32H7_REG_FLASH_PRAR_PROT_AREA_END (UINT32_C(0xFFF) << 16)
///< PCROP area end status
403
#define MCCI_STM32H7_REG_FLASH_PRAR_RSV12 (UINT32_C(15) << 12)
///< Reserved, don't change
404
#define MCCI_STM32H7_REG_FLASH_PRAR_PROT_AREA_START (UINT32_C(0xFFF) << 0)
///< PCROP area start status
405
/// @}
406
407
/// \name FLASH_SCAR_CUR1, FLASH_SCAR_PRG1, FLASH_SCAR_CUR2, FLASH_SCAR_PRG2 bits
408
/// @{
409
#define MCCI_STM32H7_REG_FLASH_SCAR_DMES (UINT32_C(1) << 31)
///< secure access protected erase enable option status
410
#define MCCI_STM32H7_REG_FLASH_SCAR_RSV28 (UINT32_C(7) << 28)
///< Reserved, don't change
411
#define MCCI_STM32H7_REG_FLASH_SCAR_SEC_AREA_END (UINT32_C(0xFFF) << 16)
///< secure-only area end status
412
#define MCCI_STM32H7_REG_FLASH_SCAR_RSV12 (UINT32_C(15) << 12)
///< Reserved, don't change
413
#define MCCI_STM32H7_REG_FLASH_SCAR_SEC_AREA_START (UINT32_C(0xFFF) << 0)
///< secure-only area start status
414
/// @}
415
416
/// \name FLASH_WPSGN_CUR1, FLASH_WPSGN_PRG1, FLASH_WPSGN_CUR2, FLASH_WPSGN_PRG2 bits
417
/// @{
418
#define MCCI_STM32H7_REG_FLASH_WPSGN_SECT(n) (UINT32_C(1) << (((n) & 127) >> 2))
///< Group embedding sectors
419
/// @}
420
421
/// \name FLASH_BOOT_CUR, FLASH_BOOT_PRG bits
422
/// @{
423
#define MCCI_STM32H7_REG_FLASH_BOOT_ADD1 (UINT32_C(0xFFFF) << 16)
///< boot address 1
424
#define MCCI_STM32H7_REG_FLASH_BOOT_ADD0 (UINT32_C(0xFFFF) << 0)
///< boot address 0
425
/// @}
426
427
/// \name FLASH_CRCCR1, FLASH_CRCCR2 bits
428
/// @{
429
#define MCCI_STM32H7_REG_FLASH_CRCCR_RSV23 (UINT32_C(0x1FF) << 23)
///< Reserved, don't change
430
#define MCCI_STM32H7_REG_FLASH_CRCCR_ALL_BANK (UINT32_C(1) << 22)
///< all CRC select
431
#define MCCI_STM32H7_REG_FLASH_CRCCR_CRC_BURST (UINT32_C(3) << 20)
///< CRC burst size
432
#define MCCI_STM32H7_REG_FLASH_CRCCR_RSV18 (UINT32_C(3) << 18)
///< Reserved, don't change
433
#define MCCI_STM32H7_REG_FLASH_CRCCR_CLEAN_CRC (UINT32_C(1) << 17)
///< CRC clear bit
434
#define MCCI_STM32H7_REG_FLASH_CRCCR_START_CRC (UINT32_C(1) << 16)
///< CRC start bit
435
#define MCCI_STM32H7_REG_FLASH_CRCCR_RSV11 (UINT32_C(0x1F) << 11)
///< Reserved, don't change
436
#define MCCI_STM32H7_REG_FLASH_CRCCR_CLEAN_SECT (UINT32_C(1) << 10)
///< CRC sector list clear bit
437
#define MCCI_STM32H7_REG_FLASH_CRCCR_ADD_SECT (UINT32_C(1) << 9)
///< CRC sector select bit
438
#define MCCI_STM32H7_REG_FLASH_CRCCR_CRC_BY_SECT (UINT32_C(1) << 8)
///< CRC sector mode select bit
439
#define MCCI_STM32H7_REG_FLASH_CRCCR_RSV7 (UINT32_C(1) << 7)
///< Reserved, don't change
440
#define MCCI_STM32H7_REG_FLASH_CRCCR_CRC_SECT (UINT32_C(0x7F) << 0)
///< CRC sector number
441
/// @}
442
443
/// \name FLASH_CRCSADD1, FLASH_CRCSADD2 bits
444
/// @{
445
#define MCCI_STM32H7_REG_FLASH_CRCSADD_RSV20 (UINT32_C(0xFFF) << 20)
///< Reserved, don't change
446
#define MCCI_STM32H7_REG_FLASH_CRCSADD_CRC_START_ADDR (UINT32_C(0x3FFFF) << 2)
///< CRC start address on bank 1/2
447
#define MCCI_STM32H7_REG_FLASH_CRCSADD_RSV0 (UINT32_C(3) << 0)
///< Reserved, don't change
448
/// @}
449
450
/// \name FLASH_CRCEADD1, FLASH_CRCEADD2 bits
451
/// @{
452
#define MCCI_STM32H7_REG_FLASH_CRCEADD_RSV20 (UINT32_C(0xFFF) << 20)
///< Reserved, don't change
453
#define MCCI_STM32H7_REG_FLASH_CRCEADD_CRC_START_ADDR (UINT32_C(0x3FFFF) << 2)
///< CRC end address on bank 1/2
454
#define MCCI_STM32H7_REG_FLASH_CRCEADD_RSV0 (UINT32_C(3) << 0)
///< Reserved, don't change
455
/// @}
456
457
/// \name FLASH_ECC_FA1, FLASH_ECC_FA2 bits
458
/// @{
459
#define MCCI_STM32H7_REG_FLASH_ECC_FA_OTP_FAIL_ECC (UINT32_C(1) << 31)
///< OTP ECC error bit
460
#define MCCI_STM32H7_REG_FLASH_ECC_FA_RSV16 (UINT32_C(0x7FFF) << 16)
///< Reserved, don't change
461
#define MCCI_STM32H7_REG_FLASH_ECC_FA_FAIL_ECC_ADDR (UINT32_C(0xFFFF) << 0)
///< ECC error address
462
/// @}
463
464
/// \name FLASH_OTPBL_CUR, FLASH_OTPBL_PRG bits
465
/// @{
466
#define MCCI_STM32H7_REG_FLASH_OTPBL_RSV16 (UINT32_C(0xFFFF) << 16)
///< Reserved, don't change
467
#define MCCI_STM32H7_REG_FLASH_OTPBL_LOCKBL (UINT32_C(0xFFFF) << 0)
///< OTP Block Lock
468
/// @}
469
470
/// \name Flash programming constants
471
/// @{
472
#define MCCI_STM32H7_FLASH_SECTOR_SIZE UINT32_C(8192)
///< size in bytes of a sector
473
#define MCCI_STM32H7_FLASH_PROGRAM_FLASH_SIZE UINT32_C(16)
///< size in bytes of a FLASH program
474
#define MCCI_STM32H7_FLASH_PROGRAM_OTP_SIZE UINT32_C(2)
///< size in bytes of a FLASH program
475
476
#define MCCI_STM32H7_FLASH_IS_VALID(f) ((f) >= MCCI_STM32H7_MEMORY_FLASH && (f) <= MCCI_STM32H7_MEMORY_FLASH_END)
477
#define MCCI_STM32H7_FLASH_IS_BANK2(f) ((f) & UINT32_C(0x100000))
478
#define MCCI_STM32H7_FLASH_GET_BANK(f) (((f) >> 20) & 1)
479
#define MCCI_STM32H7_FLASH_GET_SECTOR(f) (((f) >> 13) & 0x7F)
480
/// @}
481
482
/****************************************************************************\
483
|
484
| Power Control Registers
485
|
486
\****************************************************************************/
487
488
/// \name PWR registers
489
/// @{
490
#define MCCI_STM32H7_REG_PWR_CR1 (MCCI_STM32H7_REG_PWR + 0x00)
///< control
491
#define MCCI_STM32H7_REG_PWR_CSR1 (MCCI_STM32H7_REG_PWR + 0x04)
///< control status
492
#define MCCI_STM32H7_REG_PWR_CR2 (MCCI_STM32H7_REG_PWR + 0x08)
///< control 2
493
#define MCCI_STM32H7_REG_PWR_CR3 (MCCI_STM32H7_REG_PWR + 0x0C)
///< control 3
494
#define MCCI_STM32H7_REG_PWR_CPUCR (MCCI_STM32H7_REG_PWR + 0x10)
///< CPU control
495
#define MCCI_STM32H7_REG_PWR_SRDCR (MCCI_STM32H7_REG_PWR + 0x18)
///< SmartRun domain control
496
#define MCCI_STM32H7_REG_PWR_WKUPCR (MCCI_STM32H7_REG_PWR + 0x20)
///< wakeup clear
497
#define MCCI_STM32H7_REG_PWR_WKUPFR (MCCI_STM32H7_REG_PWR + 0x24)
///< wakeup flag
498
#define MCCI_STM32H7_REG_PWR_WKUPEPR (MCCI_STM32H7_REG_PWR + 0x28)
///< wakeup enable and polarity
499
/// @}
500
501
/// \name PWR_CR1 bits
502
/// @{
503
#define MCCI_STM32H7_REG_PWR_CR1_RSV28 (UINT32_C(15) << 28)
///< Reserved, don't change
504
#define MCCI_STM32H7_REG_PWR_CR1_SRDRAMSO (UINT32_C(1) << 27)
///< SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode
505
#define MCCI_STM32H7_REG_PWR_CR1_HSITFSO (UINT32_C(1) << 26)
///< high-speed interfaces USB and FDCAN memory shut-off in DStop/DStop2 mode
506
#define MCCI_STM32H7_REG_PWR_CR1_GFXSO (UINT32_C(1) << 25)
///< GFXMMU and JPEG memory shut-off in DStop/DStop2 mode
507
#define MCCI_STM32H7_REG_PWR_CR1_ITCMSO (UINT32_C(1) << 24)
///< instruction TCM and ETM memory shut-off in DStop/DStop2 mode
508
#define MCCI_STM32H7_REG_PWR_CR1_AHBRAM2SO (UINT32_C(1) << 23)
///< AHB SRAM2 shut-off in DStop/DStop2 mode
509
#define MCCI_STM32H7_REG_PWR_CR1_AHBRAM1SO (UINT32_C(1) << 22)
///< AHB SRAM1 shut-off in DStop/DStop2 mode
510
#define MCCI_STM32H7_REG_PWR_CR1_AXIRAM3SO (UINT32_C(1) << 21)
///< AXI SRAM3 shut-off in DStop/DStop2 mode
511
#define MCCI_STM32H7_REG_PWR_CR1_AXIRAM2SO (UINT32_C(1) << 20)
///< AXI SRAM2 shut-off in DStop/DStop2 mode
512
#define MCCI_STM32H7_REG_PWR_CR1_AXIRAM1SO (UINT32_C(1) << 19)
///< AXI SRAM1 shut-off in DStop/DStop2 mode
513
#define MCCI_STM32H7_REG_PWR_CR1_ALS (UINT32_C(3) << 17)
///< analog voltage detector level selection
514
#define MCCI_STM32H7_REG_PWR_CR1_ALS_1_7V (UINT32_C(0) << 17)
///< 1.7V
515
#define MCCI_STM32H7_REG_PWR_CR1_ALS_2_1V (UINT32_C(1) << 17)
///< 2.1V
516
#define MCCI_STM32H7_REG_PWR_CR1_ALS_2_5V (UINT32_C(2) << 17)
///< 2.5V
517
#define MCCI_STM32H7_REG_PWR_CR1_ALS_2_8V (UINT32_C(3) << 17)
///< 2.8V
518
#define MCCI_STM32H7_REG_PWR_CR1_AVDEN (UINT32_C(1) << 16)
///< peripheral voltage monitor on VDDA enable
519
#define MCCI_STM32H7_REG_PWR_CR1_SVOS (UINT32_C(3) << 14)
///< system stop mode voltage scaling selection
520
#define MCCI_STM32H7_REG_PWR_CR1_SVOS_5 (UINT32_C(1) << 14)
///< SVOS5 scale 5
521
#define MCCI_STM32H7_REG_PWR_CR1_SVOS_4 (UINT32_C(2) << 14)
///< SVOS5 scale 4
522
#define MCCI_STM32H7_REG_PWR_CR1_SVOS_3 (UINT32_C(3) << 14)
///< SVOS5 scale 3
523
#define MCCI_STM32H7_REG_PWR_CR1_AVD_READY (UINT32_C(1) << 13)
///< analog voltage ready
524
#define MCCI_STM32H7_REG_PWR_CR1_BOOSTE (UINT32_C(1) << 12)
///< analog switch VBoost control
525
#define MCCI_STM32H7_REG_PWR_CR1_RSV10 (UINT32_C(3) << 10)
///< Reserved, don't change
526
#define MCCI_STM32H7_REG_PWR_CR1_FLPS (UINT32_C(1) << 9)
///< Flash memory low-power mode in DStop or DStop2 mode
527
#define MCCI_STM32H7_REG_PWR_CR1_DBP (UINT32_C(1) << 8)
///< disable Backup domain write protection
528
#define MCCI_STM32H7_REG_PWR_CR1_PLS (UINT32_C(7) << 5)
///< programmable voltage detector level selection
529
#define MCCI_STM32H7_REG_PWR_CR1_PLS_1_95V (UINT32_C(0) << 5)
///< 1.95V
530
#define MCCI_STM32H7_REG_PWR_CR1_PLS_2_1V (UINT32_C(1) << 5)
///< 2.1V
531
#define MCCI_STM32H7_REG_PWR_CR1_PLS_2_25V (UINT32_C(2) << 5)
///< 2.25V
532
#define MCCI_STM32H7_REG_PWR_CR1_PLS_2_4V (UINT32_C(3) << 5)
///< 2.4V
533
#define MCCI_STM32H7_REG_PWR_CR1_PLS_2_55V (UINT32_C(4) << 5)
///< 2.55V
534
#define MCCI_STM32H7_REG_PWR_CR1_PLS_2_7V (UINT32_C(5) << 5)
///< 2.7V
535
#define MCCI_STM32H7_REG_PWR_CR1_PLS_2_85V (UINT32_C(6) << 5)
///< 2.85V
536
#define MCCI_STM32H7_REG_PWR_CR1_PLS_PVD_IN (UINT32_C(7) << 5)
///< PVD_IN pin
537
#define MCCI_STM32H7_REG_PWR_CR1_PVDE (UINT32_C(1) << 4)
///< programmable voltage detector enable
538
#define MCCI_STM32H7_REG_PWR_CR1_RSV1 (UINT32_C(7) << 1)
///< Reserved, don't change
539
#define MCCI_STM32H7_REG_PWR_CR1_LPDS (UINT32_C(1) << 0)
///< low-power Deepsleep with SVOS3
540
/// @}
541
542
/// \name PWR_CSR1 bits
543
/// @{
544
#define MCCI_STM32H7_REG_PWR_CSR1_RSV18 UINT32C(0xFFFC0000)
///< reserved, do not change
545
#define MCCI_STM32H7_REG_PWR_CSR1_MMCVDO (UINT32_C(1) << 17)
///< voltage detector output on VDDMMC
546
#define MCCI_STM32H7_REG_PWR_CSR1_AVDO (UINT32_C(1) << 16)
///< analog voltage detector output on VDDA
547
#define MCCI_STM32H7_REG_PWR_CSR1_ACTVOS (UINT32_C(3) << 14)
///< VOS currently applied for VCORE voltage scaling selection
548
#define MCCI_STM32H7_REG_PWR_CSR1_ACTVOSRDY (UINT32_C(1) << 13)
///< Regulator low-power flag
549
#define MCCI_STM32H7_REG_PWR_CSR1_RSV5 (UINT32_C(0xFF) << 5)
///< Reserved, do not change
550
#define MCCI_STM32H7_REG_PWR_CSR1_PVDO (UINT32_C(1) << 4)
///< programmable voltage detect output
551
#define MCCI_STM32H7_REG_PWR_CSR1_RSV0 (UINT32_C(0xF) << 0)
///< Reserved, do not change
552
/// @}
553
554
/// \name PWR_CR2 bits
555
/// @{
556
#define MCCI_STM32H7_REG_PWR_CR2_RSV24 (UINT32_C(0xFF) << 24)
///< Reserved, don't change
557
#define MCCI_STM32H7_REG_PWR_CR2_TEMPH (UINT32_C(1) << 23)
///< temperature level monitoring versus high threshold
558
#define MCCI_STM32H7_REG_PWR_CR2_TEMPL (UINT32_C(1) << 22)
///< temperature level monitoring versus low threshold
559
#define MCCI_STM32H7_REG_PWR_CR2_RSV17 (UINT32_C(0x1F) << 17)
///< Reserved, don't change
560
#define MCCI_STM32H7_REG_PWR_CR2_BRRDY (UINT32_C(1) << 16)
///< backup regulator ready
561
#define MCCI_STM32H7_REG_PWR_CR2_RSV5 (UINT32_C(0x7FF) << 5)
///< Reserved, don't change
562
#define MCCI_STM32H7_REG_PWR_CR2_MONEN (UINT32_C(1) << 4)
///< VBAT and temperature monitoring enable
563
#define MCCI_STM32H7_REG_PWR_CR2_RSV1 (UINT32_C(7) << 1)
///< Reserved, don't change
564
#define MCCI_STM32H7_REG_PWR_CR2_BREN (UINT32_C(1) << 0)
///< backup regulator enable
565
/// @}
566
567
/// \name PWR_CR3 bits
568
/// @{
569
#define MCCI_STM32H7_REG_PWR_CR3_RSV27 (UINT32_C(0x1F) << 27)
///< Reserved, don't change
570
#define MCCI_STM32H7_REG_PWR_CR3_USB33RDY (UINT32_C(1) << 26)
///< USB supply ready
571
#define MCCI_STM32H7_REG_PWR_CR3_USBREGEN (UINT32_C(1) << 25)
///< USB regulator enable
572
#define MCCI_STM32H7_REG_PWR_CR3_USB33DEN (UINT32_C(1) << 24)
///< VDD33USB voltage level detector enable
573
#define MCCI_STM32H7_REG_PWR_CR3_RSV17 (UINT32_C(0x7F) << 17)
///< Reserved, don't change
574
#define MCCI_STM32H7_REG_PWR_CR3_SMPSEXTRDY (UINT32_C(1) << 16)
///< SMPS step-down converter external supply ready
575
#define MCCI_STM32H7_REG_PWR_CR3_RSV10 (UINT32_C(0x3F) << 10)
///< Reserved, don't change
576
#define MCCI_STM32H7_REG_PWR_CR3_VBRS (UINT32_C(1) << 9)
///< VBAT charging resistor selection
577
#define MCCI_STM32H7_REG_PWR_CR3_VBE (UINT32_C(1) << 8)
///< VBAT charging enable
578
#define MCCI_STM32H7_REG_PWR_CR3_RSV6 (UINT32_C(3) << 6)
///< Reserved, don't change
579
#define MCCI_STM32H7_REG_PWR_CR3_SMPSLEVEL (UINT32_C(3) << 4)
///< SMPS step-down converter voltage output level selection
580
#define MCCI_STM32H7_REG_PWR_CR3_SMPSLEVEL_1_8V (UINT32_C(1) << 4)
///< 1.8V
581
#define MCCI_STM32H7_REG_PWR_CR3_SMPSLEVEL_2_5V (UINT32_C(2) << 4)
///< 2.5V
582
#define MCCI_STM32H7_REG_PWR_CR3_SMPSLEVEL_2V5 (UINT32_C(3) << 4)
///< 2.5V
583
#define MCCI_STM32H7_REG_PWR_CR3_SMPSEXTHP (UINT32_C(1) << 3)
///< SMPS step-down converter external power delivery selection
584
#define MCCI_STM32H7_REG_PWR_CR3_SMPSEN (UINT32_C(1) << 2)
///< SMPS step-down converter enable
585
#define MCCI_STM32H7_REG_PWR_CR3_LDOEN (UINT32_C(1) << 1)
///< low drop-out regulator enable
586
#define MCCI_STM32H7_REG_PWR_CR3_BYPASS (UINT32_C(1) << 0)
///< power management unit bypass
587
/// @}
588
589
/// \name PWR_CPUCR bits
590
/// @{
591
#define MCCI_STM32H7_REG_PWR_CPUCR_RSV12 UINT32_C(0xFFFFF000)
///< Reserved, don't change
592
#define MCCI_STM32H7_REG_PWR_CPUCR_RUN_SRD (UINT32_C(1) << 11)
///< temperature level monitoring versus high threshold
593
#define MCCI_STM32H7_REG_PWR_CPUCR_RSV10 (UINT32_C(1) << 10)
///< Reserved, don't change
594
#define MCCI_STM32H7_REG_PWR_CPUCR_CSSF (UINT32_C(1) << 9)
///< clear Standby and Stop flags (always read as 0)
595
#define MCCI_STM32H7_REG_PWR_CPUCR_RSV7 (UINT32_C(3) << 7)
///< Reserved, don't change
596
#define MCCI_STM32H7_REG_PWR_CPUCR_SBF (UINT32_C(1) << 6)
///< system Standby flag
597
#define MCCI_STM32H7_REG_PWR_CPUCR_STOPF (UINT32_C(1) << 5)
///< STOP flag
598
#define MCCI_STM32H7_REG_PWR_CPUCR_RSV3 (UINT32_C(3) << 3)
///< Reserved, don't change
599
#define MCCI_STM32H7_REG_PWR_CPUCR_PDDS_SRD (UINT32_C(1) << 2)
///< system SmartRun domain power down Deepsleep
600
#define MCCI_STM32H7_REG_PWR_CPUCR_RSV1 (UINT32_C(1) << 1)
///< Reserved, don't change
601
#define MCCI_STM32H7_REG_PWR_CPUCR_RETDS_CD (UINT32_C(1) << 0)
///< CPU domain power down Deepsleep selection
602
/// @}
603
604
/// \name PWR_SRDCR bits
605
/// @{
606
#define MCCI_STM32H7_REG_PWR_SRDCR_RSV16 UINT32_C(0xFFFF0000)
///< Reserved, don't change
607
#define MCCI_STM32H7_REG_PWR_SRDCR_VOS (UINT32_C(3) << 14)
///< voltage scaling selection according to performance
608
#define MCCI_STM32H7_REG_PWR_SRDCR_VOS_SCALE3 (UINT32_C(0) << 14)
///< scale 3
609
#define MCCI_STM32H7_REG_PWR_SRDCR_VOS_SCALE2 (UINT32_C(1) << 14)
///< scale 2
610
#define MCCI_STM32H7_REG_PWR_SRDCR_VOS_SCALE1 (UINT32_C(2) << 14)
///< scale 1
611
#define MCCI_STM32H7_REG_PWR_SRDCR_VOS_SCALE0 (UINT32_C(3) << 14)
///< scale 0
612
#define MCCI_STM32H7_REG_PWR_SRDCR_VOSRDY (UINT32_C(1) << 13)
///< VOS ready bit for VCORE voltage scaling output selection
613
#define MCCI_STM32H7_REG_PWR_SRDCR_RSV0 UINT32_C(0x00001FFF)
///< Reserved, don't change
614
/// @}
615
616
/// \name PWR_WKUPCR bits
617
/// @{
618
#define MCCI_STM32H7_REG_PWR_WKUPCR_RSV6 UINT32_C(0xFFFFFC00)
///< Reserved, don't change
619
#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC6 (UINT32_C(1) << 5)
///< clear wakeup pin flag for WKUP6
620
#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC5 (UINT32_C(1) << 4)
///< clear wakeup pin flag for WKUP5
621
#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC4 (UINT32_C(1) << 3)
///< clear wakeup pin flag for WKUP4
622
#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC3 (UINT32_C(1) << 2)
///< clear wakeup pin flag for WKUP3
623
#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC2 (UINT32_C(1) << 1)
///< clear wakeup pin flag for WKUP2
624
#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC1 (UINT32_C(1) << 0)
///< clear wakeup pin flag for WKUP1
625
626
#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC(n) (UINT32_C(1) << ((n)-1))
627
/// @}
628
629
/// \name PWR_WKUPFR bits
630
/// @{
631
#define MCCI_STM32H7_REG_PWR_WKUPFR_RSV6 UINT32_C(0xFFFFFC00)
///< Reserved, don't change
632
#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF6 (UINT32_C(1) << 5)
///< wakeup pin flag for WKUP6
633
#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF5 (UINT32_C(1) << 4)
///< wakeup pin flag for WKUP5
634
#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF4 (UINT32_C(1) << 3)
///< wakeup pin flag for WKUP4
635
#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF3 (UINT32_C(1) << 2)
///< wakeup pin flag for WKUP3
636
#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF2 (UINT32_C(1) << 1)
///< wakeup pin flag for WKUP2
637
#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF1 (UINT32_C(1) << 0)
///< wakeup pin flag for WKUP1
638
639
#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF(n) (UINT32_C(1) << ((n)-1))
640
/// @}
641
642
/// \name PWR_WKUPEPR bits
643
/// @{
644
#define MCCI_STM32H7_REG_PWR_WKUPEPR_RSV28 UINT32_C(0xF0000000)
///< Reserved, don't change
645
#define MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD6 (UINT32_C(3) << 26)
///< wakeup pin pull configuration for WKUP6
646
#define MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD5 (UINT32_C(3) << 24)
///< wakeup pin pull configuration for WKUP5
647
#define MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD4 (UINT32_C(3) << 22)
///< wakeup pin pull configuration for WKUP4
648
#define MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD3 (UINT32_C(3) << 20)
///< wakeup pin pull configuration for WKUP3
649
#define MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD2 (UINT32_C(3) << 18)
///< wakeup pin pull configuration for WKUP2
650
#define MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD1 (UINT32_C(3) << 16)
///< wakeup pin pull configuration for WKUP1
651
652
#define MCCI_STM32H7_REG_PWR_WKUPEPR_NOPU(n) (UINT32_C(0) << ((((n)-1)*2)+16))
///< no pull-up WKUPn
653
#define MCCI_STM32H7_REG_PWR_WKUPEPR_PU(n) (UINT32_C(1) << ((((n)-1)*2)+16))
///< pull-up WKUPn
654
#define MCCI_STM32H7_REG_PWR_WKUPEPR_PD(n) (UINT32_C(2) << ((((n)-1)*2)+16))
///< pull-down WKUPn
655
656
#define MCCI_STM32H7_REG_PWR_WKUPEPR_RSV14 (UINT32_C(3) << 14)
///< Reserved, don't change
657
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP6 (UINT32_C(1) << 13)
///< wakeup pin polarity for WKUP6
658
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP5 (UINT32_C(1) << 12)
///< wakeup pin polarity for WKUP5
659
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP4 (UINT32_C(1) << 11)
///< wakeup pin polarity for WKUP4
660
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP3 (UINT32_C(1) << 10)
///< wakeup pin polarity for WKUP3
661
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP2 (UINT32_C(1) << 9)
///< wakeup pin polarity for WKUP2
662
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP1 (UINT32_C(1) << 8)
///< wakeup pin polarity for WKUP1
663
#define MCCI_STM32H7_REG_PWR_WKUPEPR_RSV6 (UINT32_C(3) << 6)
///< Reserved, don't change
664
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN6 (UINT32_C(1) << 5)
///< enable wakeup pin for WKUP6
665
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN5 (UINT32_C(1) << 4)
///< enable wakeup pin for WKUP5
666
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN4 (UINT32_C(1) << 3)
///< enable wakeup pin for WKUP4
667
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN3 (UINT32_C(1) << 2)
///< enable wakeup pin for WKUP3
668
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN2 (UINT32_C(1) << 1)
///< enable wakeup pin for WKUP2
669
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN1 (UINT32_C(1) << 0)
///< enable wakeup pin for WKUP1
670
/// @}
671
672
/****************************************************************************\
673
|
674
| Reset and Clock Control (RCC) Registers
675
|
676
\****************************************************************************/
677
678
/// \name RCC registers
679
/// @{
680
#define MCCI_STM32H7_REG_RCC_CR (MCCI_STM32H7_REG_RCC + 0x00)
///< source control
681
#define MCCI_STM32H7_REG_RCC_HSICFGR (MCCI_STM32H7_REG_RCC + 0x04)
///< HSI calibration
682
#define MCCI_STM32H7_REG_RCC_CRRCR (MCCI_STM32H7_REG_RCC + 0x08)
///< Clock recovery RC
683
#define MCCI_STM32H7_REG_RCC_CSICFGR (MCCI_STM32H7_REG_RCC + 0x0C)
///< CSI calibration
684
#define MCCI_STM32H7_REG_RCC_CFGR (MCCI_STM32H7_REG_RCC + 0x10)
///< Clock configuration
685
#define MCCI_STM32H7_REG_RCC_CDCFGR1 (MCCI_STM32H7_REG_RCC + 0x14)
///< CPU domain clock configuration
686
#define MCCI_STM32H7_REG_RCC_CDCFGR2 (MCCI_STM32H7_REG_RCC + 0x18)
///< CPU domain clock configuration
687
#define MCCI_STM32H7_REG_RCC_SRDCFGR (MCCI_STM32H7_REG_RCC + 0x20)
///< SmartRun domain clock configuration
688
#define MCCI_STM32H7_REG_RCC_PLLCKSELR (MCCI_STM32H7_REG_RCC + 0x28)
///< PLLs clock source selection
689
#define MCCI_STM32H7_REG_RCC_PLLCFGR (MCCI_STM32H7_REG_RCC + 0x2C)
///< PLLs configuration
690
#define MCCI_STM32H7_REG_RCC_PLL1DIVR (MCCI_STM32H7_REG_RCC + 0x30)
///< PLL1 dividers configuration
691
#define MCCI_STM32H7_REG_RCC_PLL1FRACR (MCCI_STM32H7_REG_RCC + 0x34)
///< PLL1 fractional divider
692
#define MCCI_STM32H7_REG_RCC_PLL2DIVR (MCCI_STM32H7_REG_RCC + 0x38)
///< PLL2 dividers configuration
693
#define MCCI_STM32H7_REG_RCC_PLL2FRACR (MCCI_STM32H7_REG_RCC + 0x3C)
///< PLL2 fractional divider
694
#define MCCI_STM32H7_REG_RCC_PLL3DIVR (MCCI_STM32H7_REG_RCC + 0x40)
///< PLL3 dividers configuration
695
#define MCCI_STM32H7_REG_RCC_PLL3FRACR (MCCI_STM32H7_REG_RCC + 0x44)
///< PLL4 fractional divider
696
#define MCCI_STM32H7_REG_RCC_CDCCIPR (MCCI_STM32H7_REG_RCC + 0x4C)
///< CPU domain kernel clock configuration
697
#define MCCI_STM32H7_REG_RCC_CDCCIP1R (MCCI_STM32H7_REG_RCC + 0x50)
///< CPU domain kernel clock configuration
698
#define MCCI_STM32H7_REG_RCC_CDCCIP2R (MCCI_STM32H7_REG_RCC + 0x54)
///< CPU domain kernel clock configuration
699
#define MCCI_STM32H7_REG_RCC_SRDCCIPR (MCCI_STM32H7_REG_RCC + 0x58)
///< SmartRun domain kernel clock configuration
700
#define MCCI_STM32H7_REG_RCC_CIER (MCCI_STM32H7_REG_RCC + 0x60)
///< clock source interrupt enable
701
#define MCCI_STM32H7_REG_RCC_CIFR (MCCI_STM32H7_REG_RCC + 0x64)
///< clock source interrupt flag
702
#define MCCI_STM32H7_REG_RCC_CICR (MCCI_STM32H7_REG_RCC + 0x68)
///< clock source interrupt clear
703
#define MCCI_STM32H7_REG_RCC_BDCR (MCCI_STM32H7_REG_RCC + 0x70)
///< Backup domain control
704
#define MCCI_STM32H7_REG_RCC_CSR (MCCI_STM32H7_REG_RCC + 0x74)
///< clock control and status
705
#define MCCI_STM32H7_REG_RCC_AHB3RSTR (MCCI_STM32H7_REG_RCC + 0x7C)
///< AHB3 reset
706
#define MCCI_STM32H7_REG_RCC_AHB1RSTR (MCCI_STM32H7_REG_RCC + 0x80)
///< AHB1 peripheral reset
707
#define MCCI_STM32H7_REG_RCC_AHB2RSTR (MCCI_STM32H7_REG_RCC + 0x84)
///< AHB2 peripheral reset
708
#define MCCI_STM32H7_REG_RCC_AHB4RSTR (MCCI_STM32H7_REG_RCC + 0x88)
///< AHB4 peripheral reset
709
#define MCCI_STM32H7_REG_RCC_APB3RSTR (MCCI_STM32H7_REG_RCC + 0x8C)
///< APB3 peripheral reset
710
#define MCCI_STM32H7_REG_RCC_APB1LRSTR (MCCI_STM32H7_REG_RCC + 0x90)
///< APB1 peripheral reset
711
#define MCCI_STM32H7_REG_RCC_APB1HRSTR (MCCI_STM32H7_REG_RCC + 0x94)
///< APB1 peripheral reset
712
#define MCCI_STM32H7_REG_RCC_APB2RSTR (MCCI_STM32H7_REG_RCC + 0x98)
///< APB2 peripheral reset
713
#define MCCI_STM32H7_REG_RCC_APB4RSTR (MCCI_STM32H7_REG_RCC + 0x9C)
///< APB4 peripheral reset
714
#define MCCI_STM32H7_REG_RCC_SRDAMR (MCCI_STM32H7_REG_RCC + 0xA8)
///< SmartRun domain Autonomous mode
715
#define MCCI_STM32H7_REG_RCC_CKGAENR (MCCI_STM32H7_REG_RCC + 0xB0)
///< AXI clocks gating enable
716
#define MCCI_STM32H7_REG_RCC_RSR (MCCI_STM32H7_REG_RCC + 0x130)
///< reset status
717
#define MCCI_STM32H7_REG_RCC_AHB3ENR (MCCI_STM32H7_REG_RCC + 0x134)
///< AHB3 clock
718
#define MCCI_STM32H7_REG_RCC_AHB1ENR (MCCI_STM32H7_REG_RCC + 0x138)
///< AHB1 clock
719
#define MCCI_STM32H7_REG_RCC_AHB2ENR (MCCI_STM32H7_REG_RCC + 0x13C)
///< AHB2 clock
720
#define MCCI_STM32H7_REG_RCC_AHB4ENR (MCCI_STM32H7_REG_RCC + 0x140)
///< AHB4 clock
721
#define MCCI_STM32H7_REG_RCC_APB3ENR (MCCI_STM32H7_REG_RCC + 0x144)
///< APB3 clock
722
#define MCCI_STM32H7_REG_RCC_APB1LENR (MCCI_STM32H7_REG_RCC + 0x148)
///< APB1 clock
723
#define MCCI_STM32H7_REG_RCC_APB1HENR (MCCI_STM32H7_REG_RCC + 0x14C)
///< APB1 clock
724
#define MCCI_STM32H7_REG_RCC_APB2ENR (MCCI_STM32H7_REG_RCC + 0x150)
///< APB2 clock
725
#define MCCI_STM32H7_REG_RCC_APB4ENR (MCCI_STM32H7_REG_RCC + 0x154)
///< APB4 clock
726
#define MCCI_STM32H7_REG_RCC_AHB3LPENR (MCCI_STM32H7_REG_RCC + 0x15C)
///< AHB3 sleep clock
727
#define MCCI_STM32H7_REG_RCC_AHB1LPENR (MCCI_STM32H7_REG_RCC + 0x160)
///< AHB1 sleep clock
728
#define MCCI_STM32H7_REG_RCC_AHB2LPENR (MCCI_STM32H7_REG_RCC + 0x164)
///< AHB2 sleep clock
729
#define MCCI_STM32H7_REG_RCC_AHB4LPENR (MCCI_STM32H7_REG_RCC + 0x168)
///< AHB4 sleep clock
730
#define MCCI_STM32H7_REG_RCC_APB3LPENR (MCCI_STM32H7_REG_RCC + 0x16C)
///< APB3 sleep clock
731
#define MCCI_STM32H7_REG_RCC_APB1LLPENR (MCCI_STM32H7_REG_RCC + 0x170)
///< APB1 low-sleep clock
732
#define MCCI_STM32H7_REG_RCC_APB1HLPENR (MCCI_STM32H7_REG_RCC + 0x174)
///< APB1 high-sleep clock
733
#define MCCI_STM32H7_REG_RCC_APB2LPENR (MCCI_STM32H7_REG_RCC + 0x178)
///< APB2 sleep clock
734
#define MCCI_STM32H7_REG_RCC_APB4LPENR (MCCI_STM32H7_REG_RCC + 0x17C)
///< APB4 sleep clock
735
/// @}
736
737
/// \name RCC_CR bits
738
/// @{
739
#define MCCI_STM32H7_REG_RCC_CR_RSV30 (UINT32_C(3) << 30)
//< reserved, no change
740
#define MCCI_STM32H7_REG_RCC_CR_PLL3RDY (UINT32_C(1) << 29)
//< PLL3 clock ready flag
741
#define MCCI_STM32H7_REG_RCC_CR_PLL3ON (UINT32_C(1) << 28)
//< PLL3 enable
742
#define MCCI_STM32H7_REG_RCC_CR_PLL2RDY (UINT32_C(1) << 27)
//< PLL2 clock ready flag
743
#define MCCI_STM32H7_REG_RCC_CR_PLL2ON (UINT32_C(1) << 26)
//< PLL2 enable
744
#define MCCI_STM32H7_REG_RCC_CR_PLL1RDY (UINT32_C(1) << 25)
//< PLL1 clock ready flag
745
#define MCCI_STM32H7_REG_RCC_CR_PLL1ON (UINT32_C(1) << 24)
//< PLL1 enable
746
#define MCCI_STM32H7_REG_RCC_CR_RSV21 (UINT32_C(7) << 21)
//< reserved, no change
747
#define MCCI_STM32H7_REG_RCC_CR_HSEEXT (UINT32_C(1) << 20)
//< external high speed clock type in Bypass mode
748
#define MCCI_STM32H7_REG_RCC_CR_HSECSSON (UINT32_C(1) << 19)
//< HSE clock security system enable
749
#define MCCI_STM32H7_REG_RCC_CR_HSEBYP (UINT32_C(1) << 18)
//< enable HSE clock bypass
750
#define MCCI_STM32H7_REG_RCC_CR_HSERDY (UINT32_C(1) << 17)
//< HSE clock ready
751
#define MCCI_STM32H7_REG_RCC_CR_HSEON (UINT32_C(1) << 16)
//< HSE clock enabled
752
#define MCCI_STM32H7_REG_RCC_CR_CDCKRDY (UINT32_C(1) << 15)
//< CPU domain clocks ready flag
753
#define MCCI_STM32H7_REG_RCC_CR_CPUCKRDY (UINT32_C(1) << 14)
//< CPU related clocks ready flag
754
#define MCCI_STM32H7_REG_RCC_CR_HSI48RDY (UINT32_C(1) << 13)
//< HSI48 clock ready flag
755
#define MCCI_STM32H7_REG_RCC_CR_HSI48ON (UINT32_C(1) << 12)
//< HSI48 clock enable
756
#define MCCI_STM32H7_REG_RCC_CR_RSV10 (UINT32_C(3) << 10)
//< reserved, no change
757
#define MCCI_STM32H7_REG_RCC_CR_CSIKERON (UINT32_C(1) << 9)
//< CSI clock enable in Stop mode
758
#define MCCI_STM32H7_REG_RCC_CR_CSIRDY (UINT32_C(1) << 8)
//< CSI clock ready
759
#define MCCI_STM32H7_REG_RCC_CR_CSION (UINT32_C(1) << 7)
//< CSI clock enable
760
#define MCCI_STM32H7_REG_RCC_CR_RSV6 (UINT32_C(1) << 6)
//< reserved, no change
761
#define MCCI_STM32H7_REG_RCC_CR_HSIDIVF (UINT32_C(1) << 5)
//< HSI divider flag
762
#define MCCI_STM32H7_REG_RCC_CR_HSIDIV (UINT32_C(3) << 3)
//< HSI clock divider
763
#define MCCI_STM32H7_REG_RCC_CR_HSIDIV_1 (UINT32_C(0) << 3)
//< division by 1, hsi_ck=64MHz
764
#define MCCI_STM32H7_REG_RCC_CR_HSIDIV_2 (UINT32_C(1) << 3)
//< division by 2, hsi_ck=32MHz
765
#define MCCI_STM32H7_REG_RCC_CR_HSIDIV_3 (UINT32_C(2) << 3)
//< division by 4, hsi_ck=16MHz
766
#define MCCI_STM32H7_REG_RCC_CR_HSIDIV_8 (UINT32_C(3) << 3)
//< division by 8, hsi_ck=8MHz
767
#define MCCI_STM32H7_REG_RCC_CR_HSIRDY (UINT32_C(1) << 2)
//< HSI clock ready flag
768
#define MCCI_STM32H7_REG_RCC_CR_HSIKERON (UINT32_C(1) << 1)
//< HSI clock enable in Stop mode
769
#define MCCI_STM32H7_REG_RCC_CR_HSION (UINT32_C(1) << 0)
//< HSI clock enable
770
/// @}
771
772
/// \name RCC_HSICFGR bits
773
/// @{
774
#define MCCI_STM32H7_REG_RCC_HSICFGR_RSV31 (UINT32_C(1) << 31)
//< reserved, no change
775
#define MCCI_STM32H7_REG_RCC_HSICFGR_HSITRIM (UINT32_C(0x7F) << 24)
//< HSI clock trimming
776
#define MCCI_STM32H7_REG_RCC_HSICFGR_RSV12 (UINT32_C(0xFFF) << 12)
//< reserved, no change
777
#define MCCI_STM32H7_REG_RCC_HSICFGR_HSICAL (UINT32_C(0xFFF) << 0)
//< HSI clock cal
778
/// @}
779
780
/// \name RCC_CRRCR bits
781
/// @{
782
#define MCCI_STM32H7_REG_RCC_CRRCR_RSV10 UINT32_C(0xFFFFFC00)
//< reserved, don't change
783
#define MCCI_STM32H7_REG_RCC_CRRCR_HSI48CAL (UINT32_C(0x3FF) << 0)
//< calibration for HSI48
784
/// @}
785
786
/// \name RCC_CSICFGR bits
787
/// @{
788
#define MCCI_STM32H7_REG_RCC_CSICFGR_RSV30 (UINT32_C(3) << 30)
//< reserved, no change
789
#define MCCI_STM32H7_REG_RCC_CSICFGR_CSITRIM (UINT32_C(0x3F) << 24)
//< CSI clock trimming
790
#define MCCI_STM32H7_REG_RCC_CSICFGR_RSV8 (UINT32_C(0xFFFF) << 8)
//< reserved, no change
791
#define MCCI_STM32H7_REG_RCC_CSICFGR_CSICAL (UINT32_C(0xFF) << 0)
//< CSI clock calibration
792
/// @}
793
794
/// \name RCC_CFGR bits
795
/// @{
796
#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL (UINT32_C(7) << 29)
//< microcontroller clock output 2
797
#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_SYS (UINT32_C(0) << 29)
//< System clock
798
#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_PLL2 (UINT32_C(1) << 29)
//< PLL2
799
#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_HSE (UINT32_C(2) << 29)
//< HSE
800
#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_PLL1 (UINT32_C(3) << 29)
//< PLL1
801
#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_CSI (UINT32_C(4) << 29)
//< CSI
802
#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_LSI (UINT32_C(5) << 29)
//< LSI
803
#define MCCI_STM32H7_REG_RCC_CFGR_MCO2PRE (UINT32_C(0xF) << 25)
//< MCO2 prescaler
804
#define MCCI_STM32H7_REG_RCC_CFGR_MCO2PRE_DIS (UINT32_C(0) << 25)
//< prescaler disabled (default after reset)
805
#define MCCI_STM32H7_REG_RCC_CFGR_MCO2PRE_N(n) ((n) << 25)
//< division by n
806
#define MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL (UINT32_C(7) << 22)
//< microcontroller clock output 1
807
#define MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL_HSI (UINT32_C(0) << 22)
//< HSI
808
#define MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL_LSE (UINT32_C(1) << 22)
//< LSE
809
#define MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL_HSE (UINT32_C(2) << 22)
//< HSE
810
#define MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL_PLL1 (UINT32_C(3) << 22)
//< PLL1
811
#define MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL_HSI48 (UINT32_C(4) << 22)
//< HSI48
812
#define MCCI_STM32H7_REG_RCC_CFGR_MCO1PRE (UINT32_C(0xF) << 18)
//< MCO1 prescaler
813
#define MCCI_STM32H7_REG_RCC_CFGR_MCO1PRE_DIS (UINT32_C(0) << 18)
//< prescaler disabled (default after reset)
814
#define MCCI_STM32H7_REG_RCC_CFGR_MCO1PRE_N(n) ((n) << 18)
//< division by n
815
#define MCCI_STM32H7_REG_RCC_CFGR_RSV16 (UINT32_C(3) << 16)
//< reserved, don't change
816
#define MCCI_STM32H7_REG_RCC_CFGR_TIMPRE (UINT32_C(1) << 15)
//< timers clocks prescaler selection
817
#define MCCI_STM32H7_REG_RCC_CFGR_RSV14 (UINT32_C(1) << 14)
//< reserved, don't change
818
#define MCCI_STM32H7_REG_RCC_CFGR_RTCPRE (UINT32_C(0x3F) << 8)
//< HSE division factor for RTC clock
819
#define MCCI_STM32H7_REG_RCC_CFGR_RTCPRE_DIS (UINT32_C(0) << 8)
//< no clock (default after reset)
820
#define MCCI_STM32H7_REG_RCC_CFGR_RTCPRE_N(n) ((n) << 8)
//< HSE/n
821
#define MCCI_STM32H7_REG_RCC_CFGR_STOPKERWUCK (UINT32_C(1) << 7)
//< kernel clock selection after a wake up from system Stop
822
#define MCCI_STM32H7_REG_RCC_CFGR_STOPWUCK (UINT32_C(1) << 6)
//< system clock selection after a wake up from system Stop
823
#define MCCI_STM32H7_REG_RCC_CFGR_SWS (UINT32_C(7) << 3)
//< system clock switch status
824
#define MCCI_STM32H7_REG_RCC_CFGR_SWS_HSI (UINT32_C(0) << 3)
//< HSI used as system clock
825
#define MCCI_STM32H7_REG_RCC_CFGR_SWS_CSI (UINT32_C(1) << 3)
//< CSI used as system clock
826
#define MCCI_STM32H7_REG_RCC_CFGR_SWS_HSE (UINT32_C(2) << 3)
//< HSE used as system clock
827
#define MCCI_STM32H7_REG_RCC_CFGR_SWS_PLL1 (UINT32_C(3) << 3)
//< PLL1 used as system clock
828
#define MCCI_STM32H7_REG_RCC_CFGR_SW (UINT32_C(3) << 0)
//< system clock and trace clock switch
829
#define MCCI_STM32H7_REG_RCC_CFGR_SW_HSI (UINT32_C(0) << 0)
//< HSI selected as system clock
830
#define MCCI_STM32H7_REG_RCC_CFGR_SW_CSI (UINT32_C(1) << 0)
//< CSI selected as system clock
831
#define MCCI_STM32H7_REG_RCC_CFGR_SW_HSE (UINT32_C(2) << 0)
//< HSE selected as system clock
832
#define MCCI_STM32H7_REG_RCC_CFGR_SW_PLL1 (UINT32_C(3) << 0)
//< PLL1 selected as system clock
833
/// @}
834
835
/// \name RCC_CDCFGR1 bits
836
/// @{
837
#define MCCI_STM32H7_REG_RCC_CDCFGR1_RSV12 UINT32_C(0xFFFFF000)
//< reserved, no change
838
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE (UINT32_C(0xF) << 8)
//< CPU domain core prescaler
839
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_1 (UINT32_C(0) << 8)
//< sys_ck not divided
840
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_2 (UINT32_C(0x8) << 8)
//< sys_ck divided by 2
841
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_4 (UINT32_C(0x9) << 8)
//< sys_ck divided by 4
842
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_5 (UINT32_C(0xA) << 8)
//< sys_ck divided by 8
843
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_16 (UINT32_C(0xB) << 8)
//< sys_ck divided by 16
844
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_64 (UINT32_C(0xC) << 8)
//< sys_ck divided by 64
845
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_128 (UINT32_C(0xD) << 8)
//< sys_ck divided by 128
846
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_256 (UINT32_C(0xE) << 8)
//< sys_ck divided by 256
847
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_512 (UINT32_C(0xF) << 8)
//< sys_ck divided by 512
848
#define MCCI_STM32H7_REG_RCC_CDCFGR1_RSV7 (UINT32_C(1) << 7)
//< reserved, no change
849
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE (UINT32_C(7) << 4)
//< CPU domain APB3 prescaler
850
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE_1 (UINT32_C(0) << 4)
//< rcc_pclk3 = rcc_hclk3
851
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE_2 (UINT32_C(4) << 4)
//< rcc_pclk3 = rcc_hclk3 / 2
852
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE_3 (UINT32_C(5) << 4)
//< rcc_pclk3 = rcc_hclk3 / 4
853
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE_8 (UINT32_C(6) << 4)
//< rcc_pclk3 = rcc_hclk3 / 8
854
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE_16 (UINT32_C(7) << 4)
//< rcc_pclk3 = rcc_hclk3 / 16
855
#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE (UINT32_C(0xF) << 0)
//< CPU domain AHB prescaler
856
#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_1 (UINT32_C(0) << 0)
//< rcc_hclk3 = sys_cdcpre_ck
857
#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_2 (UINT32_C(0x8) << 0)
//< rcc_hclk3 = sys_cdcpre_ck / 2
858
#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_4 (UINT32_C(0x9) << 0)
//< rcc_hclk3 = sys_cdcpre_ck / 4
859
#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_8 (UINT32_C(0xA) << 0)
//< rcc_hclk3 = sys_cdcpre_ck / 8
860
#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_16 (UINT32_C(0xB) << 0)
//< rcc_hclk3 = sys_cdcpre_ck / 16
861
#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_64 (UINT32_C(0xC) << 0)
//< rcc_hclk3 = sys_cdcpre_ck / 64
862
#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_128 (UINT32_C(0xD) << 0)
//< rcc_hclk3 = sys_cdcpre_ck / 128
863
#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_256 (UINT32_C(0xE) << 0)
//< rcc_hclk3 = sys_cdcpre_ck / 256
864
#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_512 (UINT32_C(0xF) << 0)
//< rcc_hclk3 = sys_cdcpre_ck / 512
865
/// @}
866
867
/// \name RCC_CDCFGR2 bits
868
/// @{
869
#define MCCI_STM32H7_REG_RCC_CDCFGR2_RSV11 UINT32_C(0xFFFFF800)
//< reserved, no change
870
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2 (UINT32_C(7) << 8)
//< CPU domain APB2 prescaler
871
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2_1 (UINT32_C(0) << 8)
//< rcc_pclk2 = rcc_hclk1
872
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2_2 (UINT32_C(4) << 8)
//< rcc_pclk2 = rcc_hclk1 / 2
873
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2_3 (UINT32_C(5) << 8)
//< rcc_pclk2 = rcc_hclk1 / 4
874
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2_8 (UINT32_C(6) << 8)
//< rcc_pclk2 = rcc_hclk1 / 8
875
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2_16 (UINT32_C(7) << 8)
//< rcc_pclk2 = rcc_hclk1 / 16
876
#define MCCI_STM32H7_REG_RCC_CDCFGR2_RSV7 (UINT32_C(1) << 7)
//< reserved, no change
877
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1 (UINT32_C(7) << 4)
//< CPU domain APB1 prescaler
878
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1_1 (UINT32_C(0) << 4)
//< rcc_pclk1 = rcc_hclk1
879
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1_2 (UINT32_C(4) << 4)
//< rcc_pclk1 = rcc_hclk1 / 2
880
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1_3 (UINT32_C(5) << 4)
//< rcc_pclk1 = rcc_hclk1 / 4
881
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1_8 (UINT32_C(6) << 4)
//< rcc_pclk1 = rcc_hclk1 / 8
882
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1_16 (UINT32_C(7) << 4)
//< rcc_pclk1 = rcc_hclk1 / 16
883
#define MCCI_STM32H7_REG_RCC_CDCFGR2_RSV0 (UINT32_C(0xF) << 0)
//< reserved, no change
884
/// @}
885
886
/// \name RCC_SRDCFGR bits
887
/// @{
888
#define MCCI_STM32H7_REG_RCC_SRDCFGR_RSV7 UINT32_C(0xFFFFFF80)
//< reserved, no change
889
#define MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE (UINT32_C(7) << 4)
//< SmartRun domain APB4 prescaler
890
#define MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE_1 (UINT32_C(0) << 4)
//< rcc_pclk4 = rcc_hclk4
891
#define MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE_2 (UINT32_C(4) << 4)
//< rcc_pclk4 = rcc_hclk4 / 2
892
#define MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE_3 (UINT32_C(5) << 4)
//< rcc_pclk4 = rcc_hclk4 / 4
893
#define MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE_8 (UINT32_C(6) << 4)
//< rcc_pclk4 = rcc_hclk4 / 8
894
#define MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE_16 (UINT32_C(7) << 4)
//< rcc_pclk4 = rcc_hclk4 / 16
895
#define MCCI_STM32H7_REG_RCC_SRDCFGR_RSV0 (UINT32_C(0xF) << 0)
//< reserved, no change
896
/// @}
897
898
/// \name RCC_PLLCKSELR bits
899
/// @{
900
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_RSV26 (UINT32_C(0x3F) << 26)
//< reserved, no change
901
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM3 (UINT32_C(0x3F) << 20)
//< prescaler for PLL3
902
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM3_DIS (UINT32_C(0x3F) << 20)
//< prescaler disabled
903
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM3_N(n) ((n) << 20)
//< division by n
904
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_RSV18 (UINT32_C(3) << 18)
//< reserved, no change
905
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM2 (UINT32_C(0x3F) << 12)
//< prescaler for PLL2
906
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM2_DIS (UINT32_C(0x3F) << 12)
//< prescaler disabled
907
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM2_N(n) ((n) << 12)
//< division by n
908
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_RSV10 (UINT32_C(3) << 10)
//< reserved, no change
909
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM1 (UINT32_C(0x3F) << 14)
//< prescaler for PLL1
910
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM1_DIS (UINT32_C(0x3F) << 14)
//< prescaler disabled
911
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM1_N(n) ((n) << 14)
//< division by n
912
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_RSV2 (UINT32_C(3) << 2)
//< reserved, no change
913
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_PLLSRC (UINT32_C(3) << 0)
//< DIVMx and PLLs clock source selection
914
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_PLLSRC_HSI (UINT32_C(0) << 0)
//< HSI
915
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_PLLSRC_CSI (UINT32_C(1) << 0)
//< CSI
916
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_PLLSRC_HSE (UINT32_C(2) << 0)
//< HSE
917
/// @}
918
919
/// \name RCC_PLLCFGR bits
920
/// @{
921
#define MCCI_STM32H7_REG_RCC_PLLCFGR_RSV25 (UINT32_C(0x7F) << 25)
//< reserved, no change
922
#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVR3EN (UINT32_C(1) << 24)
//< PLL3 DIVR divider output enable
923
#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVQ3EN (UINT32_C(1) << 23)
//< PLL3 DIVQ divider output enable
924
#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVP3EN (UINT32_C(1) << 22)
//< PLL3 DIVP divider output enable
925
#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVR2EN (UINT32_C(1) << 21)
//< PLL2 DIVR divider output enable
926
#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVQ2EN (UINT32_C(1) << 20)
//< PLL2 DIVQ divider output enable
927
#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVP2EN (UINT32_C(1) << 19)
//< PLL2 DIVP divider output enable
928
#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVR1EN (UINT32_C(1) << 18)
//< PLL1 DIVR divider output enable
929
#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVQ1EN (UINT32_C(1) << 17)
//< PLL1 DIVQ divider output enable
930
#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVP1EN (UINT32_C(1) << 16)
//< PLL1 DIVP divider output enable
931
#define MCCI_STM32H7_REG_RCC_PLLCFGR_RSV12 (UINT32_C(0xF) << 12)
//< reserved, no change
932
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL3RGE (UINT32_C(3) << 10)
//< PLL3 input frequency range
933
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL3RGE_N(n) ((n) << 10)
//< PLL3 input frequency range
934
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL3VCOSEL (UINT32_C(1) << 9)
//< PLL3 VCO selection
935
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL3FRACEN (UINT32_C(1) << 8)
//< PLL3 fractional latch enable
936
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL2RGE (UINT32_C(3) << 6)
//< PLL2 input frequency range
937
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL2RGE_N(n) ((n) << 6)
//< PLL2 input frequency range
938
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL2VCOSEL (UINT32_C(1) << 5)
//< PLL2 VCO selection
939
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL2FRACEN (UINT32_C(1) << 4)
//< PLL2 fractional latch enable
940
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL1RGE (UINT32_C(3) << 2)
//< PLL1 input frequency range
941
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL1RGE_N(n) ((n) << 2)
//< PLL1 input frequency range
942
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL1VCOSEL (UINT32_C(1) << 1)
//< PLL1 VCO selection
943
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL1FRACEN (UINT32_C(1) << 0)
//< PLL1 fractional latch enable
944
/// @}
945
946
/// \name RCC_PLL1DIVR bits
947
/// @{
948
#define MCCI_STM32H7_REG_RCC_PLL1DIVR_RSV31 (UINT32_C(1) << 31)
//< reserved, no change
949
#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVR (UINT32_C(0x7F) << 24)
//< PLL1 DIVR division factor
950
#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVR_N(n) ((n) << 24)
//< pll1_r_ck = vco1_ck / (n+1)
951
#define MCCI_STM32H7_REG_RCC_PLL1DIVR_RSV23 (UINT32_C(1) << 23)
//< reserved, no change
952
#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVQ (UINT32_C(0x7F) << 16)
//< PLL1 DIVQ division factor
953
#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVQ_N(n) ((n) << 16)
//< pll1_q_ck = vco1_ck / (n+1)
954
#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVP (UINT32_C(0x7F) << 9)
//< PLL1 DIVP division factor
955
#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVP_N(n) ((n) << 9)
//< pll1_p_ck = vco1_ck / (n+1)
956
#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVN (UINT32_C(0x1FF) << 0)
//< multiplication factor for PLL1 VCO
957
#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVN_N(n) ((n) << 0)
//< DIVN = n+1
958
/// @}
959
960
/// \name RCC_PLL1FRACR bits
961
/// @{
962
#define MCCI_STM32H7_REG_RCC_PLL1FRACR_RSV16 UINT32_C(0xFFFF0000)
//< reserved, no change
963
#define MCCI_STM32H7_REG_RCC_PLL1FRACR_FRACN (UINT32_C(0x1FFF) << 3)
//< fractional part of the multiplication factor for PLL1 VCO
964
#define MCCI_STM32H7_REG_RCC_PLL1FRACR_FRACN_N(n) ((n) << 3)
//< fractional part of the multiplication factor for PLL1 VCO
965
#define MCCI_STM32H7_REG_RCC_PLL1FRACR_RSV0 (UINT32_C(7) << 0)
//< reserved, no change
966
/// @}
967
968
/// \name RCC_PLL2DIVR bits
969
/// @{
970
#define MCCI_STM32H7_REG_RCC_PLL2DIVR_RSV31 (UINT32_C(1) << 31)
//< reserved, no change
971
#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVR (UINT32_C(0x7F) << 24)
//< PLL2 DIVR division factor
972
#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVR_N(n) ((n) << 24)
//< pll2_r_ck = vco1_ck / (n+1)
973
#define MCCI_STM32H7_REG_RCC_PLL2DIVR_RSV23 (UINT32_C(1) << 23)
//< reserved, no change
974
#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVQ (UINT32_C(0x7F) << 16)
//< PLL2 DIVQ division factor
975
#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVQ_N(n) ((n) << 16)
//< pll2_q_ck = vco1_ck / (n+1)
976
#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVP (UINT32_C(0x7F) << 9)
//< PLL2 DIVP division factor
977
#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVP_N(n) ((n) << 9)
//< pll2_p_ck = vco1_ck / (n+1)
978
#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVN (UINT32_C(0x1FF) << 0)
//< multiplication factor for PLL2 VCO
979
#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVN_N(n) ((n) << 0)
//< DIVN = n+1
980
/// @}
981
982
/// \name RCC_PLL2FRACR bits
983
/// @{
984
#define MCCI_STM32H7_REG_RCC_PLL2FRACR_RSV16 UINT32_C(0xFFFF0000)
//< reserved, no change
985
#define MCCI_STM32H7_REG_RCC_PLL2FRACR_FRACN (UINT32_C(0x1FFF) << 3)
//< fractional part of the multiplication factor for PLL2 VCO
986
#define MCCI_STM32H7_REG_RCC_PLL2FRACR_FRACN_N(n) ((n) << 3)
//< fractional part of the multiplication factor for PLL2 VCO
987
#define MCCI_STM32H7_REG_RCC_PLL2FRACR_RSV0 (UINT32_C(7) << 0)
//< reserved, no change
988
/// @}
989
990
/// \name RCC_PLL3DIVR bits
991
/// @{
992
#define MCCI_STM32H7_REG_RCC_PLL3DIVR_RSV31 (UINT32_C(1) << 31)
//< reserved, no change
993
#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVR (UINT32_C(0x7F) << 24)
//< PLL3 DIVR division factor
994
#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVR_N(n) ((n) << 24)
//< pll3_r_ck = vco1_ck / (n+1)
995
#define MCCI_STM32H7_REG_RCC_PLL3DIVR_RSV23 (UINT32_C(1) << 23)
//< reserved, no change
996
#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVQ (UINT32_C(0x7F) << 16)
//< PLL3 DIVQ division factor
997
#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVQ_N(n) ((n) << 16)
//< pll3_q_ck = vco1_ck / (n+1)
998
#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVP (UINT32_C(0x7F) << 9)
//< PLL3 DIVP division factor
999
#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVP_N(n) ((n) << 9)
//< pll3_p_ck = vco1_ck / (n+1)
1000
#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVN (UINT32_C(0x1FF) << 0)
//< multiplication factor for PLL3 VCO
1001
#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVN_N(n) ((n) << 0)
//< DIVN = n+1
1002
/// @}
1003
1004
/// \name RCC_PLL3FRACR bits
1005
/// @{
1006
#define MCCI_STM32H7_REG_RCC_PLL3FRACR_RSV16 UINT32_C(0xFFFF0000)
//< reserved, no change
1007
#define MCCI_STM32H7_REG_RCC_PLL3FRACR_FRACN (UINT32_C(0x1FFF) << 3)
//< fractional part of the multiplication factor for PLL3 VCO
1008
#define MCCI_STM32H7_REG_RCC_PLL3FRACR_FRACN_N(n) ((n) << 3)
//< fractional part of the multiplication factor for PLL3 VCO
1009
#define MCCI_STM32H7_REG_RCC_PLL3FRACR_RSV0 (UINT32_C(7) << 0)
//< reserved, no change
1010
/// @}
1011
1012
/// \name RCC_CDCCIPR bits
1013
/// @{
1014
#define MCCI_STM32H7_REG_RCC_CDCCIPR_RSV30 (UINT32_C(3) << 30)
//< reserved, no change
1015
#define MCCI_STM32H7_REG_RCC_CDCCIPR_CKPERSEL (UINT32_C(3) << 28)
//< per_ck clock source selection
1016
#define MCCI_STM32H7_REG_RCC_CDCCIPR_CKPERSEL_HSI (UINT32_C(0) << 28)
//< hsi_ker_ck
1017
#define MCCI_STM32H7_REG_RCC_CDCCIPR_CKPERSEL_CSI (UINT32_C(1) << 28)
//< csi_ker_ck
1018
#define MCCI_STM32H7_REG_RCC_CDCCIPR_CKPERSEL_HSE (UINT32_C(2) << 28)
//< hse_ck
1019
#define MCCI_STM32H7_REG_RCC_CDCCIPR_RSV17 UINT32_C(0x0FFE0000)
//< reserved, no change
1020
#define MCCI_STM32H7_REG_RCC_CDCCIPR_SDMMCSEL (UINT32_C(1) << 16)
//< SDMMC kernel clock source selection
1021
#define MCCI_STM32H7_REG_RCC_CDCCIPR_RSV6 (UINT32_C(0x3F) << 6)
//< reserved, no change
1022
#define MCCI_STM32H7_REG_RCC_CDCCIPR_OCTOSPISEL (UINT32_C(3) << 4)
//< OCTOSPI kernel clock source selection
1023
#define MCCI_STM32H7_REG_RCC_CDCCIPR_OCTOSPISEL_HCLK3 (UINT32_C(0) << 4)
//< rcc_hclk3
1024
#define MCCI_STM32H7_REG_RCC_CDCCIPR_OCTOSPISEL_PLL1 (UINT32_C(1) << 4)
//< pll1_q_ck
1025
#define MCCI_STM32H7_REG_RCC_CDCCIPR_OCTOSPISEL_PLL2 (UINT32_C(2) << 4)
//< pll2_r_ck
1026
#define MCCI_STM32H7_REG_RCC_CDCCIPR_OCTOSPISEL_PER (UINT32_C(3) << 4)
//< per_ck
1027
#define MCCI_STM32H7_REG_RCC_CDCCIPR_RSV0 (UINT32_C(3) << 2)
//< reserved, no change
1028
#define MCCI_STM32H7_REG_RCC_CDCCIPR_FMCSEL (UINT32_C(3) << 0)
//< FMC kernel clock source selection
1029
#define MCCI_STM32H7_REG_RCC_CDCCIPR_FMCSEL_HCLK3 (UINT32_C(0) << 0)
//< rcc_hclk3
1030
#define MCCI_STM32H7_REG_RCC_CDCCIPR_FMCSEL_PLL1 (UINT32_C(1) << 0)
//< pll1_q_ck
1031
#define MCCI_STM32H7_REG_RCC_CDCCIPR_FMCSEL_PLL2 (UINT32_C(2) << 0)
//< pll2_r_ck
1032
#define MCCI_STM32H7_REG_RCC_CDCCIPR_FMCSEL_PER (UINT32_C(3) << 0)
//< per_ck
1033
/// @}
1034
1035
/// \name RCC_CDCCIP1R bits
1036
/// @{
1037
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SWPMISEL (UINT32_C(1) << 31)
//< SWPMI kernel clock source selection
1038
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV30 (UINT32_C(1) << 30)
//< reserved, no change
1039
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_FDCANSEL (UINT32_C(3) << 28)
//< FDCAN kernel clock source selection
1040
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_FDCANSEL_HSE (UINT32_C(0) << 28)
//< hse_ck
1041
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_FDCANSEL_PLL1 (UINT32_C(1) << 28)
//< pll1_q_ck
1042
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_FDCANSEL_PLL2 (UINT32_C(2) << 28)
//< pll2_r_ck
1043
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV25 (UINT32_C(7) << 25)
//< reserved, no change
1044
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_DFSDM1SEL (UINT32_C(1) << 24)
//< DFSDM1 kernel clock Clk source selection
1045
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV22 (UINT32_C(3) << 22)
//< reserved, no change
1046
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPDIFRXSEL (UINT32_C(3) << 20)
//< SPDIFRX kernel clock source selection
1047
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPDIFRXSEL_PLL1 (UINT32_C(0) << 20)
//< pll1_q_ck
1048
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPDIFRXSEL_PLL2 (UINT32_C(1) << 20)
//< pll2_r_ck
1049
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPDIFRXSEL_PLL3 (UINT32_C(2) << 20)
//< pll3_r_ck
1050
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPDIFRXSEL_HSI (UINT32_C(3) << 20)
//< hsi_ker_ck
1051
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV19 (UINT32_C(1) << 19)
//< reserved, no change
1052
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL (UINT32_C(7) << 16)
//< SPI4 and 5 kernel clock source selection
1053
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_PCLK2 (UINT32_C(0) << 16)
//< rcc_pclk2
1054
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_PLL2 (UINT32_C(1) << 16)
//< pll2_r_ck
1055
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_PLL3 (UINT32_C(2) << 16)
//< pll3_r_ck
1056
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_HSI (UINT32_C(3) << 16)
//< hsi_ker_ck
1057
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_CSI (UINT32_C(4) << 16)
//< csi_ker_ck
1058
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_HSE (UINT32_C(5) << 16)
//< hse_ck
1059
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV15 (UINT32_C(1) << 15)
//< reserved, no change
1060
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL (UINT32_C(7) << 12)
//< SPI/I2S1,2 and 3 kernel clock source selection
1061
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL_PLL1 (UINT32_C(0) << 12)
//< pll1_q_ck
1062
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL_PLL2 (UINT32_C(1) << 12)
//< pll2_r_ck
1063
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL_PLL3 (UINT32_C(2) << 12)
//< pll3_r_ck
1064
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL_I2S (UINT32_C(3) << 12)
//< I2S_CKIN
1065
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL_PER (UINT32_C(4) << 12)
//< per_ck
1066
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL (UINT32_C(7) << 9)
//< SAI2 kernel clock B source selection
1067
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_PLL1 (UINT32_C(0) << 9)
//< pll1_q_ck
1068
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_PLL2 (UINT32_C(1) << 9)
//< pll2_r_ck
1069
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_PLL3 (UINT32_C(2) << 9)
//< pll3_r_ck
1070
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_I2S (UINT32_C(3) << 9)
//< I2S_CKIN
1071
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_PER (UINT32_C(4) << 9)
//< per_ck
1072
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_SPDIFRX (UINT32_C(5) << 9)
//< spdifrx_symb_ck
1073
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL (UINT32_C(7) << 6)
//< SAI2 kernel clock source A selection
1074
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_PLL1 (UINT32_C(0) << 6)
//< pll1_q_ck
1075
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_PLL2 (UINT32_C(1) << 6)
//< pll2_r_ck
1076
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_PLL3 (UINT32_C(2) << 6)
//< pll3_r_ck
1077
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_I2S (UINT32_C(3) << 6)
//< I2S_CKIN
1078
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_PER (UINT32_C(4) << 6)
//< per_ck
1079
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_SPDIFRX (UINT32_C(5) << 6)
//< spdifrx_symb_ck
1080
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV3 (UINT32_C(7) << 3)
//< reserved, no change
1081
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL (UINT32_C(7) << 0)
//< SAI1 and DFSDM1 kernel Aclk clock source selection
1082
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL_PLL1 (UINT32_C(0) << 0)
//< pll1_q_ck
1083
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL_PLL2 (UINT32_C(1) << 0)
//< pll2_r_ck
1084
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL_PLL3 (UINT32_C(2) << 0)
//< pll3_r_ck
1085
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL_I2S (UINT32_C(3) << 0)
//< I2S_CKIN
1086
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL_PER (UINT32_C(4) << 0)
//< per_ck
1087
/// @}
1088
1089
/// \name RCC_CDCCIP2R bits
1090
/// @{
1091
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RSV31 (UINT32_C(1) << 31)
//< reserved, no change
1092
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL (UINT32_C(7) << 28)
//< LPTIM1 kernel clock source selection
1093
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_PCLK1 (UINT32_C(0) << 28)
//< rcc_pclk1
1094
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_PLL2 (UINT32_C(1) << 28)
//< pll2_r_ck
1095
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_PLL3 (UINT32_C(2) << 28)
//< pll3_r_ck
1096
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_LSE (UINT32_C(3) << 28)
//< lse_ck
1097
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_LSI (UINT32_C(4) << 28)
//< lsi_ck
1098
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_PER (UINT32_C(5) << 28)
//< per_ck
1099
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RSV24 (UINT32_C(0xF) << 24)
//< reserved, no change
1100
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_CECSEL (UINT32_C(3) << 22)
//< HDMI-CEC kernel clock source selection
1101
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_CECSEL_LSE (UINT32_C(0) << 22)
//< lse_ck
1102
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_CECSEL_LSI (UINT32_C(1) << 22)
//< lsi_ck
1103
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_CECSEL_CSI (UINT32_C(2) << 22)
//< csi_ker_ck
1104
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USBSEL (UINT32_C(3) << 20)
//< USBOTG 1 and 2 kernel clock source selection
1105
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USBSEL_DIS (UINT32_C(0) << 20)
//< disable
1106
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USBSEL_PLL1 (UINT32_C(1) << 20)
//< pll1_q_ck
1107
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USBSEL_PLL3 (UINT32_C(2) << 20)
//< pll3_r_ck
1108
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USBSEL_HSI48 (UINT32_C(3) << 20)
//< hsi48_ck
1109
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RSV14 (UINT32_C(0x3F) << 14)
//< reserved, no change
1110
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_I2C123SEL (UINT32_C(7) << 12)
//< I2C1,2,3 kernel clock source selection
1111
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_I2C123SEL_PCLK1 (UINT32_C(0) << 12)
//< rcc_pclk1
1112
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_I2C123SEL_PLL3 (UINT32_C(1) << 12)
//< pll3_r_ck
1113
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_I2C123SEL_HSI (UINT32_C(2) << 12)
//< hsi_ker_ck
1114
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_I2C123SEL_CSI (UINT32_C(3) << 12)
//< csi_ker_ck
1115
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RSV10 (UINT32_C(3) << 10)
//< reserved, no change
1116
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RNGSEL (UINT32_C(3) << 8)
//< RNG kernel clock source selection
1117
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RNGSEL_HSI48 (UINT32_C(0) << 8)
//< hsi48_ck
1118
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RNGSEL_PLL1 (UINT32_C(1) << 8)
//< pll1_q_ck
1119
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RNGSEL_LSE (UINT32_C(2) << 8)
//< lse_ck
1120
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RNGSEL_LSI (UINT32_C(3) << 8)
//< lsi_ck
1121
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RSV6 (UINT32_C(3) << 6)
//< reserved, no change
1122
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL (UINT32_C(7) << 3)
//< USART1, 6, 9 and 10 kernel clock source selection
1123
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_PCLK2 (UINT32_C(0) << 3)
//< rcc_pclk2
1124
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_PLL2 (UINT32_C(1) << 3)
//< pll2_r_ck
1125
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_PLL3 (UINT32_C(2) << 3)
//< pll3_r_ck
1126
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_HSI (UINT32_C(3) << 3)
//< hsi_ker_ck
1127
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_CSI (UINT32_C(4) << 3)
//< csi_ker_ck
1128
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_LSE (UINT32_C(5) << 3)
//< lse_ck
1129
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL (UINT32_C(7) << 0)
//< USART2/3, UART4,5, 7 and 8 (APB1) kernel clock source selection
1130
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_PCLK1 (UINT32_C(0) << 0)
//< rcc_pclk1
1131
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_PLL2 (UINT32_C(1) << 0)
//< pll2_r_ck
1132
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_PLL3 (UINT32_C(2) << 0)
//< pll3_r_ck
1133
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_HSI (UINT32_C(3) << 0)
//< hsi_ker_ck
1134
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_CSI (UINT32_C(4) << 0)
//< csi_ker_ck
1135
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_LSE (UINT32_C(5) << 0)
//< lse_ck
1136
/// @}
1137
1138
/// \name RCC_SRDCCIPR bits
1139
/// @{
1140
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_RSV31 (UINT32_C(1) << 31)
//< reserved, no change
1141
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL (UINT32_C(7) << 28)
//< SPI6 kernel clock source selection
1142
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_PCLK4 (UINT32_C(0) << 28)
//< rcc_pclk4
1143
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_PLL2 (UINT32_C(1) << 28)
//< pll2_r_ck
1144
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_PLL3 (UINT32_C(2) << 28)
//< pll3_r_ck
1145
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_HSI (UINT32_C(3) << 28)
//< hsi_ker_ck
1146
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_CSI (UINT32_C(4) << 28)
//< csi_ker_ck
1147
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_HSE (UINT32_C(5) << 28)
//< hse_ck
1148
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_I2S (UINT32_C(6) << 28)
//< I2S_CKIN
1149
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_DFSDM2SEL (UINT32_C(1) << 27)
//< DFSDM2 kernel Clk clock source selection
1150
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_RSV18 (UINT32_C(0x1FF) << 18)
//< reserved, no change
1151
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_ADCSEL (UINT32_C(3) << 16)
//< SAR ADC kernel clock source selection
1152
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_ADCSEL_PLL2 (UINT32_C(0) << 16)
//< pll2_r_ck
1153
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_ADCSEL_PLL3 (UINT32_C(1) << 16)
//< pll3_r_ck
1154
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_ADCSEL_PER (UINT32_C(2) << 16)
//< per_ck
1155
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL (UINT32_C(7) << 13)
//< LPTIM3 kernel clock source selection
1156
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_PCLK4 (UINT32_C(0) << 13)
//< rcc_pclk4
1157
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_PLL2 (UINT32_C(1) << 13)
//< pll2_r_ck
1158
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_PLL3 (UINT32_C(2) << 13)
//< pll3_r_ck
1159
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_LSE (UINT32_C(3) << 13)
//< lse_ck
1160
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_LSI (UINT32_C(4) << 13)
//< lsi_ck
1161
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_PER (UINT32_C(5) << 13)
//< per_ck
1162
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL (UINT32_C(7) << 10)
//< LPTIM2 kernel clock source selection
1163
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_PCLK4 (UINT32_C(0) << 10)
//< rcc_pclk4
1164
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_PLL2 (UINT32_C(1) << 10)
//< pll2_r_ck
1165
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_PLL3 (UINT32_C(2) << 10)
//< pll3_r_ck
1166
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_LSE (UINT32_C(3) << 10)
//< lse_ck
1167
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_LSI (UINT32_C(4) << 10)
//< lsi_ck
1168
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_PER (UINT32_C(5) << 10)
//< per_ck
1169
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_I2C4SEL (UINT32_C(3) << 8)
//< I2C4 kernel clock source selection
1170
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_I2C4SEL_PCLK4 (UINT32_C(0) << 8)
//< rcc_pclk4
1171
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_I2C4SEL_PLL3 (UINT32_C(1) << 8)
//< pll3_r_ck
1172
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_I2C4SEL_HSI (UINT32_C(2) << 8)
//< hsi_ker_ck
1173
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_I2C4SEL_CSI (UINT32_C(3) << 8)
//< csi_ker_ck
1174
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_RSV3 (UINT32_C(0x1F) << 3)
//< reserved, no change
1175
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL (UINT32_C(7) << 0)
//< LPUART1 kernel clock source selection
1176
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_PCLK4 (UINT32_C(0) << 0)
//< rcc_pclk4
1177
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_PLL2 (UINT32_C(1) << 0)
//< pll2_r_ck
1178
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_PLL3 (UINT32_C(2) << 0)
//< pll3_r_ck
1179
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_HSI (UINT32_C(3) << 0)
//< hsi_ker_ck
1180
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_CSI (UINT32_C(4) << 0)
//< csi_ker_ck
1181
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_LSE (UINT32_C(5) << 0)
//< lse_ck
1182
/// @}
1183
1184
/// \name RCC_CIER bits
1185
/// @{
1186
#define MCCI_STM32H7_REG_RCC_CIER_RSV10 UINT32_C(0xFFFFFC00)
//< reserved, no change
1187
#define MCCI_STM32H7_REG_RCC_CIER_LSECSSIE (UINT32_C(1) << 9)
//< LSE clock security system interrupt enable
1188
#define MCCI_STM32H7_REG_RCC_CIER_PLL3RDYIE (UINT32_C(1) << 8)
//< PLL3 ready interrupt enable
1189
#define MCCI_STM32H7_REG_RCC_CIER_PLL2RDYIE (UINT32_C(1) << 7)
//< PLL2 ready interrupt enable
1190
#define MCCI_STM32H7_REG_RCC_CIER_PLL1RDYIE (UINT32_C(1) << 6)
//< PLL1 ready interrupt enable
1191
#define MCCI_STM32H7_REG_RCC_CIER_HSI48RDYIE (UINT32_C(1) << 5)
//< HSI48 ready interrupt enable
1192
#define MCCI_STM32H7_REG_RCC_CIER_CSIRDYIE (UINT32_C(1) << 4)
//< CSI ready interrupt enable
1193
#define MCCI_STM32H7_REG_RCC_CIER_HSERDYIE (UINT32_C(1) << 3)
//< HSE ready interrupt enable
1194
#define MCCI_STM32H7_REG_RCC_CIER_HSIRDYIE (UINT32_C(1) << 2)
//< HSI ready interrupt enable
1195
#define MCCI_STM32H7_REG_RCC_CIER_LSERDYIE (UINT32_C(1) << 1)
//< LSE ready interrupt enable
1196
#define MCCI_STM32H7_REG_RCC_CIER_LSIRDYIE (UINT32_C(1) << 0)
//< LSI ready interrupt enable
1197
/// @}
1198
1199
/// \name RCC_CIFR bits
1200
/// @{
1201
#define MCCI_STM32H7_REG_RCC_CIFR_RSV11 UINT32_C(0xFFFFF800)
//< reserved, no change
1202
#define MCCI_STM32H7_REG_RCC_CIFR_HSECSSF (UINT32_C(1) << 10)
//< LSE clock security system interrupt flag
1203
#define MCCI_STM32H7_REG_RCC_CIFR_LSECSSF (UINT32_C(1) << 9)
//< LSE clock security system interrupt flag
1204
#define MCCI_STM32H7_REG_RCC_CIFR_PLL3RDYF (UINT32_C(1) << 8)
//< PLL3 ready interrupt flag
1205
#define MCCI_STM32H7_REG_RCC_CIFR_PLL2RDYF (UINT32_C(1) << 7)
//< PLL2 ready interrupt flag
1206
#define MCCI_STM32H7_REG_RCC_CIFR_PLL1RDYF (UINT32_C(1) << 6)
//< PLL1 ready interrupt flag
1207
#define MCCI_STM32H7_REG_RCC_CIFR_HSI48RDYF (UINT32_C(1) << 5)
//< HSI48 ready interrupt flag
1208
#define MCCI_STM32H7_REG_RCC_CIFR_CSIRDYF (UINT32_C(1) << 4)
//< CSI ready interrupt flag
1209
#define MCCI_STM32H7_REG_RCC_CIFR_HSERDYF (UINT32_C(1) << 3)
//< HSE ready interrupt flag
1210
#define MCCI_STM32H7_REG_RCC_CIFR_HSIRDYF (UINT32_C(1) << 2)
//< HSI ready interrupt flag
1211
#define MCCI_STM32H7_REG_RCC_CIFR_LSERDYF (UINT32_C(1) << 1)
//< LSE ready interrupt flag
1212
#define MCCI_STM32H7_REG_RCC_CIFR_LSIRDYF (UINT32_C(1) << 0)
//< LSI ready interrupt flag
1213
/// @}
1214
1215
/// \name RCC_CICR bits
1216
/// @{
1217
#define MCCI_STM32H7_REG_RCC_CICR_RSV11 UINT32_C(0xFFFFF800)
//< reserved, no change
1218
#define MCCI_STM32H7_REG_RCC_CICR_HSECSSC (UINT32_C(1) << 10)
//< LSE clock security system interrupt clear
1219
#define MCCI_STM32H7_REG_RCC_CICR_LSECSSC (UINT32_C(1) << 9)
//< LSE clock security system interrupt clear
1220
#define MCCI_STM32H7_REG_RCC_CICR_PLL3RDYC (UINT32_C(1) << 8)
//< PLL3 ready interrupt clear
1221
#define MCCI_STM32H7_REG_RCC_CICR_PLL2RDYC (UINT32_C(1) << 7)
//< PLL2 ready interrupt clear
1222
#define MCCI_STM32H7_REG_RCC_CICR_PLL1RDYC (UINT32_C(1) << 6)
//< PLL1 ready interrupt clear
1223
#define MCCI_STM32H7_REG_RCC_CICR_HSI48RDYC (UINT32_C(1) << 5)
//< HSI48 ready interrupt clear
1224
#define MCCI_STM32H7_REG_RCC_CICR_CSIRDYC (UINT32_C(1) << 4)
//< CSI ready interrupt clear
1225
#define MCCI_STM32H7_REG_RCC_CICR_HSERDYC (UINT32_C(1) << 3)
//< HSE ready interrupt clear
1226
#define MCCI_STM32H7_REG_RCC_CICR_HSIRDYC (UINT32_C(1) << 2)
//< HSI ready interrupt clear
1227
#define MCCI_STM32H7_REG_RCC_CICR_LSERDYC (UINT32_C(1) << 1)
//< LSE ready interrupt clear
1228
#define MCCI_STM32H7_REG_RCC_CICR_LSIRDYC (UINT32_C(1) << 0)
//< LSI ready interrupt clear
1229
/// @}
1230
1231
/// \name RCC_BDCR bits
1232
/// @{
1233
#define MCCI_STM32H7_REG_RCC_BDCR_RSV17 UINT32_C(0xFFFE0000)
//< reserved, don't change
1234
#define MCCI_STM32H7_REG_RCC_BDCR_VSWRST (UINT32_C(1) << 16)
//< VSwitch domain software reset
1235
#define MCCI_STM32H7_REG_RCC_BDCR_RTCEN (UINT32_C(1) << 15)
//< RTC clock enable
1236
#define MCCI_STM32H7_REG_RCC_BDCR_RSV10 (UINT32_C(0x1F) << 10)
//< reserved, don't change
1237
#define MCCI_STM32H7_REG_RCC_BDCR_RTCSEL (UINT32_C(3) << 8)
//< RTC clock source selection
1238
#define MCCI_STM32H7_REG_RCC_BDCR_RTCSEL_NO (UINT32_C(0) << 8)
//< no clock (default after Backup domain reset)
1239
#define MCCI_STM32H7_REG_RCC_BDCR_RTCSEL_LSE (UINT32_C(1) << 8)
//< LSE
1240
#define MCCI_STM32H7_REG_RCC_BDCR_RTCSEL_LSI (UINT32_C(2) << 8)
//< LSI
1241
#define MCCI_STM32H7_REG_RCC_BDCR_RTCSEL_HSE (UINT32_C(3) << 8)
//< HSE
1242
#define MCCI_STM32H7_REG_RCC_BDCR_LSEEXT (UINT32_C(1) << 7)
//< low-speed external clock type in Bypass mode
1243
#define MCCI_STM32H7_REG_RCC_BDCR_LSECSSD (UINT32_C(1) << 6)
//< LSE clock security system failure detection
1244
#define MCCI_STM32H7_REG_RCC_BDCR_LSECSSON (UINT32_C(1) << 5)
//< LSE clock security system enable
1245
#define MCCI_STM32H7_REG_RCC_BDCR_LSEDRV (UINT32_C(3) << 3)
//< LSE oscillator driving capability
1246
#define MCCI_STM32H7_REG_RCC_BDCR_LSEDRV_LOWEST (UINT32_C(0) << 3)
//< lowest drive (default after Backup domain reset)
1247
#define MCCI_STM32H7_REG_RCC_BDCR_LSEDRV_MEDLOW (UINT32_C(1) << 3)
//< medium-low drive
1248
#define MCCI_STM32H7_REG_RCC_BDCR_LSEDRV_MEDHI (UINT32_C(2) << 3)
//< medium-high drive
1249
#define MCCI_STM32H7_REG_RCC_BDCR_LSEDRV_HIEST (UINT32_C(3) << 3)
//< highest drive
1250
#define MCCI_STM32H7_REG_RCC_BDCR_LSEBYP (UINT32_C(1) << 2)
//< LSE oscillator bypass
1251
#define MCCI_STM32H7_REG_RCC_BDCR_LSERDY (UINT32_C(1) << 1)
//< LSE oscillator ready
1252
#define MCCI_STM32H7_REG_RCC_BDCR_LSEON (UINT32_C(1) << 0)
//< LSE oscillator enabled
1253
/// @}
1254
1255
/// \name RCC_CSR bits
1256
/// @{
1257
#define MCCI_STM32H7_REG_RCC_CSR_RSV2 UINT32_C(0xFFFFFFFC)
//< reserved, don't change
1258
#define MCCI_STM32H7_REG_RCC_CSR_LSIRDY (UINT32_C(1) << 1)
//< LSI oscillator ready
1259
#define MCCI_STM32H7_REG_RCC_CSR_LSION (UINT32_C(1) << 0)
//< LSI oscillator enable
1260
/// @}
1261
1262
/// \name RCC_AHB3RSTR bits
1263
/// @{
1264
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV25 (UINT32_C(0x7F) << 25)
//< reserved, don't change
1265
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_GFXMMURST (UINT32_C(1) << 24)
//< GFXMMU reset
1266
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_OTFD2RST (UINT32_C(1) << 23)
//< OTFD2 reset
1267
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_OTFD1RST (UINT32_C(1) << 22)
//< OTFD1 reset
1268
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_OCTOSPIMRST (UINT32_C(1) << 21)
//< OCTOSPIM reset
1269
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV20 (UINT32_C(1) << 20)
//< reserved, don't change
1270
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_OCTOSPI2RST (UINT32_C(1) << 19)
//< OCTOSPI2 and OCTOSPI2 delay block reset
1271
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV17 (UINT32_C(3) << 17)
//< reserved, don't change
1272
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_SDMMC1RST (UINT32_C(1) << 16)
//< SDMMC1 and SDMMC1 delay blocks reset
1273
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV15 (UINT32_C(1) << 15)
//< reserved, don't change
1274
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_OCTOSPI1RST (UINT32_C(1) << 14)
//< OCTOSPI1 and OCTOSPI1 delay blocks reset
1275
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV13 (UINT32_C(1) << 13)
//< reserved, don't change
1276
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_FMCRST (UINT32_C(1) << 12)
//< FMC block reset
1277
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV6 (UINT32_C(0x3F) << 6)
//< reserved, don't change
1278
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_JPGDECRST (UINT32_C(1) << 5)
//< JPGDEC block reset
1279
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_DMA2DRST (UINT32_C(1) << 4)
//< DMA2D block reset
1280
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV1 (UINT32_C(7) << 1)
//< reserved, don't change
1281
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_MDMARST (UINT32_C(1) << 0)
//< MDMA block reset
1282
/// @}
1283
1284
/// \name RCC_AHB1RSTR bits
1285
/// @{
1286
#define MCCI_STM32H7_REG_RCC_AHB1RSTR_RSV26 (UINT32_C(0x3F) << 26)
//< reserved, don't change
1287
#define MCCI_STM32H7_REG_RCC_AHB1RSTR_USB1OTGRST (UINT32_C(1) << 25)
//< USB1OTG block reset
1288
#define MCCI_STM32H7_REG_RCC_AHB1RSTR_RSV10 (UINT32_C(0x7FFF) << 10)
//< reserved, don't change
1289
#define MCCI_STM32H7_REG_RCC_AHB1RSTR_CRCRST (UINT32_C(1) << 9)
//< CRC block reset
1290
#define MCCI_STM32H7_REG_RCC_AHB1RSTR_RSV6 (UINT32_C(7) << 6)
//< reserved, don't change
1291
#define MCCI_STM32H7_REG_RCC_AHB1RSTR_ADC12RST (UINT32_C(1) << 5)
//< ADC1 and 2 blocks reset
1292
#define MCCI_STM32H7_REG_RCC_AHB1RSTR_RSV2 (UINT32_C(7) << 2)
//< reserved, don't change
1293
#define MCCI_STM32H7_REG_RCC_AHB1RSTR_DMA2RST (UINT32_C(1) << 1)
//< DMA2 and DMAMUX2 blocks reset
1294
#define MCCI_STM32H7_REG_RCC_AHB1RSTR_DMA1RST (UINT32_C(1) << 0)
//< DMA1 and DMAMUX1 blocks reset
1295
/// @}
1296
1297
/// \name RCC_AHB2RSTR bits
1298
/// @{
1299
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_RSV12 UINT32_C(0xFFFFF000)
//< reserved, don't change
1300
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_BDMA1RST (UINT32_C(1) << 11)
//< BDMA1 reset
1301
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_RSV10 (UINT32_C(1) << 10)
//< reserved, don't change
1302
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_SDMMC2RST (UINT32_C(1) << 9)
//< SDMMC2 and SDMMC2 delay blocks reset
1303
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_RSV7 (UINT32_C(3) << 7)
//< reserved, don't change
1304
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_RNGRST (UINT32_C(1) << 6)
//< random number generator block reset
1305
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_HASHRST (UINT32_C(1) << 5)
//< hash block reset
1306
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_CRYPTRST (UINT32_C(1) << 4)
//< cryptography block reset
1307
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_RSV3 (UINT32_C(1) << 3)
//< reserved, don't change
1308
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_HSEMRST (UINT32_C(1) << 2)
//< HSEM block reset
1309
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_RSV1 (UINT32_C(1) << 1)
//< reserved, don't change
1310
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_DCMIRST (UINT32_C(1) << 0)
//< digital camera interface block reset
1311
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_PSSIRST (UINT32_C(1) << 0)
//< PSSI block reset
1312
/// @}
1313
1314
/// \name RCC_AHB4RSTR bits
1315
/// @{
1316
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_RSV22 UINT32_C(0xFFC00000)
//< reserved, don't change
1317
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_BDMA2RST (UINT32_C(1) << 21)
//< SmartRun domain DMA and DMAMUX blocks reset
1318
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_RSV11 (UINT32_C(0x3FF) << 11)
//< reserved, don't change
1319
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOKRST (UINT32_C(1) << 10)
//< GPIOK block reset
1320
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOJRST (UINT32_C(1) << 9)
//< GPIOJ block reset
1321
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOIRST (UINT32_C(1) << 8)
//< GPIOI block reset
1322
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOHRST (UINT32_C(1) << 7)
//< GPIOH block reset
1323
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOGRST (UINT32_C(1) << 6)
//< GPIOG block reset
1324
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOFRST (UINT32_C(1) << 5)
//< GPIOF block reset
1325
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOERST (UINT32_C(1) << 4)
//< GPIOE block reset
1326
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIODRST (UINT32_C(1) << 3)
//< GPIOD block reset
1327
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOCRST (UINT32_C(1) << 2)
//< GPIOC block reset
1328
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOBRST (UINT32_C(1) << 1)
//< GPIOB block reset
1329
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOARST (UINT32_C(1) << 0)
//< GPIOA block reset
1330
/// @}
1331
1332
/// \name RCC_APB3RSTR bits
1333
/// @{
1334
#define MCCI_STM32H7_REG_RCC_APB3RSTR_RSV4 UINT32_C(0xFFFFFFF0)
///< reserved, don't change
1335
#define MCCI_STM32H7_REG_RCC_APB3RSTR_LTDCRST (UINT32_C(1) << 3)
///< LTDCRST block reset
1336
#define MCCI_STM32H7_REG_RCC_APB3RSTR_RSV0 (UINT32_C(7) << 0)
///< reserved, don't change
1337
/// @}
1338
1339
/// \name RCC_APB1LRSTR bits
1340
/// @{
1341
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_UART8RST (UINT32_C(1) << 31)
//< UART8 reset
1342
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_UART7RST (UINT32_C(1) << 30)
//< UART7 reset
1343
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_DAC1RST (UINT32_C(1) << 29)
//< DAC1 reset
1344
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_RSV28 (UINT32_C(1) << 28)
//< reserved, don't change
1345
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_CECRST (UINT32_C(1) << 27)
//< CEC reset
1346
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_RSV24 (UINT32_C(7) << 24)
//< reserved, don't change
1347
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_I2C3RST (UINT32_C(1) << 23)
//< I2C3 reset
1348
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_I2C2RST (UINT32_C(1) << 22)
//< I2C2 reset
1349
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_I2C1RST (UINT32_C(1) << 21)
//< I2C1 reset
1350
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_USART5RST (UINT32_C(1) << 20)
//< USART5 reset
1351
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_USART4RST (UINT32_C(1) << 19)
//< USART4 reset
1352
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_USART3RST (UINT32_C(1) << 18)
//< USART3 reset
1353
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_USART2RST (UINT32_C(1) << 17)
//< USART2 reset
1354
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_SPDIFRXRST (UINT32_C(1) << 16)
//< SPDIFRX reset
1355
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_SPI3RST (UINT32_C(1) << 15)
//< SPI3 reset
1356
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_SPI2RST (UINT32_C(1) << 14)
//< SPI2 reset
1357
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_RSV10 (UINT32_C(0xF) << 10)
//< reserved, don't change
1358
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_LPTIM1RST (UINT32_C(1) << 9)
//< LPTIM1 reset
1359
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM14RST (UINT32_C(1) << 8)
//< TIM14 reset
1360
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM13RST (UINT32_C(1) << 7)
//< TIM13 reset
1361
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM12RST (UINT32_C(1) << 6)
//< TIM12 reset
1362
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM7RST (UINT32_C(1) << 5)
//< TIM7 reset
1363
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM6RST (UINT32_C(1) << 4)
//< TIM6 reset
1364
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM5RST (UINT32_C(1) << 3)
//< TIM5 reset
1365
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM4RST (UINT32_C(1) << 2)
//< TIM4 reset
1366
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM3RST (UINT32_C(1) << 1)
//< TIM3 reset
1367
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM2RST (UINT32_C(1) << 0)
//< TIM2 reset
1368
/// @}
1369
1370
/// \name RCC_APB1HRSTR bits
1371
/// @{
1372
#define MCCI_STM32H7_REG_RCC_APB1HRSTR_RSV9 UINT32_C(0xFFFFFE00)
///< reserved, don't change
1373
#define MCCI_STM32H7_REG_RCC_APB1HRSTR_FDCANRST (UINT32_C(1) << 8)
//< FDCAN reset
1374
#define MCCI_STM32H7_REG_RCC_APB1HRSTR_RSV6 (UINT32_C(3) << 6)
//< reserved, don't change
1375
#define MCCI_STM32H7_REG_RCC_APB1HRSTR_MDIOSRST (UINT32_C(1) << 5)
//< MDIOS reset
1376
#define MCCI_STM32H7_REG_RCC_APB1HRSTR_OPAMPRST (UINT32_C(1) << 4)
//< OPAMP reset
1377
#define MCCI_STM32H7_REG_RCC_APB1HRSTR_RSV3 (UINT32_C(1) << 3)
//< reserved, don't change
1378
#define MCCI_STM32H7_REG_RCC_APB1HRSTR_SWPMIRST (UINT32_C(1) << 2)
//< SWPMI reset
1379
#define MCCI_STM32H7_REG_RCC_APB1HRSTR_CRSRST (UINT32_C(1) << 1)
//< CRS reset
1380
#define MCCI_STM32H7_REG_RCC_APB1HRSTR_RSV0 (UINT32_C(1) << 0)
//< reserved, don't change
1381
/// @}
1382
1383
/// \name RCC_APB2RSTR bits
1384
/// @{
1385
#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV31 (UINT32_C(1) << 31)
///< reserved, don't change
1386
#define MCCI_STM32H7_REG_RCC_APB2RSTR_DFSDM1RST (UINT32_C(1) << 30)
///< DFSDM1 reset
1387
#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV24 (UINT32_C(0x3F) << 24)
///< reserved, don't change
1388
#define MCCI_STM32H7_REG_RCC_APB2RSTR_SAI2RST (UINT32_C(1) << 23)
///< SAI2 reset
1389
#define MCCI_STM32H7_REG_RCC_APB2RSTR_SAI1RST (UINT32_C(1) << 22)
///< SAI1 reset
1390
#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV21 (UINT32_C(1) << 21)
///< reserved, don't change
1391
#define MCCI_STM32H7_REG_RCC_APB2RSTR_SPI5RST (UINT32_C(1) << 20)
///< SPI5 reset
1392
#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV19 (UINT32_C(1) << 19)
///< reserved, don't change
1393
#define MCCI_STM32H7_REG_RCC_APB2RSTR_TIM17RST (UINT32_C(1) << 18)
///< TIM17 reset
1394
#define MCCI_STM32H7_REG_RCC_APB2RSTR_TIM16RST (UINT32_C(1) << 17)
///< TIM16 reset
1395
#define MCCI_STM32H7_REG_RCC_APB2RSTR_TIM15RST (UINT32_C(1) << 16)
///< TIM15 reset
1396
#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV14 (UINT32_C(3) << 14)
///< reserved, don't change
1397
#define MCCI_STM32H7_REG_RCC_APB2RSTR_SPI4RST (UINT32_C(1) << 13)
///< SPI4 reset
1398
#define MCCI_STM32H7_REG_RCC_APB2RSTR_SPI1RST (UINT32_C(1) << 12)
///< SPI1 reset
1399
#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV8 (UINT32_C(0xF) << 8)
///< reserved, don't change
1400
#define MCCI_STM32H7_REG_RCC_APB2RSTR_USART10RST (UINT32_C(1) << 7)
///< USART10 reset
1401
#define MCCI_STM32H7_REG_RCC_APB2RSTR_UART9RST (UINT32_C(1) << 6)
///< UART9 reset
1402
#define MCCI_STM32H7_REG_RCC_APB2RSTR_USART6RST (UINT32_C(1) << 5)
///< USART6 reset
1403
#define MCCI_STM32H7_REG_RCC_APB2RSTR_USART1RST (UINT32_C(1) << 4)
///< USART1 reset
1404
#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV2 (UINT32_C(3) << 2)
///< reserved, don't change
1405
#define MCCI_STM32H7_REG_RCC_APB2RSTR_TIM8RST (UINT32_C(1) << 1)
///< TIM8 reset
1406
#define MCCI_STM32H7_REG_RCC_APB2RSTR_TIM1RST (UINT32_C(1) << 0)
///< TIM1 reset
1407
/// @}
1408
1409
/// \name RCC_APB4RSTR bits
1410
/// @{
1411
#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV28 (UINT32_C(0xF) << 28)
//< reserved, don't change
1412
#define MCCI_STM32H7_REG_RCC_APB4RSTR_DFSDM2RST (UINT32_C(1) << 27)
//< DFSDM2 reset
1413
#define MCCI_STM32H7_REG_RCC_APB4RSTR_DTSRST (UINT32_C(1) << 26)
//< DTS reset
1414
#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV16 (UINT32_C(0x3FF) << 16)
//< reserved, don't change
1415
#define MCCI_STM32H7_REG_RCC_APB4RSTR_VREFRST (UINT32_C(1) << 15)
//< VREF reset
1416
#define MCCI_STM32H7_REG_RCC_APB4RSTR_COMP12RST (UINT32_C(1) << 14)
//< COMP12 reset
1417
#define MCCI_STM32H7_REG_RCC_APB4RSTR_DAC2RST (UINT32_C(1) << 13)
//< DAC2 reset
1418
#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV11 (UINT32_C(3) << 11)
//< reserved, don't change
1419
#define MCCI_STM32H7_REG_RCC_APB4RSTR_LPTIM3RST (UINT32_C(1) << 10)
//< LPTIM3 reset
1420
#define MCCI_STM32H7_REG_RCC_APB4RSTR_LPTIM2RST (UINT32_C(1) << 9)
//< LPTIM2 reset
1421
#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV8 (UINT32_C(1) << 8)
//< reserved, don't change
1422
#define MCCI_STM32H7_REG_RCC_APB4RSTR_I2C4RST (UINT32_C(1) << 7)
//< I2C4 reset
1423
#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV6 (UINT32_C(1) << 6)
//< reserved, don't change
1424
#define MCCI_STM32H7_REG_RCC_APB4RSTR_SPI6RST (UINT32_C(1) << 5)
//< SPI6 reset
1425
#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV4 (UINT32_C(1) << 4)
//< reserved, don't change
1426
#define MCCI_STM32H7_REG_RCC_APB4RSTR_LPUART1RST (UINT32_C(1) << 3)
//< LPUART1 reset
1427
#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV2 (UINT32_C(1) << 2)
//< reserved, don't change
1428
#define MCCI_STM32H7_REG_RCC_APB4RSTR_SYSCFGRST (UINT32_C(1) << 1)
//< SYSCFG reset
1429
#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV0 (UINT32_C(1) << 0)
//< reserved, don't change
1430
/// @}
1431
1432
/// \name RCC_SRDAMR bits
1433
/// @{
1434
#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV25 (UINT32_C(3) << 30)
//< reserved, don't change
1435
#define MCCI_STM32H7_REG_RCC_SRDAMR_SRDSRAMAMEN (UINT32_C(1) << 29)
//< SmartRun domain SRAM Autonomous mode enable
1436
#define MCCI_STM32H7_REG_RCC_SRDAMR_BKPRAMAMEN (UINT32_C(1) << 28)
//< Backup RAM Autonomous mode enable
1437
#define MCCI_STM32H7_REG_RCC_SRDAMR_DFSDM2AMEN (UINT32_C(1) << 27)
//< DFSDM2 Autonomous mode enable
1438
#define MCCI_STM32H7_REG_RCC_SRDAMR_DTSAMEN (UINT32_C(1) << 26)
//< Digital temperature sensor Autonomous mode enable
1439
#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV17 (UINT32_C(0x1FF) << 17)
//< reserved, don't change
1440
#define MCCI_STM32H7_REG_RCC_SRDAMR_RTCAMEN (UINT32_C(1) << 16)
//< RTC Autonomous mode enable
1441
#define MCCI_STM32H7_REG_RCC_SRDAMR_VREFAMEN (UINT32_C(1) << 15)
//< VREF Autonomous mode enable
1442
#define MCCI_STM32H7_REG_RCC_SRDAMR_COMP12AMEN (UINT32_C(1) << 14)
//< COMP1 and 2 Autonomous mode enable
1443
#define MCCI_STM32H7_REG_RCC_SRDAMR_DAC2AMEN (UINT32_C(1) << 13)
//< DAC2 (containing one converter) Autonomous mode enable
1444
#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV11 (UINT32_C(3) << 11)
//< reserved, don't change
1445
#define MCCI_STM32H7_REG_RCC_SRDAMR_LPTIM3AMEN (UINT32_C(1) << 10)
//< LPTIM3 Autonomous mode enable
1446
#define MCCI_STM32H7_REG_RCC_SRDAMR_LPTIM2AMEN (UINT32_C(1) << 9)
//< LPTIM2 Autonomous mode enable
1447
#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV8 (UINT32_C(7) << 8)
//< reserved, don't change
1448
#define MCCI_STM32H7_REG_RCC_SRDAMR_I2C4AMEN (UINT32_C(1) << 7)
//< I2C4 Autonomous mode enable
1449
#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV6 (UINT32_C(1) << 6)
//< reserved, don't change
1450
#define MCCI_STM32H7_REG_RCC_SRDAMR_SPI6AMEN (UINT32_C(1) << 5)
//< SPI6 Autonomous mode enable
1451
#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV4 (UINT32_C(1) << 4)
//< reserved, don't change
1452
#define MCCI_STM32H7_REG_RCC_SRDAMR_LPUART1AMEN (UINT32_C(1) << 3)
//< LPUART1 Autonomous mode enable
1453
#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV2 (UINT32_C(1) << 2)
//< reserved, don't change
1454
#define MCCI_STM32H7_REG_RCC_SRDAMR_GPIOAMEN (UINT32_C(1) << 1)
//< GPIO Autonomous mode enable
1455
#define MCCI_STM32H7_REG_RCC_SRDAMR_BDMA2AMEN (UINT32_C(1) << 0)
//< SmartRun domain DMA and DMAMUX Autonomous mode enable
1456
/// @}
1457
1458
/// \name RCC_CKGAENR bits
1459
/// @{
1460
#define MCCI_STM32H7_REG_RCC_CKGAENR_JTAGCKG (UINT32_C(1) << 31)
//< JTAG automatic clock gating
1461
#define MCCI_STM32H7_REG_RCC_CKGAENR_EXTICKG (UINT32_C(1) << 30)
//< EXTI clock gating
1462
#define MCCI_STM32H7_REG_RCC_CKGAENR_ECCRAMCKG (UINT32_C(1) << 29)
//< RAM error code correction (ECC) clock gating
1463
#define MCCI_STM32H7_REG_RCC_CKGAENR_RSV18 UINT32_C(0x1FFC0000)
//< reserved, don't change
1464
#define MCCI_STM32H7_REG_RCC_CKGAENR_GFXMMUSCKG (UINT32_C(1) << 17)
//< AXI matrix slave GFXMMU clock gating
1465
#define MCCI_STM32H7_REG_RCC_CKGAENR_AXIRAM3CKG (UINT32_C(1) << 16)
//< AXI matrix slave SRAM3 clock gating
1466
#define MCCI_STM32H7_REG_RCC_CKGAENR_AXIRAM2CKG (UINT32_C(1) << 15)
//< AXI matrix slave SRAM2 clock gating
1467
#define MCCI_STM32H7_REG_RCC_CKGAENR_AXIRAM1CKG (UINT32_C(1) << 14)
//< AXI slave SRAM1 clock gating
1468
#define MCCI_STM32H7_REG_RCC_CKGAENR_OCTOSPI1CKG (UINT32_C(1) << 13)
//< AXI slave OCTOSPI1 clock gating
1469
#define MCCI_STM32H7_REG_RCC_CKGAENR_FMCCKG (UINT32_C(1) << 12)
//< AXI slave FMC clock gating
1470
#define MCCI_STM32H7_REG_RCC_CKGAENR_OCTOSPI2CKG (UINT32_C(1) << 11)
//< AXI slave OCTOSPI2 clock gating
1471
#define MCCI_STM32H7_REG_RCC_CKGAENR_FLIFTCKG (UINT32_C(1) << 10)
//< AXI slave Flash interface (FLIFT) clock gating
1472
#define MCCI_STM32H7_REG_RCC_CKGAENR_AHB34CKG (UINT32_C(1) << 9)
//< AXI slave AHB34 clock gating
1473
#define MCCI_STM32H7_REG_RCC_CKGAENR_AHB12CKG (UINT32_C(1) << 8)
//< AXI slave AHB12 clock gating
1474
#define MCCI_STM32H7_REG_RCC_CKGAENR_GFXMMUMCKG (UINT32_C(1) << 7)
//< AXI master GFXMMU clock gating
1475
#define MCCI_STM32H7_REG_RCC_CKGAENR_LTDCCKG (UINT32_C(1) << 6)
//< AXI master LTDC clock gating
1476
#define MCCI_STM32H7_REG_RCC_CKGAENR_DMA2DCKG (UINT32_C(1) << 5)
//< AXI master DMA2D clock gating
1477
#define MCCI_STM32H7_REG_RCC_CKGAENR_MDMACKG (UINT32_C(1) << 4)
//< AXI master MDMA clock gating
1478
#define MCCI_STM32H7_REG_RCC_CKGAENR_SDMMCCKG (UINT32_C(1) << 3)
//< AXI master SDMMC clock gating
1479
#define MCCI_STM32H7_REG_RCC_CKGAENR_CPUCKG (UINT32_C(1) << 2)
//< AXI master CPU clock gating
1480
#define MCCI_STM32H7_REG_RCC_CKGAENR_AHBCKG (UINT32_C(1) << 1)
//< AXI master AHB clock gating
1481
#define MCCI_STM32H7_REG_RCC_CKGAENR_AXICKG (UINT32_C(1) << 0)
//< AXI interconnect matrix clock gating
1482
/// @}
1483
1484
/// \name RCC_RSR bits
1485
/// @{
1486
#define MCCI_STM32H7_REG_RCC_RSR_RSV31 (UINT32_C(1) << 31)
//< reserved, don't change
1487
#define MCCI_STM32H7_REG_RCC_RSR_LPWRRSTF (UINT32_C(1) << 30)
//< reset due to illegal CD DStop or CD DStop2 or CPU CStop flag
1488
#define MCCI_STM32H7_REG_RCC_RSR_RSV29 (UINT32_C(1) << 29)
//< reserved, don't change
1489
#define MCCI_STM32H7_REG_RCC_RSR_WWDGRSTF (UINT32_C(1) << 28)
//< window watchdog reset flag
1490
#define MCCI_STM32H7_REG_RCC_RSR_RSV27 (UINT32_C(1) << 27)
//< reserved, don't change
1491
#define MCCI_STM32H7_REG_RCC_RSR_IWDGRSTF (UINT32_C(1) << 26)
//< independent watchdog reset flag
1492
#define MCCI_STM32H7_REG_RCC_RSR_RSV25 (UINT32_C(1) << 25)
//< reserved, don't change
1493
#define MCCI_STM32H7_REG_RCC_RSR_SFTRSTF (UINT32_C(1) << 24)
//< system reset from CPU reset flag
1494
#define MCCI_STM32H7_REG_RCC_RSR_PORRSTF (UINT32_C(1) << 23)
//< POR/PDR reset flag
1495
#define MCCI_STM32H7_REG_RCC_RSR_PINRSTF (UINT32_C(1) << 22)
//< pin reset flag (NRST)
1496
#define MCCI_STM32H7_REG_RCC_RSR_BORRSTF (UINT32_C(1) << 21)
//< BOR reset flag
1497
#define MCCI_STM32H7_REG_RCC_RSR_RSV20 (UINT32_C(1) << 20)
//< reserved, don't change
1498
#define MCCI_STM32H7_REG_RCC_RSR_CDRSTF (UINT32_C(1) << 19)
//< CPU domain power-switch reset flag
1499
#define MCCI_STM32H7_REG_RCC_RSR_RSV18 (UINT32_C(3) << 18)
//< reserved, don't change
1500
#define MCCI_STM32H7_REG_RCC_RSR_RMVF (UINT32_C(1) << 16)
//< remove reset flag
1501
#define MCCI_STM32H7_REG_RCC_RSR_RSV0 UINT32_C(0x0000FFFF)
//< reserved, don't change
1502
/// @}
1503
1504
/// \name RCC_AHB3ENR bits
1505
/// @{
1506
#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV25 (UINT32_C(0x7F) << 25)
//< reserved, don't change
1507
#define MCCI_STM32H7_REG_RCC_AHB3ENR_GFXMMUEN (UINT32_C(1) << 24)
//< GFXMMU clock enable
1508
#define MCCI_STM32H7_REG_RCC_AHB3ENR_OTFD2EN (UINT32_C(1) << 23)
//< OTFD2 clock enable
1509
#define MCCI_STM32H7_REG_RCC_AHB3ENR_OTFD1EN (UINT32_C(1) << 22)
//< OTFD1 clock enable
1510
#define MCCI_STM32H7_REG_RCC_AHB3ENR_OCTOSPIMEN (UINT32_C(1) << 21)
//< OCTOSPIM clock enable
1511
#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV20 (UINT32_C(1) << 20)
//< reserved, don't change
1512
#define MCCI_STM32H7_REG_RCC_AHB3ENR_OCTOSPI2EN (UINT32_C(1) << 19)
//< OCTOSPI2 clock enable
1513
#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV17 (UINT32_C(3) << 17)
//< reserved, don't change
1514
#define MCCI_STM32H7_REG_RCC_AHB3ENR_SDMMC1EN (UINT32_C(1) << 16)
//< SDMMC1 and SDMMC1 delay clock enable
1515
#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV15 (UINT32_C(1) << 15)
//< reserved, don't change
1516
#define MCCI_STM32H7_REG_RCC_AHB3ENR_OCTOSPI1EN (UINT32_C(1) << 14)
//< OCTOSPI1 and OCTOSPI1 delay clock enable
1517
#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV13 (UINT32_C(1) << 13)
//< reserved, don't change
1518
#define MCCI_STM32H7_REG_RCC_AHB3ENR_FMCEN (UINT32_C(1) << 12)
//< FMC peripheral clocks enable
1519
#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV6 (UINT32_C(0x3F) << 6)
//< reserved, don't change
1520
#define MCCI_STM32H7_REG_RCC_AHB3ENR_JPGDECEN (UINT32_C(1) << 5)
//< JPGDEC peripheral clock enable
1521
#define MCCI_STM32H7_REG_RCC_AHB3ENR_DMA2DEN (UINT32_C(1) << 4)
//< DMA2D peripheral clock enable
1522
#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV1 (UINT32_C(7) << 1)
//< reserved, don't change
1523
#define MCCI_STM32H7_REG_RCC_AHB3ENR_MDMAEN (UINT32_C(1) << 0)
//< MDMA peripheral clock enable
1524
/// @}
1525
1526
/// \name RCC_AHB1ENR bits
1527
/// @{
1528
#define MCCI_STM32H7_REG_RCC_AHB1ENR_RSV27 (UINT32_C(0x1F) << 27)
//< reserved, don't change
1529
#define MCCI_STM32H7_REG_RCC_AHB1ENR_USB1ULPIEN (UINT32_C(1) << 26)
//< USB_PHY1 clocks enable
1530
#define MCCI_STM32H7_REG_RCC_AHB1ENR_USB1OTGEN (UINT32_C(1) << 25)
//< USB1OTG peripheral clocks enable
1531
#define MCCI_STM32H7_REG_RCC_AHB1ENR_RSV10 (UINT32_C(0x7FFF) << 10)
//< reserved, don't change
1532
#define MCCI_STM32H7_REG_RCC_AHB1ENR_CRCEN (UINT32_C(1) << 9)
//< CRC peripheral clock enable
1533
#define MCCI_STM32H7_REG_RCC_AHB1ENR_RSV6 (UINT32_C(7) << 6)
//< reserved, don't change
1534
#define MCCI_STM32H7_REG_RCC_AHB1ENR_ADC12EN (UINT32_C(1) << 5)
//< ADC1 and 2 peripheral clocks enable
1535
#define MCCI_STM32H7_REG_RCC_AHB1ENR_RSV2 (UINT32_C(7) << 2)
//< reserved, don't change
1536
#define MCCI_STM32H7_REG_RCC_AHB1ENR_DMA2EN (UINT32_C(1) << 1)
//< DMA2 clock enable
1537
#define MCCI_STM32H7_REG_RCC_AHB1ENR_DMA1EN (UINT32_C(1) << 0)
//< DMA1 clock enable
1538
/// @}
1539
1540
/// \name RCC_AHB2ENR bits
1541
/// @{
1542
#define MCCI_STM32H7_REG_RCC_AHB2ENR_RSV31 (UINT32_C(1) << 31)
//< reserved, don't change
1543
#define MCCI_STM32H7_REG_RCC_AHB2ENR_AHBSRAM2EN (UINT32_C(1) << 30)
//< AHBSRAM2 block enable
1544
#define MCCI_STM32H7_REG_RCC_AHB2ENR_AHBSRAM1EN (UINT32_C(1) << 29)
//< AHBSRAM1 block enable
1545
#define MCCI_STM32H7_REG_RCC_AHB2ENR_RSV12 (UINT32_C(0x1FFFF) << 12)
//< reserved, don't change
1546
#define MCCI_STM32H7_REG_RCC_AHB2ENR_BDMA1EN (UINT32_C(1) << 11)
//< DMA clock enable (DFSDM dedicated DMA)
1547
#define MCCI_STM32H7_REG_RCC_AHB2ENR_RSV10 (UINT32_C(1) << 10)
//< reserved, don't change
1548
#define MCCI_STM32H7_REG_RCC_AHB2ENR_SDMMC2EN (UINT32_C(1) << 9)
//< SDMMC2 and SDMMC2 delay clock enable
1549
#define MCCI_STM32H7_REG_RCC_AHB2ENR_RSV7 (UINT32_C(3) << 7)
//< reserved, don't change
1550
#define MCCI_STM32H7_REG_RCC_AHB2ENR_RNGEN (UINT32_C(1) << 6)
//< RNG peripheral clocks enable
1551
#define MCCI_STM32H7_REG_RCC_AHB2ENR_HASHEN (UINT32_C(1) << 5)
//< HASH peripheral clock enable
1552
#define MCCI_STM32H7_REG_RCC_AHB2ENR_CRYPTEN (UINT32_C(1) << 4)
//< CRYPT peripheral clock enable
1553
#define MCCI_STM32H7_REG_RCC_AHB2ENR_RSV3 (UINT32_C(1) << 3)
//< reserved, don't change
1554
#define MCCI_STM32H7_REG_RCC_AHB2ENR_HSEMEN (UINT32_C(1) << 2)
//< HSEM peripheral clock enable
1555
#define MCCI_STM32H7_REG_RCC_AHB2ENR_RSV1 (UINT32_C(1) << 1)
//< reserved, don't change
1556
#define MCCI_STM32H7_REG_RCC_AHB2ENR_DCMIEN (UINT32_C(1) << 0)
//< digital camera interface peripheral clock enable
1557
#define MCCI_STM32H7_REG_RCC_AHB2ENR_PSSIEN (UINT32_C(1) << 0)
//< PSSI peripheral clock enable
1558
/// @}
1559
1560
/// \name RCC_AHB4ENR bits
1561
/// @{
1562
#define MCCI_STM32H7_REG_RCC_AHB4ENR_RSV30 (UINT32_C(3) << 30)
//< reserved, don't change
1563
#define MCCI_STM32H7_REG_RCC_AHB4ENR_SRDSRAMEN (UINT32_C(1) << 29)
//< SRDSRAM enable
1564
#define MCCI_STM32H7_REG_RCC_AHB4ENR_BKPRAMEN (UINT32_C(1) << 28)
//< BKPRAM enable
1565
#define MCCI_STM32H7_REG_RCC_AHB4ENR_RSV22 (UINT32_C(0x3F) << 22)
//< reserved, don't change
1566
#define MCCI_STM32H7_REG_RCC_AHB4ENR_BDMA2EN (UINT32_C(1) << 21)
//< BDMA2 enable
1567
#define MCCI_STM32H7_REG_RCC_AHB4ENR_RSV11 (UINT32_C(0x3FF) << 11)
//< reserved, don't change
1568
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOKEN (UINT32_C(1) << 10)
//< GPIOK enable
1569
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOJEN (UINT32_C(1) << 9)
//< GPIOJ enable
1570
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOIEN (UINT32_C(1) << 8)
//< GPIOI enable
1571
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOHEN (UINT32_C(1) << 7)
//< GPIOH enable
1572
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOGEN (UINT32_C(1) << 6)
//< GPIOG enable
1573
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOFEN (UINT32_C(1) << 5)
//< GPIOF enable
1574
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOEEN (UINT32_C(1) << 4)
//< GPIOE enable
1575
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIODEN (UINT32_C(1) << 3)
//< GPIOD enable
1576
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOCEN (UINT32_C(1) << 2)
//< GPIOC enable
1577
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOBEN (UINT32_C(1) << 1)
//< GPIOB enable
1578
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOAEN (UINT32_C(1) << 0)
//< GPIOA enable
1579
/// @}
1580
1581
/// \name RCC_APB3ENR bits
1582
/// @{
1583
#define MCCI_STM32H7_REG_RCC_APB3ENR_RSV7 UINT32_C(0xFFFFFF80)
//< reserved, don't change
1584
#define MCCI_STM32H7_REG_RCC_APB3ENR_WWDGEN (UINT32_C(1) << 26)
//< WWDG enable
1585
#define MCCI_STM32H7_REG_RCC_APB3ENR_RSV4 (UINT32_C(3) << 4)
//< reserved, don't change
1586
#define MCCI_STM32H7_REG_RCC_APB3ENR_LTDCEN (UINT32_C(1) << 25)
//< LTDC enable
1587
#define MCCI_STM32H7_REG_RCC_APB3ENR_RSV0 (UINT32_C(7) << 0)
//< reserved, don't change
1588
/// @}
1589
1590
/// \name RCC_APB1LENR bits
1591
/// @{
1592
#define MCCI_STM32H7_REG_RCC_APB1LENR_UART8EN (UINT32_C(1) << 31)
//< UART8 clock enable
1593
#define MCCI_STM32H7_REG_RCC_APB1LENR_UART7EN (UINT32_C(1) << 30)
//< UART7 clock enable
1594
#define MCCI_STM32H7_REG_RCC_APB1LENR_DAC1EN (UINT32_C(1) << 29)
//< DAC1 clock enable
1595
#define MCCI_STM32H7_REG_RCC_APB1LENR_RSV28 (UINT32_C(1) << 28)
//< reserved, don't change
1596
#define MCCI_STM32H7_REG_RCC_APB1LENR_CECEN (UINT32_C(1) << 27)
//< CEC clock enable
1597
#define MCCI_STM32H7_REG_RCC_APB1LENR_RSV24 (UINT32_C(7) << 24)
//< reserved, don't change
1598
#define MCCI_STM32H7_REG_RCC_APB1LENR_I2C3EN (UINT32_C(1) << 23)
//< I2C3 clock enable
1599
#define MCCI_STM32H7_REG_RCC_APB1LENR_I2C2EN (UINT32_C(1) << 22)
//< I2C2 clock enable
1600
#define MCCI_STM32H7_REG_RCC_APB1LENR_I2C1EN (UINT32_C(1) << 21)
//< I2C1 clock enable
1601
#define MCCI_STM32H7_REG_RCC_APB1LENR_USART5EN (UINT32_C(1) << 20)
//< USART5 clock enable
1602
#define MCCI_STM32H7_REG_RCC_APB1LENR_USART4EN (UINT32_C(1) << 19)
//< USART4 clock enable
1603
#define MCCI_STM32H7_REG_RCC_APB1LENR_USART3EN (UINT32_C(1) << 18)
//< USART3 clock enable
1604
#define MCCI_STM32H7_REG_RCC_APB1LENR_USART2EN (UINT32_C(1) << 17)
//< USART2 clock enable
1605
#define MCCI_STM32H7_REG_RCC_APB1LENR_SPDIFRXEN (UINT32_C(1) << 16)
//< SPDIFRX clock enable
1606
#define MCCI_STM32H7_REG_RCC_APB1LENR_SPI3EN (UINT32_C(1) << 15)
//< SPI3 clock enable
1607
#define MCCI_STM32H7_REG_RCC_APB1LENR_SPI2EN (UINT32_C(1) << 14)
//< SPI2 clock enable
1608
#define MCCI_STM32H7_REG_RCC_APB1LENR_RSV10 (UINT32_C(0xF) << 10)
//< reserved, don't change
1609
#define MCCI_STM32H7_REG_RCC_APB1LENR_LPTIM1EN (UINT32_C(1) << 9)
//< LPTIM1 clock enable
1610
#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM14EN (UINT32_C(1) << 8)
//< TIM14 clock enable
1611
#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM13EN (UINT32_C(1) << 7)
//< TIM13 clock enable
1612
#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM12EN (UINT32_C(1) << 6)
//< TIM12 clock enable
1613
#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM7EN (UINT32_C(1) << 5)
//< TIM7 clock enable
1614
#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM6EN (UINT32_C(1) << 4)
//< TIM6 clock enable
1615
#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM5EN (UINT32_C(1) << 3)
//< TIM5 clock enable
1616
#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM4EN (UINT32_C(1) << 2)
//< TIM4 clock enable
1617
#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM3EN (UINT32_C(1) << 1)
//< TIM3 clock enable
1618
#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM2EN (UINT32_C(1) << 0)
//< TIM2 clock enable
1619
/// @}
1620
1621
/// \name RCC_APB1HENR bits
1622
/// @{
1623
#define MCCI_STM32H7_REG_RCC_APB1HENR_RSV9 UINT32_C(0xFFFFFE00)
///< reserved, don't change
1624
#define MCCI_STM32H7_REG_RCC_APB1HENR_FDCANEN (UINT32_C(1) << 8)
//< FDCAN clock enable
1625
#define MCCI_STM32H7_REG_RCC_APB1HENR_RSV6 (UINT32_C(3) << 6)
//< reserved, don't change
1626
#define MCCI_STM32H7_REG_RCC_APB1HENR_MDIOSEN (UINT32_C(1) << 5)
//< MDIOS clock enable
1627
#define MCCI_STM32H7_REG_RCC_APB1HENR_OPAMPEN (UINT32_C(1) << 4)
//< OPAMP clock enable
1628
#define MCCI_STM32H7_REG_RCC_APB1HENR_RSV3 (UINT32_C(1) << 3)
//< reserved, don't change
1629
#define MCCI_STM32H7_REG_RCC_APB1HENR_SWPMIEN (UINT32_C(1) << 2)
//< SWPMI clock enable
1630
#define MCCI_STM32H7_REG_RCC_APB1HENR_CRSEN (UINT32_C(1) << 1)
//< CRS clock enable
1631
#define MCCI_STM32H7_REG_RCC_APB1HENR_RSV0 (UINT32_C(1) << 0)
//< reserved, don't change
1632
/// @}
1633
1634
/// \name RCC_APB2ENR bits
1635
/// @{
1636
#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV31 (UINT32_C(1) << 31)
///< reserved, don't change
1637
#define MCCI_STM32H7_REG_RCC_APB2ENR_DFSDM1EN (UINT32_C(1) << 30)
///< DFSDM1 clock enable
1638
#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV24 (UINT32_C(0x3F) << 24)
///< reserved, don't change
1639
#define MCCI_STM32H7_REG_RCC_APB2ENR_SAI2EN (UINT32_C(1) << 23)
///< SAI2 clock enable
1640
#define MCCI_STM32H7_REG_RCC_APB2ENR_SAI1EN (UINT32_C(1) << 22)
///< SAI1 clock enable
1641
#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV21 (UINT32_C(1) << 21)
///< reserved, don't change
1642
#define MCCI_STM32H7_REG_RCC_APB2ENR_SPI5EN (UINT32_C(1) << 20)
///< SPI5 clock enable
1643
#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV19 (UINT32_C(1) << 19)
///< reserved, don't change
1644
#define MCCI_STM32H7_REG_RCC_APB2ENR_TIM17EN (UINT32_C(1) << 18)
///< TIM17 clock enable
1645
#define MCCI_STM32H7_REG_RCC_APB2ENR_TIM16EN (UINT32_C(1) << 17)
///< TIM16 clock enable
1646
#define MCCI_STM32H7_REG_RCC_APB2ENR_TIM15EN (UINT32_C(1) << 16)
///< TIM15 clock enable
1647
#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV14 (UINT32_C(3) << 14)
///< reserved, don't change
1648
#define MCCI_STM32H7_REG_RCC_APB2ENR_SPI4EN (UINT32_C(1) << 13)
///< SPI4 clock enable
1649
#define MCCI_STM32H7_REG_RCC_APB2ENR_SPI1EN (UINT32_C(1) << 12)
///< SPI1 clock enable
1650
#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV8 (UINT32_C(0xF) << 8)
///< reserved, don't change
1651
#define MCCI_STM32H7_REG_RCC_APB2ENR_USART10EN (UINT32_C(1) << 7)
///< USART10 clock enable
1652
#define MCCI_STM32H7_REG_RCC_APB2ENR_UART9EN (UINT32_C(1) << 6)
///< UART9 clock enable
1653
#define MCCI_STM32H7_REG_RCC_APB2ENR_USART6EN (UINT32_C(1) << 5)
///< USART6 clock enable
1654
#define MCCI_STM32H7_REG_RCC_APB2ENR_USART1EN (UINT32_C(1) << 4)
///< USART1 clock enable
1655
#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV2 (UINT32_C(3) << 2)
///< reserved, don't change
1656
#define MCCI_STM32H7_REG_RCC_APB2ENR_TIM8EN (UINT32_C(1) << 1)
///< TIM8 clock enable
1657
#define MCCI_STM32H7_REG_RCC_APB2ENR_TIM1EN (UINT32_C(1) << 0)
///< TIM1 clock enable
1658
/// @}
1659
1660
/// \name RCC_APB4ENR bits
1661
/// @{
1662
#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV28 (UINT32_C(0xF) << 28)
//< reserved, don't change
1663
#define MCCI_STM32H7_REG_RCC_APB4ENR_DFSDM2EN (UINT32_C(1) << 27)
//< DFSDM2 clock enable
1664
#define MCCI_STM32H7_REG_RCC_APB4ENR_DTSEN (UINT32_C(1) << 26)
//< DTS clock enable
1665
#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV17 (UINT32_C(0x1FF) << 17)
//< reserved, don't change
1666
#define MCCI_STM32H7_REG_RCC_APB4ENR_RTCAPBEN (UINT32_C(1) << 16)
//< RTCAPB clock enable
1667
#define MCCI_STM32H7_REG_RCC_APB4ENR_VREFEN (UINT32_C(1) << 15)
//< VREF clock enable
1668
#define MCCI_STM32H7_REG_RCC_APB4ENR_COMP12EN (UINT32_C(1) << 14)
//< COMP12 clock enable
1669
#define MCCI_STM32H7_REG_RCC_APB4ENR_DAC2EN (UINT32_C(1) << 13)
//< DAC2 clock enable
1670
#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV11 (UINT32_C(3) << 11)
//< reserved, don't change
1671
#define MCCI_STM32H7_REG_RCC_APB4ENR_LPTIM3EN (UINT32_C(1) << 10)
//< LPTIM3 clock enable
1672
#define MCCI_STM32H7_REG_RCC_APB4ENR_LPTIM2EN (UINT32_C(1) << 9)
//< LPTIM2 clock enable
1673
#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV8 (UINT32_C(1) << 8)
//< reserved, don't change
1674
#define MCCI_STM32H7_REG_RCC_APB4ENR_I2C4EN (UINT32_C(1) << 7)
//< I2C4 clock enable
1675
#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV6 (UINT32_C(1) << 6)
//< reserved, don't change
1676
#define MCCI_STM32H7_REG_RCC_APB4ENR_SPI6EN (UINT32_C(1) << 5)
//< SPI6 clock enable
1677
#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV4 (UINT32_C(1) << 4)
//< reserved, don't change
1678
#define MCCI_STM32H7_REG_RCC_APB4ENR_LPUART1EN (UINT32_C(1) << 3)
//< LPUART1 clock enable
1679
#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV2 (UINT32_C(1) << 2)
//< reserved, don't change
1680
#define MCCI_STM32H7_REG_RCC_APB4ENR_SYSCFGEN (UINT32_C(1) << 1)
//< SYSCFG clock enable
1681
#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV0 (UINT32_C(1) << 0)
//< reserved, don't change
1682
/// @}
1683
1684
/// \name RCC_AHB3LPENR bits
1685
/// @{
1686
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_AXISRAM1LPEN (UINT32_C(1) << 31)
//< GFXMMU clock enable
1687
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_ITCMLPEN (UINT32_C(1) << 30)
//< GFXMMU clock enable
1688
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_DTCM2LPEN (UINT32_C(1) << 29)
//< GFXMMU clock enable
1689
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_DTCM1LPEN (UINT32_C(1) << 28)
//< GFXMMU clock enable
1690
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_AXISRAM3LPEN (UINT32_C(1) << 27)
//< GFXMMU clock enable
1691
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_AXISRAM2LPEN (UINT32_C(1) << 26)
//< GFXMMU clock enable
1692
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV25 (UINT32_C(1) << 25)
//< reserved, don't change
1693
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_GFXMMULPEN (UINT32_C(1) << 24)
//< GFXMMU clock enable
1694
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_OTFD2LPEN (UINT32_C(1) << 23)
//< OTFD2 clock enable
1695
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_OTFD1LPEN (UINT32_C(1) << 22)
//< OTFD1 clock enable
1696
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_OCTOSPIMLPEN (UINT32_C(1) << 21)
//< OCTOSPIM clock enable
1697
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV20 (UINT32_C(1) << 20)
//< reserved, don't change
1698
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_OCTOSPI2LPEN (UINT32_C(1) << 19)
//< OCTOSPI2 clock enable
1699
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV17 (UINT32_C(3) << 17)
//< reserved, don't change
1700
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_SDMMC1LPEN (UINT32_C(1) << 16)
//< SDMMC1 and SDMMC1 delay clock enable
1701
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV15 (UINT32_C(1) << 15)
//< reserved, don't change
1702
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_OCTOSPI1LPEN (UINT32_C(1) << 14)
//< OCTOSPI1 and OCTOSPI1 delay clock enable
1703
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV13 (UINT32_C(1) << 13)
//< reserved, don't change
1704
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_FMCLPEN (UINT32_C(1) << 12)
//< FMC peripheral clocks enable
1705
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV9 (UINT32_C(7) << 9)
//< reserved, don't change
1706
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_FLITFLPEN (UINT32_C(1) << 8)
//< FLITF peripheral clock enable
1707
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV6 (UINT32_C(3) << 6)
//< reserved, don't change
1708
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_JPGDECLPEN (UINT32_C(1) << 5)
//< JPGDEC peripheral clock enable
1709
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_DMA2DLPEN (UINT32_C(1) << 4)
//< DMA2D peripheral clock enable
1710
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV1 (UINT32_C(7) << 1)
//< reserved, don't change
1711
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_MDMALPEN (UINT32_C(1) << 0)
//< MDMA peripheral clock enable
1712
/// @}
1713
1714
/// \name RCC_AHB1LPENR bits
1715
/// @{
1716
#define MCCI_STM32H7_REG_RCC_AHB1LPENR_RSV27 (UINT32_C(0x1F) << 27)
//< reserved, don't change
1717
#define MCCI_STM32H7_REG_RCC_AHB1LPENR_USB1ULPILPEN (UINT32_C(1) << 26)
//< USB_PHY1 clocks enable
1718
#define MCCI_STM32H7_REG_RCC_AHB1LPENR_USB1OTGLPEN (UINT32_C(1) << 25)
//< USB1OTG peripheral clocks enable
1719
#define MCCI_STM32H7_REG_RCC_AHB1LPENR_RSV10 (UINT32_C(0x7FFF) << 10)
//< reserved, don't change
1720
#define MCCI_STM32H7_REG_RCC_AHB1LPENR_CRCLPEN (UINT32_C(1) << 9)
//< CRC peripheral clock enable
1721
#define MCCI_STM32H7_REG_RCC_AHB1LPENR_RSV6 (UINT32_C(7) << 6)
//< reserved, don't change
1722
#define MCCI_STM32H7_REG_RCC_AHB1LPENR_ADC12LPEN (UINT32_C(1) << 5)
//< ADC1 and 2 peripheral clocks enable
1723
#define MCCI_STM32H7_REG_RCC_AHB1LPENR_RSV2 (UINT32_C(7) << 2)
//< reserved, don't change
1724
#define MCCI_STM32H7_REG_RCC_AHB1LPENR_DMA2LPEN (UINT32_C(1) << 1)
//< DMA2 clock enable
1725
#define MCCI_STM32H7_REG_RCC_AHB1LPENR_DMA1LPEN (UINT32_C(1) << 0)
//< DMA1 clock enable
1726
/// @}
1727
1728
/// \name RCC_AHB2LPENR bits
1729
/// @{
1730
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_RSV31 (UINT32_C(1) << 31)
//< reserved, don't change
1731
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_AHBSRAM2LPEN (UINT32_C(1) << 30)
//< AHBSRAM2 block enable
1732
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_AHBSRAM1LPEN (UINT32_C(1) << 29)
//< AHBSRAM1 block enable
1733
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_RSV12 (UINT32_C(0x1FFFF) << 12)
//< reserved, don't change
1734
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_DFSDMDMALPEN (UINT32_C(1) << 11)
//< DMA clock enable (DFSDM dedicated DMA)
1735
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_RSV10 (UINT32_C(1) << 10)
//< reserved, don't change
1736
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_SDMMC2LPEN (UINT32_C(1) << 9)
//< SDMMC2 and SDMMC2 delay clock enable
1737
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_RSV7 (UINT32_C(3) << 7)
//< reserved, don't change
1738
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_RNGLPEN (UINT32_C(1) << 6)
//< RNG peripheral clocks enable
1739
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_HASHLPEN (UINT32_C(1) << 5)
//< HASH peripheral clock enable
1740
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_CRYPTLPEN (UINT32_C(1) << 4)
//< CRYPT peripheral clock enable
1741
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_RSV1 (UINT32_C(7) << 1)
//< reserved, don't change
1742
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_DCMILPEN (UINT32_C(1) << 0)
//< digital camera interface peripheral clock enable
1743
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_PSSILPEN (UINT32_C(1) << 0)
//< PSSI peripheral clock enable
1744
/// @}
1745
1746
/// \name RCC_AHB4LPENR bits
1747
/// @{
1748
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_RSV30 (UINT32_C(3) << 30)
//< reserved, don't change
1749
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_SRDSRAMLPEN (UINT32_C(1) << 29)
//< SRDSRAM enable
1750
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_BKPRAMLPEN (UINT32_C(1) << 28)
//< BKPRAM enable
1751
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_RSV22 (UINT32_C(0x3F) << 22)
//< reserved, don't change
1752
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_BDMA2LPEN (UINT32_C(1) << 21)
//< BDMA2 enable
1753
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_RSV11 (UINT32_C(0x3FF) << 11)
//< reserved, don't change
1754
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOKLPEN (UINT32_C(1) << 10)
//< GPIOK enable
1755
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOJLPEN (UINT32_C(1) << 9)
//< GPIOJ enable
1756
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOILPEN (UINT32_C(1) << 8)
//< GPIOI enable
1757
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOHLPEN (UINT32_C(1) << 7)
//< GPIOH enable
1758
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOGLPEN (UINT32_C(1) << 6)
//< GPIOG enable
1759
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOFLPEN (UINT32_C(1) << 5)
//< GPIOF enable
1760
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOELPEN (UINT32_C(1) << 4)
//< GPIOE enable
1761
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIODLPEN (UINT32_C(1) << 3)
//< GPIOD enable
1762
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOCLPEN (UINT32_C(1) << 2)
//< GPIOC enable
1763
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOBLPEN (UINT32_C(1) << 1)
//< GPIOB enable
1764
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOALPEN (UINT32_C(1) << 0)
//< GPIOA enable
1765
/// @}
1766
1767
/// \name RCC_APB3LPENR bits
1768
/// @{
1769
#define MCCI_STM32H7_REG_RCC_APB3LPENR_RSV7 UINT32_C(0xFFFFFF80)
//< reserved, don't change
1770
#define MCCI_STM32H7_REG_RCC_APB3LPENR_WWDGLPEN (UINT32_C(1) << 26)
//< WWDG enable
1771
#define MCCI_STM32H7_REG_RCC_APB3LPENR_RSV4 (UINT32_C(3) << 4)
//< reserved, don't change
1772
#define MCCI_STM32H7_REG_RCC_APB3LPENR_LTDCLPEN (UINT32_C(1) << 25)
//< LTDC enable
1773
#define MCCI_STM32H7_REG_RCC_APB3LPENR_RSV0 (UINT32_C(7) << 0)
//< reserved, don't change
1774
/// @}
1775
1776
/// \name RCC_APB1LLPENR bits
1777
/// @{
1778
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_UART8LPEN (UINT32_C(1) << 31)
//< UART8 clock enable
1779
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_UART7LPEN (UINT32_C(1) << 30)
//< UART7 clock enable
1780
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_DAC1LPEN (UINT32_C(1) << 29)
//< DAC1 clock enable
1781
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_RSV28 (UINT32_C(1) << 28)
//< reserved, don't change
1782
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_CECLPEN (UINT32_C(1) << 27)
//< CEC clock enable
1783
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_RSV24 (UINT32_C(7) << 24)
//< reserved, don't change
1784
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_I2C3LPEN (UINT32_C(1) << 23)
//< I2C3 clock enable
1785
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_I2C2LPEN (UINT32_C(1) << 22)
//< I2C2 clock enable
1786
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_I2C1LPEN (UINT32_C(1) << 21)
//< I2C1 clock enable
1787
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_USART5LPEN (UINT32_C(1) << 20)
//< USART5 clock enable
1788
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_USART4LPEN (UINT32_C(1) << 19)
//< USART4 clock enable
1789
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_USART3LPEN (UINT32_C(1) << 18)
//< USART3 clock enable
1790
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_USART2LPEN (UINT32_C(1) << 17)
//< USART2 clock enable
1791
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_SPDIFRXLPEN (UINT32_C(1) << 16)
//< SPDIFRX clock enable
1792
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_SPI3LPEN (UINT32_C(1) << 15)
//< SPI3 clock enable
1793
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_SPI2LPEN (UINT32_C(1) << 14)
//< SPI2 clock enable
1794
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_RSV10 (UINT32_C(0xF) << 10)
//< reserved, don't change
1795
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_LPTIM1LPEN (UINT32_C(1) << 9)
//< LPTIM1 clock enable
1796
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM14LPEN (UINT32_C(1) << 8)
//< TIM14 clock enable
1797
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM13LPEN (UINT32_C(1) << 7)
//< TIM13 clock enable
1798
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM12LPEN (UINT32_C(1) << 6)
//< TIM12 clock enable
1799
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM7LPEN (UINT32_C(1) << 5)
//< TIM7 clock enable
1800
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM6LPEN (UINT32_C(1) << 4)
//< TIM6 clock enable
1801
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM5LPEN (UINT32_C(1) << 3)
//< TIM5 clock enable
1802
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM4LPEN (UINT32_C(1) << 2)
//< TIM4 clock enable
1803
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM3LPEN (UINT32_C(1) << 1)
//< TIM3 clock enable
1804
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM2LPEN (UINT32_C(1) << 0)
//< TIM2 clock enable
1805
/// @}
1806
1807
/// \name RCC_APB1HLPENR bits
1808
/// @{
1809
#define MCCI_STM32H7_REG_RCC_APB1HLPENR_RSV9 UINT32_C(0xFFFFFE00)
///< reserved, don't change
1810
#define MCCI_STM32H7_REG_RCC_APB1HLPENR_FDCANLPEN (UINT32_C(1) << 8)
//< FDCAN clock enable
1811
#define MCCI_STM32H7_REG_RCC_APB1HLPENR_RSV6 (UINT32_C(3) << 6)
//< reserved, don't change
1812
#define MCCI_STM32H7_REG_RCC_APB1HLPENR_MDIOSLPEN (UINT32_C(1) << 5)
//< MDIOS clock enable
1813
#define MCCI_STM32H7_REG_RCC_APB1HLPENR_OPAMPLPEN (UINT32_C(1) << 4)
//< OPAMP clock enable
1814
#define MCCI_STM32H7_REG_RCC_APB1HLPENR_RSV3 (UINT32_C(1) << 3)
//< reserved, don't change
1815
#define MCCI_STM32H7_REG_RCC_APB1HLPENR_SWPMILPEN (UINT32_C(1) << 2)
//< SWPMI clock enable
1816
#define MCCI_STM32H7_REG_RCC_APB1HLPENR_CRSLPEN (UINT32_C(1) << 1)
//< CRS clock enable
1817
#define MCCI_STM32H7_REG_RCC_APB1HLPENR_RSV0 (UINT32_C(1) << 0)
//< reserved, don't change
1818
/// @}
1819
1820
/// \name RCC_APB2LPENR bits
1821
/// @{
1822
#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV31 (UINT32_C(1) << 31)
///< reserved, don't change
1823
#define MCCI_STM32H7_REG_RCC_APB2LPENR_DFSDM1LPEN (UINT32_C(1) << 30)
///< DFSDM1 clock enable
1824
#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV24 (UINT32_C(0x3F) << 24)
///< reserved, don't change
1825
#define MCCI_STM32H7_REG_RCC_APB2LPENR_SAI2LPEN (UINT32_C(1) << 23)
///< SAI2 clock enable
1826
#define MCCI_STM32H7_REG_RCC_APB2LPENR_SAI1LPEN (UINT32_C(1) << 22)
///< SAI1 clock enable
1827
#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV21 (UINT32_C(1) << 21)
///< reserved, don't change
1828
#define MCCI_STM32H7_REG_RCC_APB2LPENR_SPI5LPEN (UINT32_C(1) << 20)
///< SPI5 clock enable
1829
#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV19 (UINT32_C(1) << 19)
///< reserved, don't change
1830
#define MCCI_STM32H7_REG_RCC_APB2LPENR_TIM17LPEN (UINT32_C(1) << 18)
///< TIM17 clock enable
1831
#define MCCI_STM32H7_REG_RCC_APB2LPENR_TIM16LPEN (UINT32_C(1) << 17)
///< TIM16 clock enable
1832
#define MCCI_STM32H7_REG_RCC_APB2LPENR_TIM15LPEN (UINT32_C(1) << 16)
///< TIM15 clock enable
1833
#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV14 (UINT32_C(3) << 14)
///< reserved, don't change
1834
#define MCCI_STM32H7_REG_RCC_APB2LPENR_SPI4LPEN (UINT32_C(1) << 13)
///< SPI4 clock enable
1835
#define MCCI_STM32H7_REG_RCC_APB2LPENR_SPI1LPEN (UINT32_C(1) << 12)
///< SPI1 clock enable
1836
#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV8 (UINT32_C(0xF) << 8)
///< reserved, don't change
1837
#define MCCI_STM32H7_REG_RCC_APB2LPENR_USART10LPEN (UINT32_C(1) << 7)
///< USART10 clock enable
1838
#define MCCI_STM32H7_REG_RCC_APB2LPENR_UART9LPEN (UINT32_C(1) << 6)
///< UART9 clock enable
1839
#define MCCI_STM32H7_REG_RCC_APB2LPENR_USART6LPEN (UINT32_C(1) << 5)
///< USART6 clock enable
1840
#define MCCI_STM32H7_REG_RCC_APB2LPENR_USART1LPEN (UINT32_C(1) << 4)
///< USART1 clock enable
1841
#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV2 (UINT32_C(3) << 2)
///< reserved, don't change
1842
#define MCCI_STM32H7_REG_RCC_APB2LPENR_TIM8LPEN (UINT32_C(1) << 1)
///< TIM8 clock enable
1843
#define MCCI_STM32H7_REG_RCC_APB2LPENR_TIM1LPEN (UINT32_C(1) << 0)
///< TIM1 clock enable
1844
/// @}
1845
1846
/// \name RCC_APB4LPENR bits
1847
/// @{
1848
#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV28 (UINT32_C(0xF) << 28)
//< reserved, don't change
1849
#define MCCI_STM32H7_REG_RCC_APB4LPENR_DFSDM2LPEN (UINT32_C(1) << 27)
//< DFSDM2 clock enable
1850
#define MCCI_STM32H7_REG_RCC_APB4LPENR_DTSLPEN (UINT32_C(1) << 26)
//< DTS clock enable
1851
#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV17 (UINT32_C(0x1FF) << 17)
//< reserved, don't change
1852
#define MCCI_STM32H7_REG_RCC_APB4LPENR_RTCAPBLPEN (UINT32_C(1) << 16)
//< RTCAPB clock enable
1853
#define MCCI_STM32H7_REG_RCC_APB4LPENR_VREFLPEN (UINT32_C(1) << 15)
//< VREF clock enable
1854
#define MCCI_STM32H7_REG_RCC_APB4LPENR_COMP12LPEN (UINT32_C(1) << 14)
//< COMP12 clock enable
1855
#define MCCI_STM32H7_REG_RCC_APB4LPENR_DAC2LPEN (UINT32_C(1) << 13)
//< DAC2 clock enable
1856
#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV11 (UINT32_C(3) << 11)
//< reserved, don't change
1857
#define MCCI_STM32H7_REG_RCC_APB4LPENR_LPTIM3LPEN (UINT32_C(1) << 10)
//< LPTIM3 clock enable
1858
#define MCCI_STM32H7_REG_RCC_APB4LPENR_LPTIM2LPEN (UINT32_C(1) << 9)
//< LPTIM2 clock enable
1859
#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV8 (UINT32_C(1) << 8)
//< reserved, don't change
1860
#define MCCI_STM32H7_REG_RCC_APB4LPENR_I2C4LPEN (UINT32_C(1) << 7)
//< I2C4 clock enable
1861
#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV6 (UINT32_C(1) << 6)
//< reserved, don't change
1862
#define MCCI_STM32H7_REG_RCC_APB4LPENR_SPI6LPEN (UINT32_C(1) << 5)
//< SPI6 clock enable
1863
#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV4 (UINT32_C(1) << 4)
//< reserved, don't change
1864
#define MCCI_STM32H7_REG_RCC_APB4LPENR_LPUART1LPEN (UINT32_C(1) << 3)
//< LPUART1 clock enable
1865
#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV2 (UINT32_C(1) << 2)
//< reserved, don't change
1866
#define MCCI_STM32H7_REG_RCC_APB4LPENR_SYSCFGLPEN (UINT32_C(1) << 1)
//< SYSCFG clock enable
1867
#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV0 (UINT32_C(1) << 0)
//< reserved, don't change
1868
/// @}
1869
1870
/****************************************************************************\
1871
|
1872
| GPIO Control Registers
1873
|
1874
\****************************************************************************/
1875
1876
/// \name GPIO register offsets
1877
/// @{
1878
#define MCCI_STM32H7_GPIO_MODER UINT32_C(0x00)
//< port mode register
1879
#define MCCI_STM32H7_GPIO_OTYPER UINT32_C(0x04)
//< port output type register
1880
#define MCCI_STM32H7_GPIO_OSPEEDR UINT32_C(0x08)
//< port output speed register
1881
#define MCCI_STM32H7_GPIO_PUPDR UINT32_C(0x0C)
//< port pull-up/pull-down register
1882
#define MCCI_STM32H7_GPIO_IDR UINT32_C(0x10)
//< port input data register
1883
#define MCCI_STM32H7_GPIO_ODR UINT32_C(0x14)
//< port output data register
1884
#define MCCI_STM32H7_GPIO_BSRR UINT32_C(0x18)
//< port bit set/reset register
1885
#define MCCI_STM32H7_GPIO_LCKR UINT32_C(0x1C)
//< port configuration lock register
1886
#define MCCI_STM32H7_GPIO_AFRL UINT32_C(0x20)
//< port alternate function low register
1887
#define MCCI_STM32H7_GPIO_AFRH UINT32_C(0x24)
//< port alternate function high register
1888
/// @}
1889
1890
/// \name GPIO_MODER bits -- used to select pin mode, two bits per pin
1891
/// @{
1892
#define MCCI_STM32H7_GPIO_MODE_MASK UINT32_C(3)
//< mode bit masks
1893
#define MCCI_STM32H7_GPIO_MODE_IN UINT32_C(0)
//< digital input
1894
#define MCCI_STM32H7_GPIO_MODE_OUT UINT32_C(1)
//< digital output
1895
#define MCCI_STM32H7_GPIO_MODE_AF UINT32_C(2)
//< alternate function
1896
#define MCCI_STM32H7_GPIO_MODE_ANALOG UINT32_C(3)
//< analog
1897
/// @}
1898
1899
/// \brief compute the mask for the mode bits for port bits 0..31
1900
///
1901
/// Normally we compute a mask using an expression like:
1902
///
1903
/// `MCCI_BOOTLOADER_FIELD_SET_VALUE(
1904
/// MCCI_STM32H7_GPIO_MODE_P(3),
1905
/// MCCI_STM32H7_GPIO_MODE_IN
1906
/// )`
1907
///
1908
#define MCCI_STM32H7_GPIO_MODE_P(p) (UINT32_C(3) << (2 * (p)))
1909
#define MCCI_STM32H7_GPIO_MODE_PV(p, v) ((v) << (2 * (p)))
1910
1911
/// \name GPIO_OTYPER bits
1912
/// @{
1913
#define MCCI_STM32H7_GPIO_OTYPE_PP UINT32_C(0)
//< Output push-pull
1914
#define MCCI_STM32H7_GPIO_OTYPE_OD UINT32_C(1)
//< Output open-drain
1915
/// @}
1916
1917
1918
/// \brief compute the mask for the mode bits for port bits 0..15
1919
///
1920
/// Normally we compute a mask using an expression like:
1921
///
1922
/// `MCCI_BOOTLOADER_FIELD_SET_VALUE(
1923
/// MCCI_STM32H7_GPIO_OTYPE_P(3),
1924
/// MCCI_STM32H7_GPIO_OTYPE_PP
1925
/// )`
1926
///
1927
#define MCCI_STM32H7_GPIO_OTYPE_P(p) (UINT32_C(1) << (p))
1928
#define MCCI_STM32H7_GPIO_OTYPE_PV(p, v) ((v) << (p))
1929
1930
/// \name GPIO_OSPEEDR bits -- used to select pin speed, two bits per pin
1931
/// @{
1932
#define MCCI_STM32H7_GPIO_OSPEED_MASK UINT32_C(3)
//< speed bit masks
1933
#define MCCI_STM32H7_GPIO_OSPEED_LOW UINT32_C(0)
//< low
1934
#define MCCI_STM32H7_GPIO_OSPEED_MEDIUM UINT32_C(1)
//< medium
1935
#define MCCI_STM32H7_GPIO_OSPEED_HIGH UINT32_C(2)
//< high
1936
#define MCCI_STM32H7_GPIO_OSPEED_VHIGH UINT32_C(3)
//< very high
1937
/// @}
1938
1939
/// \brief compute the mask for the mode bits for port bits 0..31
1940
///
1941
/// Normally we compute a mask using an expression like:
1942
///
1943
/// `MCCI_BOOTLOADER_FIELD_SET_VALUE(
1944
/// MCCI_STM32H7_GPIO_OSPEED_P(3),
1945
/// MCCI_STM32H7_GPIO_OSPEED_IN
1946
/// )`
1947
///
1948
#define MCCI_STM32H7_GPIO_OSPEED_P(p) (UINT32_C(3) << (2 * (p)))
1949
#define MCCI_STM32H7_GPIO_OSPEED_PV(p, v) ((v) << (2 * (p)))
1950
1951
/// \name GPIO_PUPDR bits -- used to select pin speed, two bits per pin
1952
/// @{
1953
#define MCCI_STM32H7_GPIO_PUPD_MASK UINT32_C(3)
//< speed bit masks
1954
#define MCCI_STM32H7_GPIO_PUPD_NONE UINT32_C(0)
//< no pullup/pulldown
1955
#define MCCI_STM32H7_GPIO_PUPD_PULLUP UINT32_C(1)
//< pullup
1956
#define MCCI_STM32H7_GPIO_PUPD_PULLDOWN UINT32_C(2)
//< pulldown
1957
/// @}
1958
1959
/// \brief compute the mask for the mode bits for port bits 0..31
1960
///
1961
/// Normally we compute a mask using an expression like:
1962
///
1963
/// `MCCI_BOOTLOADER_FIELD_SET_VALUE(
1964
/// MCCI_STM32H7_GPIO_PUPD_P(3),
1965
/// MCCI_STM32H7_GPIO_PUPD_PULLDOWN
1966
/// )`
1967
///
1968
#define MCCI_STM32H7_GPIO_PUPD_P(p) (UINT32_C(3) << (2 * (p)))
1969
#define MCCI_STM32H7_GPIO_PUPD_PV(p, v) ((v) << (2 * (p)))
1970
1971
/// \name GPIO_BSRR bits
1972
/// @{
1973
#define MCCI_STM32H7_GPIO_BSRR_BR0 (UINT32_C(1) << 16)
//< reset port bit 0
1974
#define MCCI_STM32H7_GPIO_BSRR_BR (UINT32_C(0xFFFF) << 16)
//< mask of port-reset bits
1975
#define MCCI_STM32H7_GPIO_BSRR_BS0 (UINT32_C(1) << 0)
//< set port bit 0
1976
#define MCCI_STM32H7_GPIO_BSRR_BS (UINT32_C(0xFFFF) << 0)
//< mask of port-set bits
1977
/// \brief compute port-bit reset mask for bit \p p.
1978
#define MCCI_STM32H7_GPIO_BSRR_BR_P(p) (MCCI_STM32H7_GPIO_BSRR_BR0 << (p))
1979
/// \brief compute port-bit set mask for bit \p p.
1980
#define MCCI_STM32H7_GPIO_BSRR_BS_P(p) (MCCI_STM32H7_GPIO_BSRR_BS0 << (p))
1981
/// @}
1982
1983
/// \name GPIO_LCKR bits
1984
/// @{
1985
#define MCCI_STM32H7_GPIO_LCKR_RSV17 UINT32_C(0xFFFE0000)
//< reserved, don't change
1986
#define MCCI_STM32H7_GPIO_LCKR_LCKK (UINT32_C(1) << 16)
//< lock key bit; if set, ports are locked.
1987
/// \brief compute GPIO lock bit fmask for bit \p p.
1988
#define MCCI_STM32H7_GPIO_LCKR_LCK_P(p) (UINT32_C(1) << (p))
1989
#define MCCI_STM32H7_GPIO_LCKR_LCK (UINT32_C(0xFFFF) << 0)
//< mask of port-lock bits.
1990
/// @}
1991
1992
/// \name GPIO_AFRx bits
1993
/// @{
1994
/// \brief get reg offset for GPIO_AFRx
1995
#define MCCI_STM32H7_GPIO_AFRx_P(p) (MCCI_STM32H7_GPIO_AFRL + (((p) / UINT32_C(8)) * UINT32_C(4)))
//< f
1996
/// @}
1997
1998
/// \brief get AFRx mask for port bit \p p.
1999
///
2000
/// Normal use:
2001
/// `MCCI_BOOTLOADER_FIELD_SET_VALUE(
2002
/// MCCI_STM32H7_GPIO_AFSEL_P(bitnum),
2003
/// 0..15
2004
/// )`
2005
///
2006
#define MCCI_STM32H7_GPIO_AFSEL_P(p) (UINT32_C(0xF) << (((p) & UINT32_C(0x7)) * UINT32_C(4)))
2007
#define MCCI_STM32H7_GPIO_AFSEL_PV(p,v) ((v) << (((p) & UINT32_C(0x7)) * UINT32_C(4)))
2008
2009
/****************************************************************************\
2010
|
2011
| SPI Control Registers
2012
|
2013
\****************************************************************************/
2014
2015
/// \name SPI offsets
2016
/// @{
2017
#define MCCI_STM32H7_SPI_CR1 UINT32_C(0x00)
///< offset to SPI control register 1
2018
#define MCCI_STM32H7_SPI_CR2 UINT32_C(0x04)
///< offset to SPI control register 2
2019
#define MCCI_STM32H7_SPI_CFG1 UINT32_C(0x08)
///< offset to SPI configuration register 1
2020
#define MCCI_STM32H7_SPI_CFG2 UINT32_C(0x0C)
///< offset to SPI configuration register 2
2021
#define MCCI_STM32H7_SPI_IER UINT32_C(0x10)
///< offset to SPI interrupt enable register
2022
#define MCCI_STM32H7_SPI_SR UINT32_C(0x14)
///< offset to SPI status register
2023
#define MCCI_STM32H7_SPI_IFCR UINT32_C(0x18)
///< offset to SPI interrupt/status flags clear register
2024
#define MCCI_STM32H7_SPI_TXDR UINT32_C(0x20)
///< offset to SPI transmit data register
2025
#define MCCI_STM32H7_SPI_RXDR UINT32_C(0x30)
///< offset to SPI receive data register
2026
#define MCCI_STM32H7_SPI_CRCPOLY UINT32_C(0x40)
///< offset to SPI CRC polynomial
2027
#define MCCI_STM32H7_SPI_TXCRC UINT32_C(0x44)
///< offset to SPI transmit CRC
2028
#define MCCI_STM32H7_SPI_RXCRC UINT32_C(0x48)
///< offset to SPI receive CRC
2029
#define MCCI_STM32H7_SPI_UDRDR UINT32_C(0x4C)
///< offset to SPI underrun data CRC
2030
#define MCCI_STM32H7_SPI_I2SCFGR UINT32_C(0x50)
///< offset to SPI I2S config register
2031
/// @}
2032
2033
/// \name SPI_CR1 bits
2034
/// @{
2035
#define MCCI_STM32H7_SPI_CR1_RSV17 UINT32_C(0xFFFE0000)
///< reserved, don't change
2036
#define MCCI_STM32H7_SPI_CR1_IOLOCK (UINT32_C(1) << 16)
///< locking the AF configuration of associated IOs
2037
#define MCCI_STM32H7_SPI_CR1_TCRCINI (UINT32_C(1) << 15)
///< CRC calculation initialization pattern control for transmitter
2038
#define MCCI_STM32H7_SPI_CR1_RCRCINI (UINT32_C(1) << 14)
///< CRC calculation initialization pattern control for receiver
2039
#define MCCI_STM32H7_SPI_CR1_CRC33_17 (UINT32_C(1) << 13)
///< 32-bit CRC polynomial configuration
2040
#define MCCI_STM32H7_SPI_CR1_SSI (UINT32_C(1) << 12)
///< internal SS signal input level
2041
#define MCCI_STM32H7_SPI_CR1_HDDIR (UINT32_C(1) << 11)
///< Rx/Tx direction at Half-duplex mode
2042
#define MCCI_STM32H7_SPI_CR1_CSUSP (UINT32_C(1) << 10)
///< master suspend request
2043
#define MCCI_STM32H7_SPI_CR1_CSTART (UINT32_C(1) << 9)
///< master transfer start
2044
#define MCCI_STM32H7_SPI_CR1_MASRX (UINT32_C(1) << 8)
///< master automatic SUSP in Receive mode
2045
#define MCCI_STM32H7_SPI_CR1_RSV1 (UINT32_C(0x7F) << 1)
///< reserved, don't change
2046
#define MCCI_STM32H7_SPI_CR1_SPE (UINT32_C(1) << 0)
///< serial peripheral enable
2047
/// @}
2048
2049
/// \name SPI_CR2 bits
2050
/// @{
2051
#define MCCI_STM32H7_SPI_CR2_TSER UINT32_C(0xFFFF0000)
///< number of data transfer extension to be reload into TSIZE
2052
#define MCCI_STM32H7_SPI_CR2_TSIZE UINT32_C(0x0000FFFF)
///< number of data at current transfer
2053
/// @}
2054
2055
/// \name SPI_CFG1 bits
2056
/// @{
2057
#define MCCI_STM32H7_SPI_CFG1_RSV31 (UINT32_C(1) << 31)
///< reserved, don't change
2058
#define MCCI_STM32H7_SPI_CFG1_MBR (UINT32_C(7) << 28)
///< master baud rate
2059
#define MCCI_STM32H7_SPI_CFG1_MBR_2 (UINT32_C(0) << 28)
///< SPI master clock/2
2060
#define MCCI_STM32H7_SPI_CFG1_MBR_4 (UINT32_C(1) << 28)
///< SPI master clock/4
2061
#define MCCI_STM32H7_SPI_CFG1_MBR_8 (UINT32_C(2) << 28)
///< SPI master clock/8
2062
#define MCCI_STM32H7_SPI_CFG1_MBR_16 (UINT32_C(3) << 28)
///< SPI master clock/16
2063
#define MCCI_STM32H7_SPI_CFG1_MBR_32 (UINT32_C(4) << 28)
///< SPI master clock/32
2064
#define MCCI_STM32H7_SPI_CFG1_MBR_64 (UINT32_C(5) << 28)
///< SPI master clock/64
2065
#define MCCI_STM32H7_SPI_CFG1_MBR_128 (UINT32_C(6) << 28)
///< SPI master clock/128
2066
#define MCCI_STM32H7_SPI_CFG1_MBR_256 (UINT32_C(7) << 28)
///< SPI master clock/256
2067
#define MCCI_STM32H7_SPI_CFG1_RSV23 (UINT32_C(0x1F) << 23)
///< reserved, don't change
2068
#define MCCI_STM32H7_SPI_CFG1_CRCEN (UINT32_C(1) << 22)
///< hardware CRC computation enable
2069
#define MCCI_STM32H7_SPI_CFG1_RSV21 (UINT32_C(1) << 21)
///< reserved, don't change
2070
#define MCCI_STM32H7_SPI_CFG1_CRCSIZE (UINT32_C(0x1F) << 16)
///< length of CRC frame to be transacted and compared
2071
#define MCCI_STM32H7_SPI_CFG1_CRCSIZE_N(n) ((n) << 16)
///< n+1 bits
2072
#define MCCI_STM32H7_SPI_CFG1_TXDMAEN (UINT32_C(1) << 15)
///< Tx DMA stream enable
2073
#define MCCI_STM32H7_SPI_CFG1_RXDMAEN (UINT32_C(1) << 14)
///< Rx DMA stream enable
2074
#define MCCI_STM32H7_SPI_CFG1_RSV13 (UINT32_C(1) << 13)
///< reserved, don't change
2075
#define MCCI_STM32H7_SPI_CFG1_UDRDET (UINT32_C(3) << 11)
///< detection of underrun condition at slave transmitter
2076
#define MCCI_STM32H7_SPI_CFG1_UDRDET_BEGIN (UINT32_C(0) << 11)
///< underrun is detected at begin of data frame
2077
#define MCCI_STM32H7_SPI_CFG1_UDRDET_END (UINT32_C(1) << 11)
///< underrun is detected at end of data frame
2078
#define MCCI_STM32H7_SPI_CFG1_UDRDET_BEGIN_SS (UINT32_C(2) << 11)
///< underrun is detected at begin of active SS signal
2079
#define MCCI_STM32H7_SPI_CFG1_UDRCFG (UINT32_C(3) << 9)
///< behavior of slave transmitter at underrun condition
2080
#define MCCI_STM32H7_SPI_CFG1_UDRCFG_CONST (UINT32_C(0) << 9)
///< slave sends a constant pattern defined by the user at SPI_UDRDR register
2081
#define MCCI_STM32H7_SPI_CFG1_UDRCFG_RX (UINT32_C(1) << 9)
///< slave repeats lastly received data frame from master
2082
#define MCCI_STM32H7_SPI_CFG1_UDRCFG_TX (UINT32_C(2) << 9)
///< slave repeats its lastly transmitted data frame
2083
#define MCCI_STM32H7_SPI_CFG1_FTHLV (UINT32_C(0xF) << 5)
///< FIFO threshold level
2084
#define MCCI_STM32H7_SPI_CFG1_FTHLV_N(n) ((n) << 5)
///< n+1 data
2085
#define MCCI_STM32H7_SPI_CFG1_DSIZE (UINT32_C(0x1F) << 0)
///< number of bits in at single SPI data frame
2086
#define MCCI_STM32H7_SPI_CFG1_DSIZE_N(n) ((n) << 0)
///< n+1 bits
2087
/// @}
2088
2089
/// \name SPI_CFG2 bits
2090
/// @{
2091
#define MCCI_STM32H7_SPI_CFG2_AFCNTR (UINT32_C(1) << 31)
///< alternate function GPIOs control
2092
#define MCCI_STM32H7_SPI_CFG2_SSOM (UINT32_C(1) << 30)
///< SS output management in master mode
2093
#define MCCI_STM32H7_SPI_CFG2_SSOE (UINT32_C(1) << 29)
///< SS output enable
2094
#define MCCI_STM32H7_SPI_CFG2_SSIOP (UINT32_C(1) << 28)
///< SS input/output polarity
2095
#define MCCI_STM32H7_SPI_CFG2_RSV27 (UINT32_C(1) << 27)
///< reserved, don't change
2096
#define MCCI_STM32H7_SPI_CFG2_SSM (UINT32_C(1) << 26)
///< software management of SS signal input
2097
#define MCCI_STM32H7_SPI_CFG2_CPOL (UINT32_C(1) << 25)
///< clock polarity
2098
#define MCCI_STM32H7_SPI_CFG2_CPHA (UINT32_C(1) << 24)
///< clock phase
2099
#define MCCI_STM32H7_SPI_CFG2_LSBFRST (UINT32_C(1) << 23)
///< data frame format
2100
#define MCCI_STM32H7_SPI_CFG2_MASTER (UINT32_C(1) << 22)
///< SPI master
2101
#define MCCI_STM32H7_SPI_CFG2_SP (UINT32_C(7) << 19)
///< Serial protocol
2102
#define MCCI_STM32H7_SPI_CFG2_COMM (UINT32_C(3) << 17)
///< SPI communication mode
2103
#define MCCI_STM32H7_SPI_CFG2_COMM_FULL_DUPLEX (UINT32_C(0) << 17)
///< full-duplex
2104
#define MCCI_STM32H7_SPI_CFG2_COMM_SIMPLEX_TX (UINT32_C(1) << 17)
///< simplex transmitter
2105
#define MCCI_STM32H7_SPI_CFG2_COMM_SIMPLEX_RX (UINT32_C(2) << 17)
///< simplex receiver
2106
#define MCCI_STM32H7_SPI_CFG2_COMM_HALF_DUPLEX (UINT32_C(3) << 17)
///< half-duplex
2107
#define MCCI_STM32H7_SPI_CFG2_RSV16 (UINT32_C(1) << 16)
///< reserved, don't change
2108
#define MCCI_STM32H7_SPI_CFG2_IOSWP (UINT32_C(1) << 15)
///< swap functionality of MISO and MOSI pins
2109
#define MCCI_STM32H7_SPI_CFG2_RSV8 (UINT32_C(0x7F) << 8)
///< reserved, don't change
2110
#define MCCI_STM32H7_SPI_CFG2_MIDI (UINT32_C(15) << 4)
///< master Inter-Data Idleness
2111
#define MCCI_STM32H7_SPI_CFG2_MIDI_N(n) ((n) << 4)
///< n clock cycle period delay
2112
#define MCCI_STM32H7_SPI_CFG2_MSSI (UINT32_C(15) << 0)
///< master SS idleness
2113
#define MCCI_STM32H7_SPI_CFG2_MSSI_N(n) ((n) << 0)
///< n clock cycle period delay added
2114
/// @}
2115
2116
/// \name SPI_IER bits
2117
/// @{
2118
#define MCCI_STM32H7_SPI_IER_RSV11 UINT32_C(0xFFFFFF80)
///< reserved, don't change
2119
#define MCCI_STM32H7_SPI_IER_TSERFIE (UINT32_C(1) << 10)
///< additional number of transactions reload interrupt enable
2120
#define MCCI_STM32H7_SPI_IER_MODFIE (UINT32_C(1) << 9)
///< mode fault interrupt enable
2121
#define MCCI_STM32H7_SPI_IER_TIFREIE (UINT32_C(1) << 8)
///< TIFRE interrupt enable
2122
#define MCCI_STM32H7_SPI_IER_CRCEIE (UINT32_C(1) << 7)
///< CRC error interrupt enable
2123
#define MCCI_STM32H7_SPI_IER_OVRIE (UINT32_C(1) << 6)
///< OVR interrupt enable
2124
#define MCCI_STM32H7_SPI_IER_UDRIE (UINT32_C(1) << 5)
///< UDR interrupt enable
2125
#define MCCI_STM32H7_SPI_IER_TXTFIE (UINT32_C(1) << 4)
///< TXTFIE interrupt enable
2126
#define MCCI_STM32H7_SPI_IER_EOTIE (UINT32_C(1) << 3)
///< EOT, SUSP and TXC interrupt enable
2127
#define MCCI_STM32H7_SPI_IER_DXPIE (UINT32_C(1) << 2)
///< DXP interrupt enabled
2128
#define MCCI_STM32H7_SPI_IER_TXPIE (UINT32_C(1) << 1)
///< TXP interrupt enable
2129
#define MCCI_STM32H7_SPI_IER_RXPIE (UINT32_C(1) << 0)
///< RXP Interrupt Enable
2130
/// @}
2131
2132
/// \name SPI_SR bits
2133
/// @{
2134
#define MCCI_STM32H7_SPI_SR_CTSIZE UINT32_C(0xFFFF0000)
///< number of data frames remaining in current TSIZE session
2135
#define MCCI_STM32H7_SPI_SR_RXWNE (UINT32_C(1) << 15)
///< RxFIFO word not empty
2136
#define MCCI_STM32H7_SPI_SR_RXPLVL (UINT32_C(3) << 13)
///< RxFIFO packing leveL
2137
#define MCCI_STM32H7_SPI_SR_RXPLVL_N(n) ((n) << 13)
///< n frame is available
2138
#define MCCI_STM32H7_SPI_SR_TXC (UINT32_C(1) << 12)
///< TxFIFO transmission complete
2139
#define MCCI_STM32H7_SPI_SR_SUSP (UINT32_C(1) << 11)
///< suspension status
2140
#define MCCI_STM32H7_SPI_SR_TSERF (UINT32_C(1) << 10)
///< additional number of SPI data to be transacted was reload
2141
#define MCCI_STM32H7_SPI_SR_MODF (UINT32_C(1) << 9)
///< mode fault
2142
#define MCCI_STM32H7_SPI_SR_TIFRE (UINT32_C(1) << 8)
///< TI frame format error
2143
#define MCCI_STM32H7_SPI_SR_CRCE (UINT32_C(1) << 7)
///< CRC error
2144
#define MCCI_STM32H7_SPI_SR_OVR (UINT32_C(1) << 6)
///< overrun
2145
#define MCCI_STM32H7_SPI_SR_UDR (UINT32_C(1) << 5)
///< underrun at slave transmission mode
2146
#define MCCI_STM32H7_SPI_SR_TXTF (UINT32_C(1) << 4)
///< transmission transfer filled
2147
#define MCCI_STM32H7_SPI_SR_EOT (UINT32_C(1) << 3)
///< end of transfer
2148
#define MCCI_STM32H7_SPI_SR_DXP (UINT32_C(1) << 2)
///< duplex packet
2149
#define MCCI_STM32H7_SPI_SR_TXP (UINT32_C(1) << 1)
///< Tx-packet space available
2150
#define MCCI_STM32H7_SPI_SR_RXP (UINT32_C(1) << 0)
///< Rx-packet available
2151
/// @}
2152
2153
/// \name SPI_IFCR bits
2154
/// @{
2155
#define MCCI_STM32H7_SPI_IFCR_RSV12 UINT32_C(0xFFFFFF00)
///< reserved, don't change
2156
#define MCCI_STM32H7_SPI_IFCR_SUSPC (UINT32_C(1) << 11)
///< SUSPend flag clear
2157
#define MCCI_STM32H7_SPI_IFCR_TSERFC (UINT32_C(1) << 10)
///< additional number of transactions reload flag clear
2158
#define MCCI_STM32H7_SPI_IFCR_MODFC (UINT32_C(1) << 9)
///< mode fault flag clear
2159
#define MCCI_STM32H7_SPI_IFCR_TIFREC (UINT32_C(1) << 8)
///< TIFRE flag clear
2160
#define MCCI_STM32H7_SPI_IFCR_CRCEC (UINT32_C(1) << 7)
///< CRC error flag clear
2161
#define MCCI_STM32H7_SPI_IFCR_OVRC (UINT32_C(1) << 6)
///< OVR flag clear
2162
#define MCCI_STM32H7_SPI_IFCR_UDRC (UINT32_C(1) << 5)
///< UDR flag clear
2163
#define MCCI_STM32H7_SPI_IFCR_TXTFC (UINT32_C(1) << 4)
///< TXTFC flag clear
2164
#define MCCI_STM32H7_SPI_IFCR_EOTC (UINT32_C(1) << 3)
///< EOT, SUSP and TXC flag clear
2165
#define MCCI_STM32H7_SPI_IFCR_RSV0 (UINT32_C(7) << 0)
///< reserved, don't change
2166
/// @}
2167
2168
/// \name SPI_I2SCFGR bits
2169
/// @{
2170
#define MCCI_STM32H7_SPI_I2SCFGR_RSV26 (UINT32_C(0x3F) << 26)
///< reserved (do not change)
2171
#define MCCI_STM32H7_SPI_I2SCFGR_MCKOE (UINT32_C(1) << 25)
///< master clock output enable
2172
#define MCCI_STM32H7_SPI_I2SCFGR_ODD (UINT32_C(1) << 24)
///< odd factor for the prescaler
2173
#define MCCI_STM32H7_SPI_I2SCFGR_I2SDIV (UINT32_C(0xFF) << 16)
///< I2S linear prescaler
2174
#define MCCI_STM32H7_SPI_I2SCFGR_I2SDIV_N(n) ((n) << 16)
///<
2175
#define MCCI_STM32H7_SPI_I2SCFGR_RSV15 (UINT32_C(1) << 15)
///< reserved (do not change)
2176
#define MCCI_STM32H7_SPI_I2SCFGR_DATFMT (UINT32_C(1) << 14)
///< data format
2177
#define MCCI_STM32H7_SPI_I2SCFGR_WSINV (UINT32_C(1) << 13)
///< Word select inversion
2178
#define MCCI_STM32H7_SPI_I2SCFGR_FIXCH (UINT32_C(1) << 12)
///< fixed channel length in slave
2179
#define MCCI_STM32H7_SPI_I2SCFGR_CKPOL (UINT32_C(1) << 11)
///< serial audio clock polarity
2180
#define MCCI_STM32H7_SPI_I2SCFGR_CHLEN (UINT32_C(1) << 10)
///< channel length
2181
#define MCCI_STM32H7_SPI_I2SCFGR_DATLEN (UINT32_C(3) << 8)
///< data length to be transferred
2182
#define MCCI_STM32H7_SPI_I2SCFGR_DATLEN_16 (UINT32_C(0) << 8)
///< 16 bit
2183
#define MCCI_STM32H7_SPI_I2SCFGR_DATLEN_24 (UINT32_C(1) << 8)
///< 24 bit
2184
#define MCCI_STM32H7_SPI_I2SCFGR_DATLEN_32 (UINT32_C(2) << 8)
///< 32 bit
2185
#define MCCI_STM32H7_SPI_I2SCFGR_PCMSYNC (UINT32_C(1) << 7)
///< PCM frame synchronization
2186
#define MCCI_STM32H7_SPI_I2SCFGR_RSV6 (UINT32_C(1) << 6)
///< reserved (do not change)
2187
#define MCCI_STM32H7_SPI_I2SCFGR_I2SSTD (UINT32_C(3) << 4)
///< I2S standard selection
2188
#define MCCI_STM32H7_SPI_I2SCFGR_I2SSTD_PHILIPS (UINT32_C(0) << 4)
///< I2S Philips standard
2189
#define MCCI_STM32H7_SPI_I2SCFGR_I2SSTD_MSB (UINT32_C(1) << 4)
///< MSB justified standard
2190
#define MCCI_STM32H7_SPI_I2SCFGR_I2SSTD_LSB (UINT32_C(2) << 4)
///< LSB justified standard
2191
#define MCCI_STM32H7_SPI_I2SCFGR_I2SSTD_PCM (UINT32_C(3) << 4)
///< PCM standard
2192
#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG (UINT32_C(7) << 1)
///< I2S configuration mode
2193
#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_STX (UINT32_C(0) << 1)
///< slave - transmit
2194
#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_SRX (UINT32_C(1) << 1)
///< slave - receive
2195
#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_MTX (UINT32_C(2) << 1)
///< master - transmit
2196
#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_MRX (UINT32_C(3) << 1)
///< master - receive
2197
#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_SFD (UINT32_C(4) << 1)
///< slave - full duplex
2198
#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_MFD (UINT32_C(5) << 1)
///< master - full duplex
2199
#define MCCI_STM32H7_SPI_I2SCFGR_I2SMOD (UINT32_C(1) << 0)
///< I2S mode selection
2200
/// @}
2201
2202
2203
/****************************************************************************\
2204
|
2205
| DMA Control Registers
2206
|
2207
\****************************************************************************/
2208
2209
/// \name DMA offsets
2210
/// @{
2211
#define MCCI_STM32H7_DMA_LISR UINT32_C(0x00)
///< offset to DMA low interrupt status register
2212
#define MCCI_STM32H7_DMA_HISR UINT32_C(0x04)
///< offset to DMA high interrupt status register
2213
#define MCCI_STM32H7_DMA_LIFCR UINT32_C(0x08)
///< offset to DMA low interrupt flag clear register
2214
#define MCCI_STM32H7_DMA_HIFCR UINT32_C(0x0C)
///< offset to DMA high interrupt flag clear register
2215
2216
#define MCCI_STM32H7_DMA_SCR UINT32_C(0x00)
///< offset to DMA stream configuration register
2217
#define MCCI_STM32H7_DMA_SNDTR UINT32_C(0x04)
///< offset to DMA stream number of data register
2218
#define MCCI_STM32H7_DMA_SPAR UINT32_C(0x08)
///< offset to DMA stream peripheral address register
2219
#define MCCI_STM32H7_DMA_SM0AR UINT32_C(0x0C)
///< offset to DMA stream memory 0 address register
2220
#define MCCI_STM32H7_DMA_SM1AR UINT32_C(0x10)
///< offset to DMA stream memory 1 address register
2221
#define MCCI_STM32H7_DMA_SFCR UINT32_C(0x14)
///< offset to DMA stream FIFO control register
2222
2223
#define MCCI_STM32H7_DMA_STREAM_BASE(x) (((x) * UINT32_C(0x18)) + UINT32_C(0x10))
///< offset to DMA stream x base
2224
#define MCCI_STM32H7_DMA_SxCR(x) (((x) * UINT32_C(0x18)) + UINT32_C(0x10))
///< offset to DMA stream x configuration register
2225
#define MCCI_STM32H7_DMA_SxNDTR(x) (((x) * UINT32_C(0x18)) + UINT32_C(0x14))
///< offset to DMA stream x number of data register
2226
#define MCCI_STM32H7_DMA_SxPAR(x) (((x) * UINT32_C(0x18)) + UINT32_C(0x18))
///< offset to DMA stream x peripheral address register
2227
#define MCCI_STM32H7_DMA_SxM0AR(x) (((x) * UINT32_C(0x18)) + UINT32_C(0x1C))
///< offset to DMA stream x memory 0 address register
2228
#define MCCI_STM32H7_DMA_SxM1AR(x) (((x) * UINT32_C(0x18)) + UINT32_C(0x20))
///< offset to DMA stream x memory 1 address register
2229
#define MCCI_STM32H7_DMA_SxFCR(x) (((x) * UINT32_C(0x18)) + UINT32_C(0x24))
///< offset to DMA stream x FIFO control register
2230
/// @}
2231
2232
/// \name DMA stream base address
2233
/// @{
2234
#define MCCI_STM32H7_DMA1_STREAM_BASE(x) \
2235
(MCCI_STM32H7_REG_DMA1 + MCCI_STM32H7_DMA_STREAM_BASE(x))
2236
#define MCCI_STM32H7_DMA2_STREAM_BASE(x) \
2237
(MCCI_STM32H7_REG_DMA2 + MCCI_STM32H7_DMA_STREAM_BASE(x))
2238
2239
#define MCCI_STM32H7_DMA_GET_STREAM(b) ((((b) & UINT32_C(0xFF)) - UINT32_C(0x10)) / UINT32_C(0x18))
2240
/// @}
2241
2242
/// \name DMA_LISR and DMA_FISR bits
2243
/// @{
2244
#define MCCI_STM32H7_DMA_ISR_RSV28 UINT32_C(0xF0000000)
///< reserved, don't change
2245
#define MCCI_STM32H7_DMA_ISR_TCIF3 (UINT32_C(1) << 27)
///< transfer complete interrupt flag
2246
#define MCCI_STM32H7_DMA_ISR_HTIF3 (UINT32_C(1) << 26)
///< half transfer interrupt flag
2247
#define MCCI_STM32H7_DMA_ISR_TEIF3 (UINT32_C(1) << 25)
///< transfer error interrupt flag
2248
#define MCCI_STM32H7_DMA_ISR_DMEIF3 (UINT32_C(1) << 24)
///< direct mode error interrupt flag
2249
#define MCCI_STM32H7_DMA_ISR_RSV23 (UINT32_C(1) << 23)
///< reserved, don't change
2250
#define MCCI_STM32H7_DMA_ISR_FEIF3 (UINT32_C(1) << 22)
///< FIFO error interrupt flag
2251
#define MCCI_STM32H7_DMA_ISR_TCIF2 (UINT32_C(1) << 21)
///< transfer complete interrupt flag
2252
#define MCCI_STM32H7_DMA_ISR_HTIF2 (UINT32_C(1) << 20)
///< half transfer interrupt flag
2253
#define MCCI_STM32H7_DMA_ISR_TEIF2 (UINT32_C(1) << 19)
///< transfer error interrupt flag
2254
#define MCCI_STM32H7_DMA_ISR_DMEIF2 (UINT32_C(1) << 18)
///< direct mode error interrupt flag
2255
#define MCCI_STM32H7_DMA_ISR_RSV17 (UINT32_C(1) << 17)
///< reserved, don't change
2256
#define MCCI_STM32H7_DMA_ISR_FEIF2 (UINT32_C(1) << 16)
///< FIFO error interrupt flag
2257
#define MCCI_STM32H7_DMA_ISR_RSV12 UINT32_C(0x0000F000)
///< reserved, don't change
2258
#define MCCI_STM32H7_DMA_ISR_TCIF1 (UINT32_C(1) << 11)
///< transfer complete interrupt flag
2259
#define MCCI_STM32H7_DMA_ISR_HTIF1 (UINT32_C(1) << 10)
///< half transfer interrupt flag
2260
#define MCCI_STM32H7_DMA_ISR_TEIF1 (UINT32_C(1) << 9)
///< transfer error interrupt flag
2261
#define MCCI_STM32H7_DMA_ISR_DMEIF1 (UINT32_C(1) << 8)
///< direct mode error interrupt flag
2262
#define MCCI_STM32H7_DMA_ISR_RSV7 (UINT32_C(1) << 7)
///< reserved, don't change
2263
#define MCCI_STM32H7_DMA_ISR_FEIF1 (UINT32_C(1) << 6)
///< FIFO error interrupt flag
2264
#define MCCI_STM32H7_DMA_ISR_TCIF0 (UINT32_C(1) << 5)
///< transfer complete interrupt flag
2265
#define MCCI_STM32H7_DMA_ISR_HTIF0 (UINT32_C(1) << 4)
///< half transfer interrupt flag
2266
#define MCCI_STM32H7_DMA_ISR_TEIF0 (UINT32_C(1) << 3)
///< transfer error interrupt flag
2267
#define MCCI_STM32H7_DMA_ISR_DMEIF0 (UINT32_C(1) << 2)
///< direct mode error interrupt flag
2268
#define MCCI_STM32H7_DMA_ISR_RSV1 (UINT32_C(1) << 1)
///< reserved, don't change
2269
#define MCCI_STM32H7_DMA_ISR_FEIF0 (UINT32_C(1) << 0)
///< FIFO error interrupt flag
2270
2271
#define MCCI_STM32H7_DMA_ISR_TCIF (UINT32_C(1) << 5)
///< transfer complete interrupt flag
2272
#define MCCI_STM32H7_DMA_ISR_HTIF (UINT32_C(1) << 4)
///< half transfer interrupt flag
2273
#define MCCI_STM32H7_DMA_ISR_TEIF (UINT32_C(1) << 3)
///< transfer error interrupt flag
2274
#define MCCI_STM32H7_DMA_ISR_DMEIF (UINT32_C(1) << 2)
///< direct mode error interrupt flag
2275
#define MCCI_STM32H7_DMA_ISR_FEIF (UINT32_C(1) << 0)
///< FIFO error interrupt flag
2276
#define MCCI_STM32H7_DMA_ISR_MASK UINT32_C(0x3D)
///< ISR stream mask
2277
/// @}
2278
2279
/// \name DMA_SCR bits
2280
/// @{
2281
#define MCCI_STM32H7_DMA_SCR_RSV25 UINT32_C(0xFE000000)
///< reserved, don't change
2282
#define MCCI_STM32H7_DMA_SCR_MBURST (UINT32_C(3) << 23)
///< memory burst transfer configuration
2283
#define MCCI_STM32H7_DMA_SCR_MBURST_SINGLE (UINT32_C(0) << 23)
///< single transfer
2284
#define MCCI_STM32H7_DMA_SCR_MBURST_INCR4 (UINT32_C(1) << 23)
///< INCR4 (incremental burst of 4 beats)
2285
#define MCCI_STM32H7_DMA_SCR_MBURST_INCR8 (UINT32_C(2) << 23)
///< INCR8 (incremental burst of 8 beats)
2286
#define MCCI_STM32H7_DMA_SCR_MBURST_INCR16 (UINT32_C(3) << 23)
///< INCR16 (incremental burst of 16 beats)
2287
#define MCCI_STM32H7_DMA_SCR_PBURST (UINT32_C(3) << 21)
///< peripheral burst transfer configuration
2288
#define MCCI_STM32H7_DMA_SCR_PBURST_SINGLE (UINT32_C(0) << 21)
///< single transfer
2289
#define MCCI_STM32H7_DMA_SCR_PBURST_INCR4 (UINT32_C(1) << 21)
///< INCR4 (incremental burst of 4 beats)
2290
#define MCCI_STM32H7_DMA_SCR_PBURST_INCR8 (UINT32_C(2) << 21)
///< INCR8 (incremental burst of 8 beats)
2291
#define MCCI_STM32H7_DMA_SCR_PBURST_INCR16 (UINT32_C(3) << 21)
///< INCR16 (incremental burst of 16 beats)
2292
#define MCCI_STM32H7_DMA_SCR_TRBUFF (UINT32_C(1) << 20)
///< Enable the DMA to handle bufferable transfers
2293
#define MCCI_STM32H7_DMA_SCR_CT (UINT32_C(1) << 19)
///< current target (only in double-buffer mode)
2294
#define MCCI_STM32H7_DMA_SCR_DBM (UINT32_C(1) << 18)
///< double-buffer mode
2295
#define MCCI_STM32H7_DMA_SCR_PL (UINT32_C(3) << 16)
///< priority level
2296
#define MCCI_STM32H7_DMA_SCR_PL_LOW (UINT32_C(0) << 16)
///< low
2297
#define MCCI_STM32H7_DMA_SCR_PL_MEDIUM (UINT32_C(0) << 16)
///< medium
2298
#define MCCI_STM32H7_DMA_SCR_PL_HIGH (UINT32_C(0) << 16)
///< high
2299
#define MCCI_STM32H7_DMA_SCR_PL_VERY_HIGH (UINT32_C(0) << 16)
///< very high
2300
#define MCCI_STM32H7_DMA_SCR_PINCOS (UINT32_C(1) << 15)
///< peripheral increment offset size
2301
#define MCCI_STM32H7_DMA_SCR_MSIZE (UINT32_C(3) << 13)
///< memory data size
2302
#define MCCI_STM32H7_DMA_SCR_MSIZE_BYTE (UINT32_C(0) << 13)
///< byte (8-bit)
2303
#define MCCI_STM32H7_DMA_SCR_MSIZE_HALF (UINT32_C(1) << 13)
///< hlaf-word (16-bit)
2304
#define MCCI_STM32H7_DMA_SCR_MSIZE_WORD (UINT32_C(2) << 13)
///< word (32-bit)
2305
#define MCCI_STM32H7_DMA_SCR_PSIZE (UINT32_C(3) << 11)
///< peripheral data size
2306
#define MCCI_STM32H7_DMA_SCR_PSIZE_BYTE (UINT32_C(0) << 11)
///< byte (8-bit)
2307
#define MCCI_STM32H7_DMA_SCR_PSIZE_HALF (UINT32_C(1) << 11)
///< hlaf-word (16-bit)
2308
#define MCCI_STM32H7_DMA_SCR_PSIZE_WORD (UINT32_C(2) << 11)
///< word (32-bit)
2309
#define MCCI_STM32H7_DMA_SCR_MINC (UINT32_C(1) << 10)
///< memory increment mode
2310
#define MCCI_STM32H7_DMA_SCR_PINC (UINT32_C(1) << 9)
///< peripheral increment mode
2311
#define MCCI_STM32H7_DMA_SCR_CIRC (UINT32_C(1) << 8)
///< circular mode
2312
#define MCCI_STM32H7_DMA_SCR_DIR (UINT32_C(3) << 6)
///< data transfer direction
2313
#define MCCI_STM32H7_DMA_SCR_DIR_PERI_TO_MEM (UINT32_C(0) << 6)
///< peripheral-to-memory
2314
#define MCCI_STM32H7_DMA_SCR_DIR_MEM_TO_PERI (UINT32_C(1) << 6)
///< memory-to-peripheral
2315
#define MCCI_STM32H7_DMA_SCR_DIR_MEM_TO_MEM (UINT32_C(2) << 6)
///< memory-to-memory
2316
#define MCCI_STM32H7_DMA_SCR_PFCTRL (UINT32_C(1) << 5)
///< peripheral flow controller
2317
#define MCCI_STM32H7_DMA_SCR_TCIE (UINT32_C(1) << 4)
///< transfer complete interrupt enable
2318
#define MCCI_STM32H7_DMA_SCR_HTIE (UINT32_C(1) << 3)
///< half transfer interrupt enable
2319
#define MCCI_STM32H7_DMA_SCR_TEIE (UINT32_C(1) << 2)
///< transfer error interrupt enable
2320
#define MCCI_STM32H7_DMA_SCR_DMEIE (UINT32_C(1) << 1)
///< direct mode error interrupt enable
2321
#define MCCI_STM32H7_DMA_SCR_EN (UINT32_C(1) << 0)
///< stream enable / flag stream ready when read low
2322
/// @}
2323
2324
/// \name DMA_SFCR bits
2325
/// @{
2326
#define MCCI_STM32H7_DMA_SFCR_RSV8 UINT32_C(0xFFFFFF00)
///< reserved, don't change
2327
#define MCCI_STM32H7_DMA_SFCR_FEIE (UINT32_C(1) << 7)
///< FIFO error interrupt enable
2328
#define MCCI_STM32H7_DMA_SFCR_RSV6 (UINT32_C(1) << 6)
///< reserved, don't change
2329
#define MCCI_STM32H7_DMA_SFCR_FS (UINT32_C(7) << 3)
///< FIFO status
2330
#define MCCI_STM32H7_DMA_SFCR_FS_LESS_1P4 (UINT32_C(0) << 3)
///< 0 < fifo_level < 1/4
2331
#define MCCI_STM32H7_DMA_SFCR_FS_LESS_1P2 (UINT32_C(1) << 3)
///< 1/4 <= fifo_level < 1/2
2332
#define MCCI_STM32H7_DMA_SFCR_FS_LESS_3P4 (UINT32_C(2) << 3)
///< 1/2 <= fifo_level < 3/4
2333
#define MCCI_STM32H7_DMA_SFCR_FS_LESS_FULL (UINT32_C(3) << 3)
///< 3/4 <= fifo_level < full
2334
#define MCCI_STM32H7_DMA_SFCR_FS_EMPTY (UINT32_C(4) << 3)
///< FIFO is empty
2335
#define MCCI_STM32H7_DMA_SFCR_FS_FULL (UINT32_C(5) << 3)
///< FIFO is full
2336
#define MCCI_STM32H7_DMA_SFCR_DMDIS (UINT32_C(1) << 2)
///< direct mode disable
2337
#define MCCI_STM32H7_DMA_SFCR_FTH (UINT32_C(3) << 0)
///< FIFO threshold selection
2338
#define MCCI_STM32H7_DMA_SFCR_FTH_1P4_FULL (UINT32_C(0) << 0)
///< 1/4 full FIFO
2339
#define MCCI_STM32H7_DMA_SFCR_FTH_1P2_FULL (UINT32_C(1) << 0)
///< 1/4 full FIFO
2340
#define MCCI_STM32H7_DMA_SFCR_FTH_3P4_FULL (UINT32_C(2) << 0)
///< 1/4 full FIFO
2341
#define MCCI_STM32H7_DMA_SFCR_FTH_FULL (UINT32_C(3) << 0)
///< 1/4 full FIFO
2342
/// @}
2343
2344
2345
/****************************************************************************\
2346
|
2347
| DMAMUX Control Registers
2348
|
2349
\****************************************************************************/
2350
2351
/// \name DMAMUX offsets
2352
/// @{
2353
#define MCCI_STM32H7_DMAMUX1_C0CR UINT32_C(0x00)
///< offset to DMAMUX1 request line multiplexer channel 0 configuration register
2354
#define MCCI_STM32H7_DMAMUX1_C1CR UINT32_C(0x04)
///< offset to DMAMUX1 request line multiplexer channel 1 configuration register
2355
#define MCCI_STM32H7_DMAMUX1_C2CR UINT32_C(0x08)
///< offset to DMAMUX1 request line multiplexer channel 2 configuration register
2356
#define MCCI_STM32H7_DMAMUX1_C3CR UINT32_C(0x0C)
///< offset to DMAMUX1 request line multiplexer channel 3 configuration register
2357
#define MCCI_STM32H7_DMAMUX1_C4CR UINT32_C(0x10)
///< offset to DMAMUX1 request line multiplexer channel 4 configuration register
2358
#define MCCI_STM32H7_DMAMUX1_C5CR UINT32_C(0x14)
///< offset to DMAMUX1 request line multiplexer channel 5 configuration register
2359
#define MCCI_STM32H7_DMAMUX1_C6CR UINT32_C(0x18)
///< offset to DMAMUX1 request line multiplexer channel 6 configuration register
2360
#define MCCI_STM32H7_DMAMUX1_C7CR UINT32_C(0x1C)
///< offset to DMAMUX1 request line multiplexer channel 7 configuration register
2361
#define MCCI_STM32H7_DMAMUX1_C8CR UINT32_C(0x20)
///< offset to DMAMUX1 request line multiplexer channel 8 configuration register
2362
#define MCCI_STM32H7_DMAMUX1_C9CR UINT32_C(0x24)
///< offset to DMAMUX1 request line multiplexer channel 9 configuration register
2363
#define MCCI_STM32H7_DMAMUX1_C10CR UINT32_C(0x28)
///< offset to DMAMUX1 request line multiplexer channel 10 configuration register
2364
#define MCCI_STM32H7_DMAMUX1_C11CR UINT32_C(0x2C)
///< offset to DMAMUX1 request line multiplexer channel 11 configuration register
2365
#define MCCI_STM32H7_DMAMUX1_C12CR UINT32_C(0x30)
///< offset to DMAMUX1 request line multiplexer channel 12 configuration register
2366
#define MCCI_STM32H7_DMAMUX1_C13CR UINT32_C(0x34)
///< offset to DMAMUX1 request line multiplexer channel 13 configuration register
2367
#define MCCI_STM32H7_DMAMUX1_C14CR UINT32_C(0x38)
///< offset to DMAMUX1 request line multiplexer channel 14 configuration register
2368
#define MCCI_STM32H7_DMAMUX1_C15CR UINT32_C(0x3C)
///< offset to DMAMUX1 request line multiplexer channel 15 configuration register
2369
#define MCCI_STM32H7_DMAMUX1_CCR(x) ((x) * UINT32_C(0x04))
///< offset to DMAMUX1 request line multiplexer channel x configuration register
2370
2371
#define MCCI_STM32H7_DMAMUX2_C0CR UINT32_C(0x00)
///< offset to DMAMUX2 request line multiplexer channel 0 configuration register
2372
#define MCCI_STM32H7_DMAMUX2_C1CR UINT32_C(0x04)
///< offset to DMAMUX2 request line multiplexer channel 1 configuration register
2373
#define MCCI_STM32H7_DMAMUX2_C2CR UINT32_C(0x08)
///< offset to DMAMUX2 request line multiplexer channel 2 configuration register
2374
#define MCCI_STM32H7_DMAMUX2_C3CR UINT32_C(0x0C)
///< offset to DMAMUX2 request line multiplexer channel 3 configuration register
2375
#define MCCI_STM32H7_DMAMUX2_C4CR UINT32_C(0x10)
///< offset to DMAMUX2 request line multiplexer channel 4 configuration register
2376
#define MCCI_STM32H7_DMAMUX2_C5CR UINT32_C(0x14)
///< offset to DMAMUX2 request line multiplexer channel 5 configuration register
2377
#define MCCI_STM32H7_DMAMUX2_C6CR UINT32_C(0x18)
///< offset to DMAMUX2 request line multiplexer channel 6 configuration register
2378
#define MCCI_STM32H7_DMAMUX2_C7CR UINT32_C(0x1C)
///< offset to DMAMUX2 request line multiplexer channel 7 configuration register
2379
#define MCCI_STM32H7_DMAMUX2_CCR(x) ((x) * UINT32_C(0x04))
///< offset to DMAMUX2 request line multiplexer channel x configuration register
2380
2381
#define MCCI_STM32H7_DMAMUX1_CSR UINT32_C(0x80)
///< offset to DMAMUX1 request line multiplexer interrupt channel status register
2382
#define MCCI_STM32H7_DMAMUX2_CSR UINT32_C(0x80)
///< offset to DMAMUX2 request line multiplexer interrupt channel status register
2383
#define MCCI_STM32H7_DMAMUX1_CFR UINT32_C(0x84)
///< offset to DMAMUX1 request line multiplexer interrupt clear flag register
2384
#define MCCI_STM32H7_DMAMUX2_CFR UINT32_C(0x84)
///< offset to DMAMUX2 request line multiplexer interrupt clear flag register
2385
2386
#define MCCI_STM32H7_DMAMUX1_RG0CR UINT32_C(0x100)
///< offset to DMAMUX1 request generator channel 0 configuration register
2387
#define MCCI_STM32H7_DMAMUX1_RG1CR UINT32_C(0x104)
///< offset to DMAMUX1 request generator channel 1 configuration register
2388
#define MCCI_STM32H7_DMAMUX1_RG2CR UINT32_C(0x108)
///< offset to DMAMUX1 request generator channel 2 configuration register
2389
#define MCCI_STM32H7_DMAMUX1_RG3CR UINT32_C(0x10C)
///< offset to DMAMUX1 request generator channel 3 configuration register
2390
#define MCCI_STM32H7_DMAMUX1_RG4CR UINT32_C(0x110)
///< offset to DMAMUX1 request generator channel 4 configuration register
2391
#define MCCI_STM32H7_DMAMUX1_RG5CR UINT32_C(0x114)
///< offset to DMAMUX1 request generator channel 5 configuration register
2392
#define MCCI_STM32H7_DMAMUX1_RG6CR UINT32_C(0x118)
///< offset to DMAMUX1 request generator channel 6 configuration register
2393
#define MCCI_STM32H7_DMAMUX1_RG7CR UINT32_C(0x11C)
///< offset to DMAMUX1 request generator channel 7 configuration register
2394
#define MCCI_STM32H7_DMAMUX1_RGCR(x) (UINT32_C(0x100) + ((x) * UINT32_C(0x04)))
///< offset to DMAMUX1 request generator channel x configuration register
2395
2396
#define MCCI_STM32H7_DMAMUX2_RG0CR UINT32_C(0x100)
///< offset to DMAMUX2 request generator channel 0 configuration register
2397
#define MCCI_STM32H7_DMAMUX2_RG1CR UINT32_C(0x104)
///< offset to DMAMUX2 request generator channel 1 configuration register
2398
#define MCCI_STM32H7_DMAMUX2_RG2CR UINT32_C(0x108)
///< offset to DMAMUX2 request generator channel 2 configuration register
2399
#define MCCI_STM32H7_DMAMUX2_RG3CR UINT32_C(0x10C)
///< offset to DMAMUX2 request generator channel 3 configuration register
2400
#define MCCI_STM32H7_DMAMUX2_RG4CR UINT32_C(0x110)
///< offset to DMAMUX2 request generator channel 4 configuration register
2401
#define MCCI_STM32H7_DMAMUX2_RG5CR UINT32_C(0x114)
///< offset to DMAMUX2 request generator channel 5 configuration register
2402
#define MCCI_STM32H7_DMAMUX2_RG6CR UINT32_C(0x118)
///< offset to DMAMUX2 request generator channel 6 configuration register
2403
#define MCCI_STM32H7_DMAMUX2_RG7CR UINT32_C(0x11C)
///< offset to DMAMUX2 request generator channel 7 configuration register
2404
#define MCCI_STM32H7_DMAMUX2_RGCR(x) (UINT32_C(0x100) + ((x) * UINT32_C(0x04)))
///< offset to DMAMUX2 request generator channel x configuration register
2405
2406
#define MCCI_STM32H7_DMAMUX1_RGSR UINT32_C(0x140)
///< offset to DMAMUX1 request generator interrupt channel status register
2407
#define MCCI_STM32H7_DMAMUX2_RGSR UINT32_C(0x140)
///< offset to DMAMUX2 request generator interrupt channel status register
2408
#define MCCI_STM32H7_DMAMUX1_RGCFR UINT32_C(0x144)
///< offset to DMAMUX1 request generator interrupt clear flag register
2409
#define MCCI_STM32H7_DMAMUX2_RGCFR UINT32_C(0x144)
///< offset to DMAMUX2 request generator interrupt clear flag register
2410
/// @}
2411
2412
/// \name DMAMUX1_CxCR bits
2413
/// @{
2414
#define MCCI_STM32H7_DMAMUX1_CxCR_RSV27 UINT32_C(0xF8000000)
///< reserved, don't change
2415
#define MCCI_STM32H7_DMAMUX1_CxCR_SYNC_ID (UINT32_C(7) << 24)
///< Synchronization identification
2416
#define MCCI_STM32H7_DMAMUX1_CxCR_SYNC_ID_N(n) ((n) << 24)
///<
2417
#define MCCI_STM32H7_DMAMUX1_CxCR_NBREQ (UINT32_C(0x1F) << 19)
///< Number of DMA requests minus 1 to forward
2418
#define MCCI_STM32H7_DMAMUX1_CxCR_NBREQ_N(n) ((n) << 19)
///<
2419
#define MCCI_STM32H7_DMAMUX1_CxCR_SPOL (UINT32_C(3) << 17)
///< Synchronization polarity
2420
#define MCCI_STM32H7_DMAMUX1_CxCR_SPOL_NO (UINT32_C(0) << 17)
///< no event, i.e. no synchronization nor detection
2421
#define MCCI_STM32H7_DMAMUX1_CxCR_SPOL_RISING (UINT32_C(1) << 17)
///< rising edge
2422
#define MCCI_STM32H7_DMAMUX1_CxCR_SPOL_FALLING (UINT32_C(2) << 17)
///< falling edge
2423
#define MCCI_STM32H7_DMAMUX1_CxCR_SPOL_BOTH (UINT32_C(3) << 17)
///< rising and falling edges
2424
#define MCCI_STM32H7_DMAMUX1_CxCR_SE (UINT32_C(1) << 16)
///< Synchronization enable
2425
#define MCCI_STM32H7_DMAMUX1_CxCR_RSV10 (UINT32_C(0x3F) << 10)
///< reserved, don't change
2426
#define MCCI_STM32H7_DMAMUX1_CxCR_EGE (UINT32_C(1) << 9)
///< Event generation enable
2427
#define MCCI_STM32H7_DMAMUX1_CxCR_SOIE (UINT32_C(1) << 8)
///< Synchronization overrun interrupt enable
2428
#define MCCI_STM32H7_DMAMUX1_CxCR_RSV7 (UINT32_C(1) << 7)
///< reserved, don't change
2429
#define MCCI_STM32H7_DMAMUX1_CxCR_DMAREQ_ID (UINT32_C(0x7F) << 0)
///< DMA request identification
2430
#define MCCI_STM32H7_DMAMUX1_CxCR_DMAREQ_ID_N(n) ((n) << 0)
///<
2431
/// @}
2432
2433
/// \name DMAMUX2_CxCR bits
2434
/// @{
2435
#define MCCI_STM32H7_DMAMUX2_CxCR_RSV28 UINT32_C(0xF0000000)
///< reserved, don't change
2436
#define MCCI_STM32H7_DMAMUX2_CxCR_SYNC_ID (UINT32_C(0xF) << 24)
///< Synchronization identification
2437
#define MCCI_STM32H7_DMAMUX2_CxCR_SYNC_ID_N(n) ((n) << 24)
///<
2438
#define MCCI_STM32H7_DMAMUX2_CxCR_NBREQ (UINT32_C(0x1F) << 19)
///< Number of DMA requests minus 1 to forward
2439
#define MCCI_STM32H7_DMAMUX2_CxCR_NBREQ_N(n) ((n) << 19)
///<
2440
#define MCCI_STM32H7_DMAMUX2_CxCR_SPOL (UINT32_C(3) << 17)
///< Synchronization polarity
2441
#define MCCI_STM32H7_DMAMUX2_CxCR_SPOL_NO (UINT32_C(0) << 17)
///< no event, i.e. no synchronization nor detection
2442
#define MCCI_STM32H7_DMAMUX2_CxCR_SPOL_RISING (UINT32_C(1) << 17)
///< rising edge
2443
#define MCCI_STM32H7_DMAMUX2_CxCR_SPOL_FALLING (UINT32_C(2) << 17)
///< falling edge
2444
#define MCCI_STM32H7_DMAMUX2_CxCR_SPOL_BOTH (UINT32_C(3) << 17)
///< rising and falling edges
2445
#define MCCI_STM32H7_DMAMUX2_CxCR_SE (UINT32_C(1) << 16)
///< Synchronization enable
2446
#define MCCI_STM32H7_DMAMUX2_CxCR_RSV10 (UINT32_C(0x3F) << 10)
///< reserved, don't change
2447
#define MCCI_STM32H7_DMAMUX2_CxCR_EGE (UINT32_C(1) << 9)
///< Event generation enable
2448
#define MCCI_STM32H7_DMAMUX2_CxCR_SOIE (UINT32_C(1) << 8)
///< Synchronization overrun interrupt enable
2449
#define MCCI_STM32H7_DMAMUX2_CxCR_RSV7 (UINT32_C(7) << 5)
///< reserved, don't change
2450
#define MCCI_STM32H7_DMAMUX2_CxCR_DMAREQ_ID (UINT32_C(0x1F) << 0)
///< DMA request identification
2451
#define MCCI_STM32H7_DMAMUX2_CxCR_DMAREQ_ID_N(n) ((n) << 0)
///<
2452
/// @}
2453
2454
/// \name DMAMUX1_RGxCR bits
2455
/// @{
2456
#define MCCI_STM32H7_DMAMUX1_RGxCR_RSV24 UINT32_C(0xFF000000)
///< reserved, don't change
2457
#define MCCI_STM32H7_DMAMUX1_RGxCR_GNBREQ (UINT32_C(0x1F) << 19)
///< Number of DMA requests to be generated (minus 1)
2458
#define MCCI_STM32H7_DMAMUX1_RGxCR_GNBREQ_N(n) ((n) << 19)
///<
2459
#define MCCI_STM32H7_DMAMUX1_RGxCR_GPOL (UINT32_C(3) << 17)
///< DMA request generator trigger polarity
2460
#define MCCI_STM32H7_DMAMUX1_RGxCR_GPOL_NO (UINT32_C(0) << 17)
///< no event, i.e. no synchronization nor detection
2461
#define MCCI_STM32H7_DMAMUX1_RGxCR_GPOL_RISING (UINT32_C(1) << 17)
///< rising edge
2462
#define MCCI_STM32H7_DMAMUX1_RGxCR_GPOL_FALLING (UINT32_C(2) << 17)
///< falling edge
2463
#define MCCI_STM32H7_DMAMUX1_RGxCR_GPOL_BOTH (UINT32_C(3) << 17)
///< rising and falling edges
2464
#define MCCI_STM32H7_DMAMUX1_RGxCR_GE (UINT32_C(1) << 16)
///< DMA request generator channel x enable
2465
#define MCCI_STM32H7_DMAMUX1_RGxCR_RSV9 (UINT32_C(0x7F) << 9)
///< reserved, don't change
2466
#define MCCI_STM32H7_DMAMUX1_RGxCR_OIE (UINT32_C(1) << 8)
///< Trigger overrun interrupt enable
2467
#define MCCI_STM32H7_DMAMUX1_RGxCR_RSV3 (UINT32_C(0x1F) << 3)
///< reserved, don't change
2468
#define MCCI_STM32H7_DMAMUX1_RGxCR_SIG_ID (UINT32_C(7) << 0)
///< Signal identification
2469
#define MCCI_STM32H7_DMAMUX1_RGxCR_SIG_ID_N(n) ((n) << 0)
///<
2470
/// @}
2471
2472
/// \name DMAMUX2_RGxCR bits
2473
/// @{
2474
#define MCCI_STM32H7_DMAMUX2_RGxCR_RSV24 UINT32_C(0xFF000000)
///< reserved, don't change
2475
#define MCCI_STM32H7_DMAMUX2_RGxCR_GNBREQ (UINT32_C(0x1F) << 19)
///< Number of DMA requests to be generated (minus 1)
2476
#define MCCI_STM32H7_DMAMUX2_RGxCR_GNBREQ_N(n) ((n) << 19)
///<
2477
#define MCCI_STM32H7_DMAMUX2_RGxCR_GPOL (UINT32_C(3) << 17)
///< DMA request generator trigger polarity
2478
#define MCCI_STM32H7_DMAMUX2_RGxCR_GPOL_NO (UINT32_C(0) << 17)
///< no event, i.e. no synchronization nor detection
2479
#define MCCI_STM32H7_DMAMUX2_RGxCR_GPOL_RISING (UINT32_C(1) << 17)
///< rising edge
2480
#define MCCI_STM32H7_DMAMUX2_RGxCR_GPOL_FALLING (UINT32_C(2) << 17)
///< falling edge
2481
#define MCCI_STM32H7_DMAMUX2_RGxCR_GPOL_BOTH (UINT32_C(3) << 17)
///< rising and falling edges
2482
#define MCCI_STM32H7_DMAMUX2_RGxCR_GE (UINT32_C(1) << 16)
///< DMA request generator channel x enable
2483
#define MCCI_STM32H7_DMAMUX2_RGxCR_RSV9 (UINT32_C(0x7F) << 9)
///< reserved, don't change
2484
#define MCCI_STM32H7_DMAMUX2_RGxCR_OIE (UINT32_C(1) << 8)
///< Trigger overrun interrupt enable
2485
#define MCCI_STM32H7_DMAMUX2_RGxCR_RSV5 (UINT32_C(7) << 5)
///< reserved, don't change
2486
#define MCCI_STM32H7_DMAMUX2_RGxCR_SIG_ID (UINT32_C(0x1F) << 0)
///< Signal identification
2487
#define MCCI_STM32H7_DMAMUX2_RGxCR_SIG_ID_N(n) ((n) << 0)
///<
2488
/// @}
2489
2490
2491
/****************************************************************************\
2492
|
2493
| DCMI Control Registers
2494
|
2495
\****************************************************************************/
2496
2497
/// \name DCMI offsets
2498
/// @{
2499
#define MCCI_STM32H7_DCMI_CR UINT32_C(0x00)
///< offset to DCMI control register
2500
#define MCCI_STM32H7_DCMI_SR UINT32_C(0x04)
///< offset to DCMI status register
2501
#define MCCI_STM32H7_DCMI_RIS UINT32_C(0x08)
///< offset to DCMI raw interrupt status register
2502
#define MCCI_STM32H7_DCMI_IER UINT32_C(0x0C)
///< offset to DCMI interrupt enable register
2503
#define MCCI_STM32H7_DCMI_MIS UINT32_C(0x10)
///< offset to DCMI masked interrupt status register
2504
#define MCCI_STM32H7_DCMI_ICR UINT32_C(0x14)
///< offset to DCMI interrupt clear register
2505
#define MCCI_STM32H7_DCMI_ESCR UINT32_C(0x18)
///< offset to DCMI embedded synchronization code register
2506
#define MCCI_STM32H7_DCMI_ESUR UINT32_C(0x1C)
///< offset to DCMI embedded synchronization unmask register
2507
#define MCCI_STM32H7_DCMI_CWSTRT UINT32_C(0x20)
///< offset to DCMI crop window start
2508
#define MCCI_STM32H7_DCMI_CWSIZE UINT32_C(0x24)
///< offset to DCMI crop window size
2509
#define MCCI_STM32H7_DCMI_DR UINT32_C(0x28)
///< offset to DCMI data register
2510
/// @}
2511
2512
/// \name DCMI_CR bits
2513
/// @{
2514
#define MCCI_STM32H7_DCMI_CR_RSV21 UINT32_C(0xFFE00000)
///< reserved, don't change
2515
#define MCCI_STM32H7_DCMI_CR_OELS (UINT32_C(1) << 20)
///< Odd/Even Line Select (Line Select Start)
2516
#define MCCI_STM32H7_DCMI_CR_LSM (UINT32_C(1) << 19)
///< Line Select mode
2517
#define MCCI_STM32H7_DCMI_CR_OEBS (UINT32_C(1) << 18)
///< Odd/Even Byte Select (Byte Select Start)
2518
#define MCCI_STM32H7_DCMI_CR_BSM (UINT32_C(3) << 16)
///< Byte Select mode
2519
#define MCCI_STM32H7_DCMI_CR_BSM_N(n) ((n) << 16)
///<
2520
#define MCCI_STM32H7_DCMI_CR_RSV15 (UINT32_C(1) << 15)
///< reserved, don't change
2521
#define MCCI_STM32H7_DCMI_CR_ENABLE (UINT32_C(1) << 14)
///< DCMI enable
2522
#define MCCI_STM32H7_DCMI_CR_RSV12 (UINT32_C(3) << 12)
///< reserved, don't change
2523
#define MCCI_STM32H7_DCMI_CR_EDM (UINT32_C(3) << 10)
///< Extended data mode
2524
#define MCCI_STM32H7_DCMI_CR_EDM_N(n) ((n) << 10)
///<
2525
#define MCCI_STM32H7_DCMI_CR_FCRC (UINT32_C(3) << 8)
///< Frame capture rate control
2526
#define MCCI_STM32H7_DCMI_CR_FCRC_N(n) ((n) << 8)
///<
2527
#define MCCI_STM32H7_DCMI_CR_VSPOL (UINT32_C(1) << 7)
///< Vertical synchronization polarity
2528
#define MCCI_STM32H7_DCMI_CR_HSPOL (UINT32_C(1) << 6)
///< Horizontal synchronization polarity
2529
#define MCCI_STM32H7_DCMI_CR_PCKPOL (UINT32_C(1) << 5)
///< Pixel clock polarity
2530
#define MCCI_STM32H7_DCMI_CR_ESS (UINT32_C(1) << 4)
///< Embedded synchronization select
2531
#define MCCI_STM32H7_DCMI_CR_JPEG (UINT32_C(1) << 3)
///< JPEG format
2532
#define MCCI_STM32H7_DCMI_CR_CROP (UINT32_C(1) << 2)
///< Crop feature
2533
#define MCCI_STM32H7_DCMI_CR_CM (UINT32_C(1) << 1)
///< Capture mode
2534
#define MCCI_STM32H7_DCMI_CR_CAPTURE (UINT32_C(1) << 0)
///< Capture enable
2535
/// @}
2536
2537
/// \name DCMI_SR bits
2538
/// @{
2539
#define MCCI_STM32H7_DCMI_SR_RSV3 UINT32_C(0xFFFFFFF8)
///< reserved, don't change
2540
#define MCCI_STM32H7_DCMI_SR_FNE (UINT32_C(1) << 2)
///< FIFO not empty
2541
#define MCCI_STM32H7_DCMI_SR_VSYNC (UINT32_C(1) << 1)
///< Vertical synchronization
2542
#define MCCI_STM32H7_DCMI_SR_HSYNC (UINT32_C(1) << 0)
///< Horizontal synchronization
2543
/// @}
2544
2545
/// \name DCMI_RIS bits
2546
/// @{
2547
#define MCCI_STM32H7_DCMI_RIS_RSV5 UINT32_C(0xFFFFFFE0)
///< reserved, don't change
2548
#define MCCI_STM32H7_DCMI_RIS_LINE (UINT32_C(1) << 4)
///< Line raw interrupt status
2549
#define MCCI_STM32H7_DCMI_RIS_VSYNC (UINT32_C(1) << 3)
///< DCMI_VSYNC raw interrupt status
2550
#define MCCI_STM32H7_DCMI_RIS_ERR (UINT32_C(1) << 2)
///< Synchronization error raw interrupt status
2551
#define MCCI_STM32H7_DCMI_RIS_OVR (UINT32_C(1) << 1)
///< Overrun raw interrupt status
2552
#define MCCI_STM32H7_DCMI_RIS_FRAME (UINT32_C(1) << 0)
///< Capture complete raw interrupt status
2553
/// @}
2554
2555
/// \name DCMI_IER bits
2556
/// @{
2557
#define MCCI_STM32H7_DCMI_IER_RSV5 UINT32_C(0xFFFFFFE0)
///< reserved, don't change
2558
#define MCCI_STM32H7_DCMI_IER_LINE (UINT32_C(1) << 4)
///< Line interrupt enable
2559
#define MCCI_STM32H7_DCMI_IER_VSYNC (UINT32_C(1) << 3)
///< DCMI_VSYNC interrupt enable
2560
#define MCCI_STM32H7_DCMI_IER_ERR (UINT32_C(1) << 2)
///< Synchronization interrupt enable
2561
#define MCCI_STM32H7_DCMI_IER_OVR (UINT32_C(1) << 1)
///< Overrun interrupt enable
2562
#define MCCI_STM32H7_DCMI_IER_FRAME (UINT32_C(1) << 0)
///< Capture complete interrupt enable
2563
/// @}
2564
2565
/// \name DCMI_MIS bits
2566
/// @{
2567
#define MCCI_STM32H7_DCMI_MIS_RSV5 UINT32_C(0xFFFFFFE0)
///< reserved, don't change
2568
#define MCCI_STM32H7_DCMI_MIS_LINE (UINT32_C(1) << 4)
///< Line maskedinterrupt status
2569
#define MCCI_STM32H7_DCMI_MIS_VSYNC (UINT32_C(1) << 3)
///< DCMI_VSYNC maskedinterrupt status
2570
#define MCCI_STM32H7_DCMI_MIS_ERR (UINT32_C(1) << 2)
///< Synchronization maskedinterrupt status
2571
#define MCCI_STM32H7_DCMI_MIS_OVR (UINT32_C(1) << 1)
///< Overrun maskedinterrupt status
2572
#define MCCI_STM32H7_DCMI_MIS_FRAME (UINT32_C(1) << 0)
///< Capture complete maskedinterrupt status
2573
/// @}
2574
2575
/// \name DCMI_ICR bits
2576
/// @{
2577
#define MCCI_STM32H7_DCMI_ICR_RSV5 UINT32_C(0xFFFFFFE0)
///< reserved, don't change
2578
#define MCCI_STM32H7_DCMI_ICR_LINE (UINT32_C(1) << 4)
///< Line interrupt status clear
2579
#define MCCI_STM32H7_DCMI_ICR_VSYNC (UINT32_C(1) << 3)
///< DCMI_VSYNC interrupt status clear
2580
#define MCCI_STM32H7_DCMI_ICR_ERR (UINT32_C(1) << 2)
///< Synchronization raw interrupt status clear
2581
#define MCCI_STM32H7_DCMI_ICR_OVR (UINT32_C(1) << 1)
///< Overrun interrupt status clear
2582
#define MCCI_STM32H7_DCMI_ICR_FRAME (UINT32_C(1) << 0)
///< Capture complete interrupt status clear
2583
/// @}
2584
2585
/// \name DCMI_ESCR bits
2586
/// @{
2587
#define MCCI_STM32H7_DCMI_ESCR_FEC (UINT32_C(0xFF) << 24)
///< Frame end delimiter code
2588
#define MCCI_STM32H7_DCMI_ESCR_FEC_N(n) ((n) << 24)
///<
2589
#define MCCI_STM32H7_DCMI_ESCR_LEC (UINT32_C(0xFF) << 16)
///< Line end delimiter code
2590
#define MCCI_STM32H7_DCMI_ESCR_LEC_N(n) ((n) << 16)
///<
2591
#define MCCI_STM32H7_DCMI_ESCR_LSC (UINT32_C(0xFF) << 8)
///< Line start delimiter code
2592
#define MCCI_STM32H7_DCMI_ESCR_LSC_N(n) ((n) << 8)
///<
2593
#define MCCI_STM32H7_DCMI_ESCR_FSC (UINT32_C(0xFF) << 0)
///< Frame start delimiter code
2594
#define MCCI_STM32H7_DCMI_ESCR_FSC_N(n) ((n) << 0)
///<
2595
/// @}
2596
2597
/// \name DCMI_ESUR bits
2598
/// @{
2599
#define MCCI_STM32H7_DCMI_ESUR_FEU (UINT32_C(0xFF) << 24)
///< Frame end delimiter unmask
2600
#define MCCI_STM32H7_DCMI_ESUR_FEU_N(n) ((n) << 24)
///<
2601
#define MCCI_STM32H7_DCMI_ESUR_LEU (UINT32_C(0xFF) << 16)
///< Line end delimiter unmask
2602
#define MCCI_STM32H7_DCMI_ESUR_LEU_N(n) ((n) << 16)
///<
2603
#define MCCI_STM32H7_DCMI_ESUR_LSU (UINT32_C(0xFF) << 8)
///< Line start delimiter unmask
2604
#define MCCI_STM32H7_DCMI_ESUR_LSU_N(n) ((n) << 8)
///<
2605
#define MCCI_STM32H7_DCMI_ESUR_FSU (UINT32_C(0xFF) << 0)
///< Frame start delimiter unmask
2606
#define MCCI_STM32H7_DCMI_ESUR_FSU_N(n) ((n) << 0)
///<
2607
/// @}
2608
2609
/// \name DCMI_CWSTRT bits
2610
/// @{
2611
#define MCCI_STM32H7_DCMI_CWSTRT_RSV29 (UINT32_C(7) << 29)
///< reserved, don't change
2612
#define MCCI_STM32H7_DCMI_CWSTRT_VST (UINT32_C(0x1FFF) << 16)
///< Vertical start line count
2613
#define MCCI_STM32H7_DCMI_CWSTRT_VST_N(n) ((n) << 16)
///<
2614
#define MCCI_STM32H7_DCMI_CWSTRT_RSV14 (UINT32_C(3) << 14)
///< reserved, don't change
2615
#define MCCI_STM32H7_DCMI_CWSTRT_HOFFCNT (UINT32_C(0x3FFF) << 0)
///< Horizontal offset count
2616
#define MCCI_STM32H7_DCMI_CWSTRT_HOFFCNT_N(n) ((n) << 0)
///<
2617
/// @}
2618
2619
/// \name DCMI_CWSIZE bits
2620
/// @{
2621
#define MCCI_STM32H7_DCMI_CWSIZE_RSV30 (UINT32_C(3) << 30)
///< reserved, don't change
2622
#define MCCI_STM32H7_DCMI_CWSIZE_VLINE (UINT32_C(0x3FFF) << 16)
///< Vertical line count
2623
#define MCCI_STM32H7_DCMI_CWSIZE_VLINE_N(n) ((n) << 16)
///<
2624
#define MCCI_STM32H7_DCMI_CWSIZE_RSV14 (UINT32_C(3) << 14)
///< reserved, don't change
2625
#define MCCI_STM32H7_DCMI_CWSIZE_CAPCNT (UINT32_C(0x3FFF) << 0)
///< Capture count
2626
#define MCCI_STM32H7_DCMI_CWSIZE_CAPCNT_N(n) ((n) << 0)
///<
2627
/// @}
2628
2629
2630
/****************************************************************************\
2631
|
2632
| I2C Control Registers
2633
|
2634
\****************************************************************************/
2635
2636
/// \name I2C offsets
2637
/// @{
2638
#define MCCI_STM32H7_I2C_CR1 UINT32_C(0x00)
///< offset to I2C control register 1
2639
#define MCCI_STM32H7_I2C_CR2 UINT32_C(0x04)
///< offset to I2C control register 2
2640
#define MCCI_STM32H7_I2C_OAR1 UINT32_C(0x08)
///< offset to I2C own address 1 register
2641
#define MCCI_STM32H7_I2C_OAR2 UINT32_C(0x0C)
///< offset to I2C own address 2 register
2642
#define MCCI_STM32H7_I2C_TIMINGR UINT32_C(0x10)
///< offset to I2C timing register
2643
#define MCCI_STM32H7_I2C_TIMOUTR UINT32_C(0x14)
///< offset to I2C timeout register
2644
#define MCCI_STM32H7_I2C_ISR UINT32_C(0x18)
///< offset to I2C interrupt and status register
2645
#define MCCI_STM32H7_I2C_ICR UINT32_C(0x1C)
///< offset to I2C interrupt clear register
2646
#define MCCI_STM32H7_I2C_PECR UINT32_C(0x20)
///< offset to I2C PEC register
2647
#define MCCI_STM32H7_I2C_RXDR UINT32_C(0x24)
///< offset to I2C receive data register
2648
#define MCCI_STM32H7_I2C_TXDR UINT32_C(0x28)
///< offset to I2C transmit data register
2649
/// @}
2650
2651
/// \name I2C_CR1 bits
2652
/// @{
2653
#define MCCI_STM32H7_I2C_CR1_RSV24 UINT32_C(0xFF000000)
///< reserved, don't change
2654
#define MCCI_STM32H7_I2C_CR1_PECEN (UINT32_C(1) << 23)
///< PEC enable
2655
#define MCCI_STM32H7_I2C_CR1_ALERTEN (UINT32_C(1) << 22)
///< SMBus alert enable
2656
#define MCCI_STM32H7_I2C_CR1_SMBDEN (UINT32_C(1) << 21)
///< SMBus Device Default Address enable
2657
#define MCCI_STM32H7_I2C_CR1_SMBHEN (UINT32_C(1) << 20)
///< SMBus Host Address enable
2658
#define MCCI_STM32H7_I2C_CR1_GCEN (UINT32_C(1) << 19)
///< General call enable
2659
#define MCCI_STM32H7_I2C_CR1_WUPEN (UINT32_C(1) << 18)
///< Wakeup from Stop mode enable
2660
#define MCCI_STM32H7_I2C_CR1_NOSTRETCH (UINT32_C(1) << 17)
///< Clock stretching disable
2661
#define MCCI_STM32H7_I2C_CR1_SBC (UINT32_C(1) << 16)
///< Slave byte control
2662
#define MCCI_STM32H7_I2C_CR1_RXDMAEN (UINT32_C(1) << 15)
///< DMA reception requests enable
2663
#define MCCI_STM32H7_I2C_CR1_TXDMAEN (UINT32_C(1) << 14)
///< DMA transmission requests enable
2664
#define MCCI_STM32H7_I2C_CR1_RSV13 (UINT32_C(1) << 13)
///< reserved, don't change
2665
#define MCCI_STM32H7_I2C_CR1_ANFOFF (UINT32_C(1) << 12)
///< Analog noise filter OFF
2666
#define MCCI_STM32H7_I2C_CR1_DNF (UINT32_C(0xF) << 8)
///< Digital noise filter
2667
#define MCCI_STM32H7_I2C_CR1_DNF_N(n) ((n) << 8)
///<
2668
#define MCCI_STM32H7_I2C_CR1_ERRIE (UINT32_C(1) << 7)
///< Error interrupts enable
2669
#define MCCI_STM32H7_I2C_CR1_TCIE (UINT32_C(1) << 6)
///< Transfer Complete interrupt enable
2670
#define MCCI_STM32H7_I2C_CR1_STOPIE (UINT32_C(1) << 5)
///< Stop detection Interrupt enable
2671
#define MCCI_STM32H7_I2C_CR1_NACKIE (UINT32_C(1) << 4)
///< Not acknowledge received Interrupt enable
2672
#define MCCI_STM32H7_I2C_CR1_ADDRIE (UINT32_C(1) << 3)
///< Address match Interrupt enable (slave only)
2673
#define MCCI_STM32H7_I2C_CR1_RXIE (UINT32_C(1) << 2)
///< RX Interrupt enable
2674
#define MCCI_STM32H7_I2C_CR1_TXIE (UINT32_C(1) << 1)
///< TX Interrupt enable
2675
#define MCCI_STM32H7_I2C_CR1_PE (UINT32_C(1) << 0)
///< Peripheral enable
2676
/// @}
2677
2678
/// \name I2C_CR2 bits
2679
/// @{
2680
#define MCCI_STM32H7_I2C_CR2_RSV27 UINT32_C(0xF8000000)
///< reserved, don't change
2681
#define MCCI_STM32H7_I2C_CR2_PECBYTE (UINT32_C(1) << 26)
///< Packet error checking byte
2682
#define MCCI_STM32H7_I2C_CR2_AUTOEND (UINT32_C(1) << 25)
///< Automatic end mode (master mode)
2683
#define MCCI_STM32H7_I2C_CR2_RELOAD (UINT32_C(1) << 24)
///< NBYTES reload mode
2684
#define MCCI_STM32H7_I2C_CR2_NBYTES (UINT32_C(0xFF) << 16)
///< Number of bytes
2685
#define MCCI_STM32H7_I2C_CR2_NBYTES_N(n) ((n) << 16)
///<
2686
#define MCCI_STM32H7_I2C_CR2_NACK (UINT32_C(1) << 15)
///< NACK generation (slave mode)
2687
#define MCCI_STM32H7_I2C_CR2_STOP (UINT32_C(1) << 14)
///< Stop generation (master mode)
2688
#define MCCI_STM32H7_I2C_CR2_START (UINT32_C(1) << 13)
///< Start generation
2689
#define MCCI_STM32H7_I2C_CR2_HEAD10R (UINT32_C(1) << 12)
///< 10-bit address header only read direction (master receiver mode)
2690
#define MCCI_STM32H7_I2C_CR2_ADD10 (UINT32_C(1) << 11)
///< 10-bit addressing mode (master mode)
2691
#define MCCI_STM32H7_I2C_CR2_RD_WRN (UINT32_C(1) << 10)
///< Transfer direction (master mode)
2692
#define MCCI_STM32H7_I2C_CR2_SADD (UINT32_C(0x3FF) << 0)
///< Slave address (master mode)
2693
#define MCCI_STM32H7_I2C_CR2_SADD_N(n) ((n) << 0)
///<
2694
/// @}
2695
2696
/// \name I2C_OAR1 bits
2697
/// @{
2698
#define MCCI_STM32H7_I2C_OAR1_RSV16 UINT32_C(0xFFFF0000)
///< reserved, don't change
2699
#define MCCI_STM32H7_I2C_OAR1_OA1EN (UINT32_C(1) << 15)
///< Own Address 1 enable
2700
#define MCCI_STM32H7_I2C_OAR1_RSV11 (UINT32_C(0xF) << 11)
///< reserved, don't change
2701
#define MCCI_STM32H7_I2C_OAR1_OA1MODE (UINT32_C(1) << 10)
///< Own Address 1 10-bit mode
2702
#define MCCI_STM32H7_I2C_OAR1_OA1 (UINT32_C(0x3FF) << 0)
///< Interface own slave address
2703
#define MCCI_STM32H7_I2C_OAR1_OA1_N(n) ((n) << 0)
///<
2704
/// @}
2705
2706
/// \name I2C_OAR2 bits
2707
/// @{
2708
#define MCCI_STM32H7_I2C_OAR2_RSV16 UINT32_C(0xFFFF0000)
///< reserved, don't change
2709
#define MCCI_STM32H7_I2C_OAR2_OA2EN (UINT32_C(1) << 15)
///< Own Address 2 enable
2710
#define MCCI_STM32H7_I2C_OAR2_RSV11 (UINT32_C(0xF) << 11)
///< reserved, don't change
2711
#define MCCI_STM32H7_I2C_OAR2_OA2MSK (UINT32_C(7) << 8)
///< Own Address 2 masks
2712
#define MCCI_STM32H7_I2C_OAR2_OA2MSK_N(n) ((n) << 8)
///<
2713
#define MCCI_STM32H7_I2C_OAR2_OA2 (UINT32_C(0xFF) << 0)
///< Interface address
2714
#define MCCI_STM32H7_I2C_OAR2_OA2_N(n) ((n) << 0)
///<
2715
/// @}
2716
2717
/// \name I2C_TIMINGR bits
2718
/// @{
2719
#define MCCI_STM32H7_I2C_TIMINGR_PRESC (UINT32_C(0xF) << 28)
///< Timing prescaler
2720
#define MCCI_STM32H7_I2C_TIMINGR_PRESC_N(n) ((n) << 28)
///<
2721
#define MCCI_STM32H7_I2C_TIMINGR_RSV24 (UINT32_C(0xF) << 24)
///< reserved, don't change
2722
#define MCCI_STM32H7_I2C_TIMINGR_SCLDEL (UINT32_C(0xF) << 20)
///< Data setup time
2723
#define MCCI_STM32H7_I2C_TIMINGR_SCLDEL_N(n) ((n) << 20)
///<
2724
#define MCCI_STM32H7_I2C_TIMINGR_SDADEL (UINT32_C(0xF) << 16)
///< Data hold time
2725
#define MCCI_STM32H7_I2C_TIMINGR_SDADEL_N(n) ((n) << 16)
///<
2726
#define MCCI_STM32H7_I2C_TIMINGR_SCLH (UINT32_C(0xFF) << 8)
///< SCL high period (master mode)
2727
#define MCCI_STM32H7_I2C_TIMINGR_SCLH_N(n) ((n) << 8)
///<
2728
#define MCCI_STM32H7_I2C_TIMINGR_SCLL (UINT32_C(0xFF) << 0)
///< SCL low period (master mode)
2729
#define MCCI_STM32H7_I2C_TIMINGR_SCLL_N(n) ((n) << 0)
///<
2730
/// @}
2731
2732
/// \name I2C_TIMEOUTR bits
2733
/// @{
2734
#define MCCI_STM32H7_I2C_TIMEOUTR_TEXTEN (UINT32_C(1) << 31)
///< Extended clock timeout enable
2735
#define MCCI_STM32H7_I2C_TIMEOUTR_RSV28 (UINT32_C(7) << 28)
///< reserved, don't change
2736
#define MCCI_STM32H7_I2C_TIMEOUTR_TIMEOUTB (UINT32_C(0xFFF) << 16)
///< Bus timeout B
2737
#define MCCI_STM32H7_I2C_TIMEOUTR_TIMEOUTB_N(n) ((n) << 16)
///<
2738
#define MCCI_STM32H7_I2C_TIMEOUTR_TIMOUTEN (UINT32_C(1) << 15)
///< Clock timeout enable
2739
#define MCCI_STM32H7_I2C_TIMINGR_RSV13 (UINT32_C(3) << 13)
///< reserved, don't change
2740
#define MCCI_STM32H7_I2C_TIMEOUTR_TIDLE (UINT32_C(1) << 12)
///< Idle clock timeout detection
2741
#define MCCI_STM32H7_I2C_TIMEOUTR_TIMEOUTA (UINT32_C(0xFFF) << 0)
///< Bus Timeout A
2742
#define MCCI_STM32H7_I2C_TIMEOUTR_TIMEOUTA_N(n) ((n) << 0)
///<
2743
/// @}
2744
2745
/// \name I2C_ISR bits
2746
/// @{
2747
#define MCCI_STM32H7_I2C_ISR_RSV24 UINT32_C(0xFF000000)
///< reserved, don't change
2748
#define MCCI_STM32H7_I2C_ISR_ADDCODE (UINT32_C(0x7F) << 17)
///< Address match code (Slave mode)
2749
#define MCCI_STM32H7_I2C_ISR_DIR (UINT32_C(1) << 16)
///< Transfer direction (Slave mode)
2750
#define MCCI_STM32H7_I2C_ISR_BUSY (UINT32_C(1) << 15)
///< Bus busy
2751
#define MCCI_STM32H7_I2C_ISR_RSV14 (UINT32_C(1) << 14)
///< reserved, don't change
2752
#define MCCI_STM32H7_I2C_ISR_ALERT (UINT32_C(1) << 13)
///< SMBus alert
2753
#define MCCI_STM32H7_I2C_ISR_TIMEOUT (UINT32_C(1) << 12)
///< Timeout or tLOW detection flag
2754
#define MCCI_STM32H7_I2C_ISR_PECERR (UINT32_C(1) << 11)
///< PEC Error in reception
2755
#define MCCI_STM32H7_I2C_ISR_OVR (UINT32_C(1) << 10)
///< Overrun/Underrun (slave mode)
2756
#define MCCI_STM32H7_I2C_ISR_ARLO (UINT32_C(1) << 9)
///< Arbitration lost
2757
#define MCCI_STM32H7_I2C_ISR_BERR (UINT32_C(1) << 8)
///< Bus error
2758
#define MCCI_STM32H7_I2C_ISR_TCR (UINT32_C(1) << 7)
///< Transfer Complete Reload
2759
#define MCCI_STM32H7_I2C_ISR_TC (UINT32_C(1) << 6)
///< Transfer Complete (master mode)
2760
#define MCCI_STM32H7_I2C_ISR_STOPF (UINT32_C(1) << 5)
///< Stop detection flag
2761
#define MCCI_STM32H7_I2C_ISR_NACKF (UINT32_C(1) << 4)
///< Not Acknowledge received flag
2762
#define MCCI_STM32H7_I2C_ISR_ADDR (UINT32_C(1) << 3)
///< Address matched (slave mode)
2763
#define MCCI_STM32H7_I2C_ISR_RXNE (UINT32_C(1) << 2)
///< Receive data register not empty (receivers)
2764
#define MCCI_STM32H7_I2C_ISR_TXIS (UINT32_C(1) << 1)
///< Transmit interrupt status (transmitters)
2765
#define MCCI_STM32H7_I2C_ISR_TXE (UINT32_C(1) << 0)
///< Transmit data register empty (transmitters)
2766
/// @}
2767
2768
/// \name I2C_ICR bits
2769
/// @{
2770
#define MCCI_STM32H7_I2C_ICR_RSV14 UINT32_C(0xFFFFC000)
///< reserved, don't change
2771
#define MCCI_STM32H7_I2C_ICR_ALERTCF (UINT32_C(1) << 13)
///< Alert flag clear
2772
#define MCCI_STM32H7_I2C_ICR_TIMEOUTCF (UINT32_C(1) << 12)
///< Timeout detection flag clear
2773
#define MCCI_STM32H7_I2C_ICR_PECCF (UINT32_C(1) << 11)
///< PEC Error flag clear
2774
#define MCCI_STM32H7_I2C_ICR_OVRCF (UINT32_C(1) << 10)
///< Overrun/Underrun flag clear
2775
#define MCCI_STM32H7_I2C_ICR_ARLOCF (UINT32_C(1) << 9)
///< Arbitration lost flag clear
2776
#define MCCI_STM32H7_I2C_ICR_BERRCF (UINT32_C(1) << 8)
///< Bus error flag clear
2777
#define MCCI_STM32H7_I2C_ICR_RSV6 (UINT32_C(3) << 6)
///< reserved, don't change
2778
#define MCCI_STM32H7_I2C_ICR_STOPCF (UINT32_C(1) << 5)
///< STOP detection flag clear
2779
#define MCCI_STM32H7_I2C_ICR_NACKCF (UINT32_C(1) << 4)
///< Not Acknowledge flag clear
2780
#define MCCI_STM32H7_I2C_ICR_ADDRCF (UINT32_C(1) << 3)
///< Address matched flag clear
2781
#define MCCI_STM32H7_I2C_ICR_RSV0 (UINT32_C(7) << 0)
///< reserved, don't change
2782
/// @}
2783
2784
/// \name I2C_PECR bits
2785
/// @{
2786
#define MCCI_STM32H7_I2C_PECR_RSV8 UINT32_C(0xFFFFFF00)
///< reserved, don't change
2787
#define MCCI_STM32H7_I2C_PECR_PEC (UINT32_C(0xFF) << 0)
///< Packet error checking register
2788
/// @}
2789
2790
/// \name I2C_RXDR bits
2791
/// @{
2792
#define MCCI_STM32H7_I2C_RXDR_RSV8 UINT32_C(0xFFFFFF00)
///< reserved, don't change
2793
#define MCCI_STM32H7_I2C_RXDR_RXDATA (UINT32_C(0xFF) << 0)
///< 8-bit receive data
2794
/// @}
2795
2796
/// \name I2C_TXDR bits
2797
/// @{
2798
#define MCCI_STM32H7_I2C_TXDR_RSV8 UINT32_C(0xFFFFFF00)
///< reserved, don't change
2799
#define MCCI_STM32H7_I2C_TXDR_TXDATA (UINT32_C(0xFF) << 0)
///< 8-bit transmit data
2800
/// @}
2801
2802
2803
/****************************************************************************\
2804
|
2805
| Timer Control Registers
2806
|
2807
\****************************************************************************/
2808
2809
/// \name Timer offsets
2810
/// @{
2811
#define MCCI_STM32H7_TIM_CR1 UINT32_C(0x00)
///< offset to TIM control register 1
2812
#define MCCI_STM32H7_TIM_CR2 UINT32_C(0x04)
///< offset to TIM control register 2
2813
#define MCCI_STM32H7_TIM_SMCR UINT32_C(0x08)
///< offset to TIM slave mode control register
2814
#define MCCI_STM32H7_TIM_DIER UINT32_C(0x0C)
///< offset to TIM DMA/interrupt enable register
2815
#define MCCI_STM32H7_TIM_SR UINT32_C(0x10)
///< offset to TIM status register
2816
#define MCCI_STM32H7_TIM_EGR UINT32_C(0x14)
///< offset to TIM event generation register
2817
#define MCCI_STM32H7_TIM_CCMR1 UINT32_C(0x18)
///< offset to TIM capture/compare mode register 1
2818
#define MCCI_STM32H7_TIM_CCMR2 UINT32_C(0x1C)
///< offset to TIM capture/compare mode register 2
2819
#define MCCI_STM32H7_TIM_CCER UINT32_C(0x20)
///< offset to TIM capture/compare enable register
2820
#define MCCI_STM32H7_TIM_CNT UINT32_C(0x24)
///< offset to TIM counter register
2821
#define MCCI_STM32H7_TIM_PSC UINT32_C(0x28)
///< offset to TIM prescaler register
2822
#define MCCI_STM32H7_TIM_ARR UINT32_C(0x2C)
///< offset to TIM auto-reload register
2823
#define MCCI_STM32H7_TIM_RCR UINT32_C(0x30)
///< offset to TIM repetition counter register
2824
#define MCCI_STM32H7_TIM_CCR1 UINT32_C(0x34)
///< offset to TIM capture/compare register 1
2825
#define MCCI_STM32H7_TIM_CCR2 UINT32_C(0x38)
///< offset to TIM capture/compare register 2
2826
#define MCCI_STM32H7_TIM_CCR3 UINT32_C(0x3C)
///< offset to TIM capture/compare register 3
2827
#define MCCI_STM32H7_TIM_CCR4 UINT32_C(0x40)
///< offset to TIM capture/compare register 4
2828
#define MCCI_STM32H7_TIM_BDTR UINT32_C(0x44)
///< offset to TIM break and dead-time register
2829
#define MCCI_STM32H7_TIM_DCR UINT32_C(0x48)
///< offset to TIM DMA control register
2830
#define MCCI_STM32H7_TIM_DMAR UINT32_C(0x4C)
///< offset to TIM DMA address register
2831
#define MCCI_STM32H7_TIM_CCMR3 UINT32_C(0x54)
///< offset to TIM capture/compare mode register 3
2832
#define MCCI_STM32H7_TIM_CCR5 UINT32_C(0x58)
///< offset to TIM capture/compare register 5
2833
#define MCCI_STM32H7_TIM_CCR6 UINT32_C(0x5C)
///< offset to TIM capture/compare register 6
2834
#define MCCI_STM32H7_TIM_AF1 UINT32_C(0x60)
///< offset to TIM Alternate function option register 1
2835
#define MCCI_STM32H7_TIM_AF2 UINT32_C(0x64)
///< offset to TIM Alternate function option register 2
2836
#define MCCI_STM32H7_TIM_TISEL UINT32_C(0x68)
///< offset to TIM timer input selection register
2837
/// @}
2838
2839
/// \name TIM_CR1 bits
2840
/// @{
2841
#define MCCI_STM32H7_TIM_CR1_RSV12 UINT32_C(0xFFFFF000)
///< reserved, don't change
2842
#define MCCI_STM32H7_TIM_CR1_UIFREMAP (UINT32_C(1) << 11)
///< UIF status bit remapping
2843
#define MCCI_STM32H7_TIM_CR1_RSV10 (UINT32_C(1) << 10)
///< reserved, don't change
2844
#define MCCI_STM32H7_TIM_CR1_CKD (UINT32_C(0x3) << 8)
///< Clock division
2845
#define MCCI_STM32H7_TIM_CR1_CKD_N(n) ((n) << 8)
///<
2846
#define MCCI_STM32H7_TIM_CR1_ARPE (UINT32_C(1) << 7)
///< Auto-reload preload enable
2847
#define MCCI_STM32H7_TIM_CR1_CMS (UINT32_C(0x3) << 5)
///< Center-aligned mode selection
2848
#define MCCI_STM32H7_TIM_CR1_CMS_N(n) ((n) << 5)
///<
2849
#define MCCI_STM32H7_TIM_CR1_DIR (UINT32_C(1) << 4)
///< Direction
2850
#define MCCI_STM32H7_TIM_CR1_OPM (UINT32_C(1) << 3)
///< One pulse mode
2851
#define MCCI_STM32H7_TIM_CR1_URS (UINT32_C(1) << 2)
///< Update request source
2852
#define MCCI_STM32H7_TIM_CR1_UDIS (UINT32_C(1) << 1)
///< Update disable
2853
#define MCCI_STM32H7_TIM_CR1_CEN (UINT32_C(1) << 0)
///< Counter enable
2854
/// @}
2855
2856
/// \name TIM_CR2 bits
2857
/// @{
2858
#define MCCI_STM32H7_TIM_CR2_RSV24 UINT32_C(0xFF000000)
///< reserved, don't change
2859
#define MCCI_STM32H7_TIM_CR2_MMS2 (UINT32_C(0xF) << 20)
///< Master mode selection 2
2860
#define MCCI_STM32H7_TIM_CR2_MMS2_N(n) ((n) << 20)
///<
2861
#define MCCI_STM32H7_TIM_CR2_RSV19 (UINT32_C(1) << 19)
///< reserved, don't change
2862
#define MCCI_STM32H7_TIM_CR2_OIS6 (UINT32_C(1) << 18)
///< Output Idle state 6 (OC6 output)
2863
#define MCCI_STM32H7_TIM_CR2_RSV17 (UINT32_C(1) << 17)
///< reserved, don't change
2864
#define MCCI_STM32H7_TIM_CR2_OIS5 (UINT32_C(1) << 16)
///< Output Idle state 5 (OC5 output)
2865
#define MCCI_STM32H7_TIM_CR2_RSV15 (UINT32_C(1) << 15)
///< reserved, don't change
2866
#define MCCI_STM32H7_TIM_CR2_OIS4 (UINT32_C(1) << 14)
///< Output Idle state 4 (OC4 output)
2867
#define MCCI_STM32H7_TIM_CR2_OIS3N (UINT32_C(1) << 13)
///< Output Idle state 3 (OC3N output)
2868
#define MCCI_STM32H7_TIM_CR2_OIS3 (UINT32_C(1) << 12)
///< Output Idle state 3 (OC3 output)
2869
#define MCCI_STM32H7_TIM_CR2_OIS2N (UINT32_C(1) << 11)
///< Output Idle state 2 (OC2N output)
2870
#define MCCI_STM32H7_TIM_CR2_OIS2 (UINT32_C(1) << 10)
///< Output Idle state 2 (OC2 output)
2871
#define MCCI_STM32H7_TIM_CR2_OIS1N (UINT32_C(1) << 9)
///< Output Idle state 1 (OC1N output)
2872
#define MCCI_STM32H7_TIM_CR2_OIS1 (UINT32_C(1) << 8)
///< Output Idle state 1 (OC1 output)
2873
#define MCCI_STM32H7_TIM_CR2_TI1S (UINT32_C(1) << 7)
///< TI1 selection
2874
#define MCCI_STM32H7_TIM_CR2_MMS (UINT32_C(0x7) << 4)
///< Master mode selection
2875
#define MCCI_STM32H7_TIM_CR2_MMS_N(n) ((n) << 4)
///<
2876
#define MCCI_STM32H7_TIM_CR2_CCDS (UINT32_C(1) << 3)
///< Capture/compare DMA selection
2877
#define MCCI_STM32H7_TIM_CR2_CCUS (UINT32_C(1) << 2)
///< Capture/compare control update selection
2878
#define MCCI_STM32H7_TIM_CR2_RSV1 (UINT32_C(1) << 1)
///< reserved, don't change
2879
#define MCCI_STM32H7_TIM_CR2_CCPC (UINT32_C(1) << 0)
///< Capture/compare preloaded control
2880
/// @}
2881
2882
/// \name TIM_SMCR bits
2883
/// @{
2884
#define MCCI_STM32H7_TIM_SMCR_RSV22 UINT32_C(0xFFC00000)
///< reserved, don't change
2885
#define MCCI_STM32H7_TIM_SMCR_TS3 (UINT32_C(0x3) << 20)
///< Trigger selection
2886
#define MCCI_STM32H7_TIM_SMCR_TS3_N(n) ((n) << 20)
///<
2887
#define MCCI_STM32H7_TIM_SMCR_RSV17 (UINT32_C(7) << 17)
///< reserved, don't change
2888
#define MCCI_STM32H7_TIM_SMCR_SMS3 (UINT32_C(1) << 16)
///< Slave mode selection
2889
#define MCCI_STM32H7_TIM_SMCR_ETP (UINT32_C(1) << 15)
///< External trigger polarity
2890
#define MCCI_STM32H7_TIM_SMCR_ECE (UINT32_C(1) << 14)
///< External clock enable
2891
#define MCCI_STM32H7_TIM_SMCR_ETPS (UINT32_C(0x3) << 12)
///< External trigger prescaler
2892
#define MCCI_STM32H7_TIM_SMCR_ETPS_N(n) ((n) << 12)
///<
2893
#define MCCI_STM32H7_TIM_SMCR_ETF (UINT32_C(0xF) << 8)
///< External trigger filter
2894
#define MCCI_STM32H7_TIM_SMCR_ETF_N(n) ((n) << 8)
///<
2895
#define MCCI_STM32H7_TIM_SMCR_MSM (UINT32_C(1) << 7)
///< Master/slave mode
2896
#define MCCI_STM32H7_TIM_SMCR_TS0 (UINT32_C(0x7) << 4)
///< Trigger selection
2897
#define MCCI_STM32H7_TIM_SMCR_TS0_N(n) ((n) << 4)
///<
2898
#define MCCI_STM32H7_TIM_SMCR_RSV3 (UINT32_C(1) << 3)
///< reserved, don't change
2899
#define MCCI_STM32H7_TIM_SMCR_SMS0 (UINT32_C(0x7) << 0)
///< Slave mode selection
2900
#define MCCI_STM32H7_TIM_SMCR_SMS0_N(n) ((n) << 0)
///<
2901
2902
#define MCCI_STM32H7_TIM_SMCR_TS (MCCI_STM32H7_TIM_SMCR_TS3 | MCCI_STM32H7_TIM_SMCR_TS0)
///< Trigger selection
2903
#define MCCI_STM32H7_TIM_SMCR_TS_N(n) (MCCI_STM32H7_TIM_SMCR_TS3_N((n) >> 3) | MCCI_STM32H7_TIM_SMCR_TS0_N((n) & UINT32_C(0x7)))
2904
#define MCCI_STM32H7_TIM_SMCR_SMS (MCCI_STM32H7_TIM_SMCR_SMS3 | MCCI_STM32H7_TIM_SMCR_SMS0)
///< Trigger selection
2905
#define MCCI_STM32H7_TIM_SMCR_SMS_N(n) ((((n) >> 3) << 16) | MCCI_STM32H7_TIM_SMCR_SMS0_N((n) & UINT32_C(0x7)))
2906
/// @}
2907
2908
/// \name TIM_DIER bits
2909
/// @{
2910
#define MCCI_STM32H7_TIM_DIER_RSV15 UINT32_C(0xFFFF8000)
///< reserved, don't change
2911
#define MCCI_STM32H7_TIM_DIER_TDE (UINT32_C(1) << 14)
///< Trigger DMA request enable
2912
#define MCCI_STM32H7_TIM_DIER_COMDE (UINT32_C(1) << 13)
///< COM DMA request enable
2913
#define MCCI_STM32H7_TIM_DIER_CC4DE (UINT32_C(1) << 12)
///< Capture/Compare 4 DMA request enable
2914
#define MCCI_STM32H7_TIM_DIER_CC3DE (UINT32_C(1) << 11)
///< Capture/Compare 3 DMA request enable
2915
#define MCCI_STM32H7_TIM_DIER_CC2DE (UINT32_C(1) << 10)
///< Capture/Compare 2 DMA request enable
2916
#define MCCI_STM32H7_TIM_DIER_CC1DE (UINT32_C(1) << 9)
///< Capture/Compare 1 DMA request enable
2917
#define MCCI_STM32H7_TIM_DIER_UDE (UINT32_C(1) << 8)
///< Update DMA request enable
2918
#define MCCI_STM32H7_TIM_DIER_BIE (UINT32_C(1) << 7)
///< Break interrupt enable
2919
#define MCCI_STM32H7_TIM_DIER_TIE (UINT32_C(1) << 6)
///< Trigger interrupt enable
2920
#define MCCI_STM32H7_TIM_DIER_COMIE (UINT32_C(1) << 5)
///< COM interrupt enable
2921
#define MCCI_STM32H7_TIM_DIER_CC4IE (UINT32_C(1) << 4)
///< Capture/Compare 4 interrupt enable
2922
#define MCCI_STM32H7_TIM_DIER_CC3IE (UINT32_C(1) << 3)
///< Capture/Compare 3 interrupt enable
2923
#define MCCI_STM32H7_TIM_DIER_CC2IE (UINT32_C(1) << 2)
///< Capture/Compare 2 interrupt enable
2924
#define MCCI_STM32H7_TIM_DIER_CC1IE (UINT32_C(1) << 1)
///< Capture/Compare 1 interrupt enable
2925
#define MCCI_STM32H7_TIM_DIER_UIE (UINT32_C(1) << 0)
///< Update interrupt enable
2926
/// @}
2927
2928
/// \name TIM_SR bits
2929
/// @{
2930
#define MCCI_STM32H7_TIM_SR_RSV18 UINT32_C(0xFFFC0000)
///< reserved, don't change
2931
#define MCCI_STM32H7_TIM_SR_CC6IF (UINT32_C(1) << 17)
///< Compare 6 interrupt flag
2932
#define MCCI_STM32H7_TIM_SR_CC5IF (UINT32_C(1) << 16)
///< Compare 5 interrupt flag
2933
#define MCCI_STM32H7_TIM_SR_RSV14 (UINT32_C(3) << 14)
///< reserved, don't change
2934
#define MCCI_STM32H7_TIM_SR_SBIF (UINT32_C(1) << 13)
///< System Break interrupt flag
2935
#define MCCI_STM32H7_TIM_SR_CC4OF (UINT32_C(1) << 12)
///< Capture/Compare 4 overcapture flag
2936
#define MCCI_STM32H7_TIM_SR_CC3OF (UINT32_C(1) << 11)
///< Capture/Compare 3 overcapture flag
2937
#define MCCI_STM32H7_TIM_SR_CC2OF (UINT32_C(1) << 10)
///< Capture/Compare 2 overcapture flag
2938
#define MCCI_STM32H7_TIM_SR_CC1OF (UINT32_C(1) << 9)
///< Capture/Compare 1 overcapture flag
2939
#define MCCI_STM32H7_TIM_SR_B2IF (UINT32_C(1) << 8)
///< Break 2 interrupt flag
2940
#define MCCI_STM32H7_TIM_SR_BIF (UINT32_C(1) << 7)
///< Break interrupt flag
2941
#define MCCI_STM32H7_TIM_SR_TIF (UINT32_C(1) << 6)
///< Trigger interrupt flag
2942
#define MCCI_STM32H7_TIM_SR_COMIF (UINT32_C(1) << 5)
///< COM interrupt flag
2943
#define MCCI_STM32H7_TIM_SR_CC4IF (UINT32_C(1) << 4)
///< Capture/Compare 4 interrupt flag
2944
#define MCCI_STM32H7_TIM_SR_CC3IF (UINT32_C(1) << 3)
///< Capture/Compare 3 interrupt flag
2945
#define MCCI_STM32H7_TIM_SR_CC2IF (UINT32_C(1) << 2)
///< Capture/Compare 2 interrupt flag
2946
#define MCCI_STM32H7_TIM_SR_CC1IF (UINT32_C(1) << 1)
///< Capture/Compare 1 interrupt flag
2947
#define MCCI_STM32H7_TIM_SR_UIF (UINT32_C(1) << 0)
///< Update interrupt flag
2948
/// @}
2949
2950
/// \name TIM_EGR bits
2951
/// @{
2952
#define MCCI_STM32H7_TIM_EGR_RSV8 UINT32_C(0xFFFFFE00)
///< reserved, don't change
2953
#define MCCI_STM32H7_TIM_EGR_B2G (UINT32_C(1) << 8)
///< Break 2 generation
2954
#define MCCI_STM32H7_TIM_EGR_BG (UINT32_C(1) << 7)
///< Break generation
2955
#define MCCI_STM32H7_TIM_EGR_TG (UINT32_C(1) << 6)
///< Trigger generation
2956
#define MCCI_STM32H7_TIM_EGR_COMG (UINT32_C(1) << 5)
///< COM generation
2957
#define MCCI_STM32H7_TIM_EGR_CC4G (UINT32_C(1) << 4)
///< Capture/Compare 4 generation
2958
#define MCCI_STM32H7_TIM_EGR_CC3G (UINT32_C(1) << 3)
///< Capture/Compare 3 generation
2959
#define MCCI_STM32H7_TIM_EGR_CC2G (UINT32_C(1) << 2)
///< Capture/Compare 2 generation
2960
#define MCCI_STM32H7_TIM_EGR_CC1G (UINT32_C(1) << 1)
///< Capture/Compare 1 generation
2961
#define MCCI_STM32H7_TIM_EGR_UG (UINT32_C(1) << 0)
///< Update generation
2962
/// @}
2963
2964
/// \name TIM_CNT bits
2965
/// @{
2966
#define MCCI_STM32H7_TIM_CNT_UIFCPY (UINT32_C(1) << 8)
///< UIF copy
2967
#define MCCI_STM32H7_TIM_CNT_RSV16 UINT32_C(0x7FFF0000)
///< reserved, don't change
2968
#define MCCI_STM32H7_TIM_CNT_CNT (UINT32_C(0xFFFF) << 0)
///< Counter value
2969
/// @}
2970
2971
/// \name TIM_PSC bits
2972
/// @{
2973
#define MCCI_STM32H7_TIM_PSC_RSV16 UINT32_C(0xFFFF0000)
///< reserved, don't change
2974
#define MCCI_STM32H7_TIM_PSC_PSC (UINT32_C(0xFFFF) << 0)
///< Prescaler value
2975
/// @}
2976
2977
/// \name TIM_ARR bits
2978
/// @{
2979
#define MCCI_STM32H7_TIM_ARR_RSV16 UINT32_C(0xFFFF0000)
///< reserved, don't change
2980
#define MCCI_STM32H7_TIM_ARR_ARR (UINT32_C(0xFFFF) << 0)
///< Auto-reload value
2981
/// @}
2982
2983
/// \name TIM_RCR bits
2984
/// @{
2985
#define MCCI_STM32H7_TIM_RCR_RSV16 UINT32_C(0xFFFF0000)
///< reserved, don't change
2986
#define MCCI_STM32H7_TIM_RCR_REP (UINT32_C(0xFFFF) << 0)
///< Repetition counter value
2987
/// @}
2988
2989
/// \name TIM_CCRx bits
2990
/// @{
2991
#define MCCI_STM32H7_TIM_CCR_RSV16 UINT32_C(0xFFFF0000)
///< reserved, don't change
2992
#define MCCI_STM32H7_TIM_CCR_CCR (UINT32_C(0xFFFF) << 0)
///< Capture/Compare value
2993
/// @}
2994
2995
/// \name TIM_AF1 bits
2996
/// @{
2997
#define MCCI_STM32H7_TIM_AF1_RSV18 UINT32_C(0xFFFC0000)
///< reserved, don't change
2998
#define MCCI_STM32H7_TIM_AF1_ETRSEL (UINT32_C(0xF) << 14)
///< ETR source selection
2999
#define MCCI_STM32H7_TIM_AF1_ETRSEL_N(n) ((n) << 14)
///
3000
#define MCCI_STM32H7_TIM_AF1_RSV12 (UINT32_C(3) << 12)
///< reserved, don't change
3001
#define MCCI_STM32H7_TIM_AF1_BKCMP2P (UINT32_C(1) << 11)
///< BRK COMP2 input polarity
3002
#define MCCI_STM32H7_TIM_AF1_BKCMP1P (UINT32_C(1) << 10)
///< BRK COMP1 input polarity
3003
#define MCCI_STM32H7_TIM_AF1_BKINP (UINT32_C(1) << 9)
///< BRK BKIN input polarity
3004
#define MCCI_STM32H7_TIM_AF1_BKDF1BK2E (UINT32_C(1) << 8)
///< BRK dfsdm1_break[2] enable
3005
#define MCCI_STM32H7_TIM_AF1_RSV3 (UINT32_C(0x1F) << 3)
///< reserved, don't change
3006
#define MCCI_STM32H7_TIM_AF1_BKCMP2E (UINT32_C(1) << 2)
///< BRK COMP2 enable
3007
#define MCCI_STM32H7_TIM_AF1_BKCMP1E (UINT32_C(1) << 1)
///< BRK COMP1 enable
3008
#define MCCI_STM32H7_TIM_AF1_BKINE (UINT32_C(1) << 0)
///< BRK BKIN input enable
3009
/// @}
3010
3011
/// \name TIM_AF2 bits
3012
/// @{
3013
#define MCCI_STM32H7_TIM_AF2_RSV12 UINT32_C(0xFFFFF000)
///< reserved, don't change
3014
#define MCCI_STM32H7_TIM_AF2_BKCMP2P (UINT32_C(1) << 11)
///< BRK COMP2 input polarity
3015
#define MCCI_STM32H7_TIM_AF2_BKCMP1P (UINT32_C(1) << 10)
///< BRK COMP1 input polarity
3016
#define MCCI_STM32H7_TIM_AF2_BKINP (UINT32_C(1) << 9)
///< BRK BKIN input polarity
3017
#define MCCI_STM32H7_TIM_AF2_BKDF1BK2E (UINT32_C(1) << 8)
///< BRK dfsdm1_break[2] enable
3018
#define MCCI_STM32H7_TIM_AF2_RSV3 (UINT32_C(0x1F) << 3)
///< reserved, don't change
3019
#define MCCI_STM32H7_TIM_AF2_BKCMP2E (UINT32_C(1) << 2)
///< BRK COMP2 enable
3020
#define MCCI_STM32H7_TIM_AF2_BKCMP1E (UINT32_C(1) << 1)
///< BRK COMP1 enable
3021
#define MCCI_STM32H7_TIM_AF2_BKINE (UINT32_C(1) << 0)
///< BRK BKIN input enable
3022
/// @}
3023
3024
/// \name TIM_TISEL bits
3025
/// @{
3026
#define MCCI_STM32H7_TIM_TISEL_RSV28 (UINT32_C(0xF) << 28)
///< reserved, don't change
3027
#define MCCI_STM32H7_TIM_TISEL_TI4SEL (UINT32_C(0xF) << 24)
///< selects TI4[0] to TI4[15] input
3028
#define MCCI_STM32H7_TIM_TISEL_TI4SEL_N(n) ((n) << 24)
///
3029
#define MCCI_STM32H7_TIM_TISEL_RSV20 (UINT32_C(0xF) << 20)
///< reserved, don't change
3030
#define MCCI_STM32H7_TIM_TISEL_TI3SEL (UINT32_C(0xF) << 16)
///< selects TI3[0] to TI3[15] input
3031
#define MCCI_STM32H7_TIM_TISEL_TI3SEL_N(n) ((n) << 16)
///
3032
#define MCCI_STM32H7_TIM_TISEL_RSV12 (UINT32_C(0xF) << 12)
///< reserved, don't change
3033
#define MCCI_STM32H7_TIM_TISEL_TI2SEL (UINT32_C(0xF) << 8)
///< selects TI2[0] to TI2[15] input
3034
#define MCCI_STM32H7_TIM_TISEL_TI2SEL_N(n) ((n) << 8)
///
3035
#define MCCI_STM32H7_TIM_TISEL_RSV4 (UINT32_C(0xF) << 4)
///< reserved, don't change
3036
#define MCCI_STM32H7_TIM_TISEL_TI1SEL (UINT32_C(0xF) << 0)
///< selects TI1[0] to TI1[15] input
3037
#define MCCI_STM32H7_TIM_TISEL_TI1SEL_N(n) ((n) << 0)
///
3038
/// @}
3039
3040
/****************************************************************************\
3041
|
3042
| Interrupt Number Definition
3043
|
3044
\****************************************************************************/
3045
3046
/// \name STM32Hxx interrupt numbers
3047
/// @{
3048
#define MCCI_STM32H7_IRQ_WWDG UINT32_C(0)
///< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)
3049
#define MCCI_STM32H7_IRQ_PVD_PVM UINT32_C(1)
///< PVD/PVM through EXTI Line detection Interrupt
3050
#define MCCI_STM32H7_IRQ_RTC_TAMP_STAMP_CSS_LSE UINT32_C(2)
///< Tamper, TimeStamp, CSS and LSE interrupts through the EXTI line
3051
#define MCCI_STM32H7_IRQ_RTC_WKUP UINT32_C(3)
///< RTC Wakeup interrupt through the EXTI line
3052
#define MCCI_STM32H7_IRQ_FLASH UINT32_C(4)
///< FLASH global Interrupt
3053
#define MCCI_STM32H7_IRQ_RCC UINT32_C(5)
///< RCC global Interrupt
3054
#define MCCI_STM32H7_IRQ_EXTI0 UINT32_C(6)
///< EXTI Line0 Interrupt
3055
#define MCCI_STM32H7_IRQ_EXTI1 UINT32_C(7)
///< EXTI Line1 Interrupt
3056
#define MCCI_STM32H7_IRQ_EXTI2 UINT32_C(8)
///< EXTI Line2 Interrupt
3057
#define MCCI_STM32H7_IRQ_EXTI3 UINT32_C(9)
///< EXTI Line3 Interrupt
3058
#define MCCI_STM32H7_IRQ_EXTI4 UINT32_C(10)
///< EXTI Line4 Interrupt
3059
#define MCCI_STM32H7_IRQ_DMA1_Stream0 UINT32_C(11)
///< DMA1 Stream 0 global Interrupt
3060
#define MCCI_STM32H7_IRQ_DMA1_Stream1 UINT32_C(12)
///< DMA1 Stream 1 global Interrupt
3061
#define MCCI_STM32H7_IRQ_DMA1_Stream2 UINT32_C(13)
///< DMA1 Stream 2 global Interrupt
3062
#define MCCI_STM32H7_IRQ_DMA1_Stream3 UINT32_C(14)
///< DMA1 Stream 3 global Interrupt
3063
#define MCCI_STM32H7_IRQ_DMA1_Stream4 UINT32_C(15)
///< DMA1 Stream 4 global Interrupt
3064
#define MCCI_STM32H7_IRQ_DMA1_Stream5 UINT32_C(16)
///< DMA1 Stream 5 global Interrupt
3065
#define MCCI_STM32H7_IRQ_DMA1_Stream6 UINT32_C(17)
///< DMA1 Stream 6 global Interrupt
3066
#define MCCI_STM32H7_IRQ_ADC UINT32_C(18)
///< ADC1 and ADC2 global Interrupts
3067
#define MCCI_STM32H7_IRQ_FDCAN1_IT0 UINT32_C(19)
///< FDCAN1 Interrupt line 0
3068
#define MCCI_STM32H7_IRQ_FDCAN2_IT0 UINT32_C(20)
///< FDCAN2 Interrupt line 0
3069
#define MCCI_STM32H7_IRQ_FDCAN1_IT1 UINT32_C(21)
///< FDCAN1 Interrupt line 1
3070
#define MCCI_STM32H7_IRQ_FDCAN2_IT1 UINT32_C(22)
///< FDCAN2 Interrupt line 1
3071
#define MCCI_STM32H7_IRQ_EXTI9_5 UINT32_C(23)
///< External Line[9:5] Interrupts
3072
#define MCCI_STM32H7_IRQ_TIM1_BRK UINT32_C(24)
///< TIM1 Break Interrupt
3073
#define MCCI_STM32H7_IRQ_TIM1_UP UINT32_C(25)
///< TIM1 Update Interrupt
3074
#define MCCI_STM32H7_IRQ_TIM1_TRG_COM UINT32_C(26)
///< TIM1 Trigger and Commutation Interrupt
3075
#define MCCI_STM32H7_IRQ_TIM1_CC UINT32_C(27)
///< TIM1 Capture Compare Interrupt
3076
#define MCCI_STM32H7_IRQ_TIM2 UINT32_C(28)
///< TIM2 global Interrupt
3077
#define MCCI_STM32H7_IRQ_TIM3 UINT32_C(29)
///< TIM3 global Interrupt
3078
#define MCCI_STM32H7_IRQ_TIM4 UINT32_C(30)
///< TIM4 global Interrupt
3079
#define MCCI_STM32H7_IRQ_I2C1_EV UINT32_C(31)
///< I2C1 Event Interrupt
3080
#define MCCI_STM32H7_IRQ_I2C1_ER UINT32_C(32)
///< I2C1 Error Interrupt
3081
#define MCCI_STM32H7_IRQ_I2C2_EV UINT32_C(33)
///< I2C2 Event Interrupt
3082
#define MCCI_STM32H7_IRQ_I2C2_ER UINT32_C(34)
///< I2C2 Error Interrupt
3083
#define MCCI_STM32H7_IRQ_SPI1 UINT32_C(35)
///< SPI1 global Interrupt
3084
#define MCCI_STM32H7_IRQ_SPI2 UINT32_C(36)
///< SPI2 global Interrupt
3085
#define MCCI_STM32H7_IRQ_USART1 UINT32_C(37)
///< USART1 global Interrupt
3086
#define MCCI_STM32H7_IRQ_USART2 UINT32_C(38)
///< USART2 global Interrupt
3087
#define MCCI_STM32H7_IRQ_USART3 UINT32_C(39)
///< USART3 global Interrupt
3088
#define MCCI_STM32H7_IRQ_EXTI15_10 UINT32_C(40)
///< External Line[15:10] Interrupts
3089
#define MCCI_STM32H7_IRQ_RTC_Alarm UINT32_C(41)
///< RTC Alarm (A and B) through EXTI Line Interrupt
3090
#define MCCI_STM32H7_IRQ_DFSDM2 UINT32_C(42)
///< DFSDM2 global Interrupt
3091
#define MCCI_STM32H7_IRQ_TIM8_BRK_TIM12 UINT32_C(43)
///< TIM8 Break Interrupt and TIM12 global interrupt
3092
#define MCCI_STM32H7_IRQ_TIM8_UP_TIM13 UINT32_C(44)
///< TIM8 Update Interrupt and TIM13 global interrupt
3093
#define MCCI_STM32H7_IRQ_TIM8_TRG_COM_TIM14 UINT32_C(45)
///< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
3094
#define MCCI_STM32H7_IRQ_TIM8_CC UINT32_C(46)
///< TIM8 Capture Compare Interrupt
3095
#define MCCI_STM32H7_IRQ_DMA1_Stream7 UINT32_C(47)
///< DMA1 Stream7 Interrupt
3096
#define MCCI_STM32H7_IRQ_FMC UINT32_C(48)
///< FMC global Interrupt
3097
#define MCCI_STM32H7_IRQ_SDMMC1 UINT32_C(49)
///< SDMMC1 global Interrupt
3098
#define MCCI_STM32H7_IRQ_TIM5 UINT32_C(50)
///< TIM5 global Interrupt
3099
#define MCCI_STM32H7_IRQ_SPI3 UINT32_C(51)
///< SPI3 global Interrupt
3100
#define MCCI_STM32H7_IRQ_UART4 UINT32_C(52)
///< UART4 global Interrupt
3101
#define MCCI_STM32H7_IRQ_UART5 UINT32_C(53)
///< UART5 global Interrupt
3102
#define MCCI_STM32H7_IRQ_TIM6_DAC UINT32_C(54)
///< TIM6 global and DAC1&2 underrun error interrupts
3103
#define MCCI_STM32H7_IRQ_TIM7 UINT32_C(55)
///< TIM7 global interrupt
3104
#define MCCI_STM32H7_IRQ_DMA2_Stream0 UINT32_C(56)
///< DMA2 Stream 0 global Interrupt
3105
#define MCCI_STM32H7_IRQ_DMA2_Stream1 UINT32_C(57)
///< DMA2 Stream 1 global Interrupt
3106
#define MCCI_STM32H7_IRQ_DMA2_Stream2 UINT32_C(58)
///< DMA2 Stream 2 global Interrupt
3107
#define MCCI_STM32H7_IRQ_DMA2_Stream3 UINT32_C(59)
///< DMA2 Stream 3 global Interrupt
3108
#define MCCI_STM32H7_IRQ_DMA2_Stream4 UINT32_C(60)
///< DMA2 Stream 4 global Interrupt
3109
#define MCCI_STM32H7_IRQ_FDCAN_CAL UINT32_C(63)
///< FDCAN Calibration unit Interrupt
3110
#define MCCI_STM32H7_IRQ_DFSDM1_FLT4 UINT32_C(64)
///< DFSDM Filter4 Interrupt
3111
#define MCCI_STM32H7_IRQ_DFSDM1_FLT5 UINT32_C(65)
///< DFSDM Filter5 Interrupt
3112
#define MCCI_STM32H7_IRQ_DFSDM1_FLT6 UINT32_C(66)
///< DFSDM Filter6 Interrupt
3113
#define MCCI_STM32H7_IRQ_DFSDM1_FLT7 UINT32_C(67)
///< DFSDM Filter7 Interrupt
3114
#define MCCI_STM32H7_IRQ_DMA2_Stream5 UINT32_C(68)
///< DMA2 Stream 5 global interrupt
3115
#define MCCI_STM32H7_IRQ_DMA2_Stream6 UINT32_C(69)
///< DMA2 Stream 6 global interrupt
3116
#define MCCI_STM32H7_IRQ_DMA2_Stream7 UINT32_C(70)
///< DMA2 Stream 7 global interrupt
3117
#define MCCI_STM32H7_IRQ_USART6 UINT32_C(71)
///< USART6 global interrupt
3118
#define MCCI_STM32H7_IRQ_I2C3_EV UINT32_C(72)
///< I2C3 event interrupt
3119
#define MCCI_STM32H7_IRQ_I2C3_ER UINT32_C(73)
///< I2C3 error interrupt
3120
#define MCCI_STM32H7_IRQ_OTG_HS_EP1_OUT UINT32_C(74)
///< USB OTG HS End Point 1 Out global interrupt
3121
#define MCCI_STM32H7_IRQ_OTG_HS_EP1_IN UINT32_C(75)
///< USB OTG HS End Point 1 In global interrupt
3122
#define MCCI_STM32H7_IRQ_OTG_HS_WKUP UINT32_C(76)
///< USB OTG HS Wakeup through EXTI interrupt
3123
#define MCCI_STM32H7_IRQ_OTG_HS UINT32_C(77)
///< USB OTG HS global interrupt
3124
#define MCCI_STM32H7_IRQ_DCMI_PSSI UINT32_C(78)
///< DCMI and PSSI global interrupt
3125
#define MCCI_STM32H7_IRQ_CRYP UINT32_C(79)
///< CRYP crypto global interrupt
3126
#define MCCI_STM32H7_IRQ_HASH_RNG UINT32_C(80)
///< HASH and RNG global interrupt
3127
#define MCCI_STM32H7_IRQ_FPU UINT32_C(81)
///< FPU global interrupt
3128
#define MCCI_STM32H7_IRQ_UART7 UINT32_C(82)
///< UART7 global interrupt
3129
#define MCCI_STM32H7_IRQ_UART8 UINT32_C(83)
///< UART8 global interrupt
3130
#define MCCI_STM32H7_IRQ_SPI4 UINT32_C(84)
///< SPI4 global Interrupt
3131
#define MCCI_STM32H7_IRQ_SPI5 UINT32_C(85)
///< SPI5 global Interrupt
3132
#define MCCI_STM32H7_IRQ_SPI6 UINT32_C(86)
///< SPI6 global Interrupt
3133
#define MCCI_STM32H7_IRQ_SAI1 UINT32_C(87)
///< SAI1 global Interrupt
3134
#define MCCI_STM32H7_IRQ_LTDC UINT32_C(88)
///< LTDC global Interrupt
3135
#define MCCI_STM32H7_IRQ_LTDC_ER UINT32_C(89)
///< LTDC Error global Interrupt
3136
#define MCCI_STM32H7_IRQ_DMA2D UINT32_C(90)
///< DMA2D global Interrupt
3137
#define MCCI_STM32H7_IRQ_SAI2 UINT32_C(91)
///< SAI2 global Interrupt
3138
#define MCCI_STM32H7_IRQ_OCTOSPI1 UINT32_C(92)
///< OCTOSPI1 global interrupt
3139
#define MCCI_STM32H7_IRQ_LPTIM1 UINT32_C(93)
///< LP TIM1 interrupt
3140
#define MCCI_STM32H7_IRQ_CEC UINT32_C(94)
///< HDMI-CEC global Interrupt
3141
#define MCCI_STM32H7_IRQ_I2C4_EV UINT32_C(95)
///< I2C4 Event Interrupt
3142
#define MCCI_STM32H7_IRQ_I2C4_ER UINT32_C(96)
///< I2C4 Error Interrupt
3143
#define MCCI_STM32H7_IRQ_SPDIF_RX UINT32_C(97)
///< SPDIF-RX global Interrupt
3144
#define MCCI_STM32H7_IRQ_DMAMUX1_OVR UINT32_C(102)
///< DMAMUX1 Overrun interrupt
3145
#define MCCI_STM32H7_IRQ_DFSDM1_FLT0 UINT32_C(110)
///< DFSDM Filter1 Interrupt
3146
#define MCCI_STM32H7_IRQ_DFSDM1_FLT1 UINT32_C(111)
///< DFSDM Filter2 Interrupt
3147
#define MCCI_STM32H7_IRQ_DFSDM1_FLT2 UINT32_C(112)
///< DFSDM Filter3 Interrupt
3148
#define MCCI_STM32H7_IRQ_DFSDM1_FLT3 UINT32_C(113)
///< DFSDM Filter4 Interrupt
3149
#define MCCI_STM32H7_IRQ_SWPMI1 UINT32_C(115)
///< Serial Wire Interface 1 global interrupt
3150
#define MCCI_STM32H7_IRQ_TIM15 UINT32_C(116)
///< TIM15 global Interrupt
3151
#define MCCI_STM32H7_IRQ_TIM16 UINT32_C(117)
///< TIM16 global Interrupt
3152
#define MCCI_STM32H7_IRQ_TIM17 UINT32_C(118)
///< TIM17 global Interrupt
3153
#define MCCI_STM32H7_IRQ_MDIOS_WKUP UINT32_C(119)
///< MDIOS Wakeup Interrupt
3154
#define MCCI_STM32H7_IRQ_MDIOS UINT32_C(120)
///< MDIOS global Interrupt
3155
#define MCCI_STM32H7_IRQ_JPEG UINT32_C(121)
///< JPEG global Interrupt
3156
#define MCCI_STM32H7_IRQ_MDMA UINT32_C(122)
///< MDMA global Interrupt
3157
#define MCCI_STM32H7_IRQ_SDMMC2 UINT32_C(124)
///< SDMMC2 global Interrupt
3158
#define MCCI_STM32H7_IRQ_HSEM1 UINT32_C(125)
///< HSEM1 global Interrupt
3159
#define MCCI_STM32H7_IRQ_DAC2 UINT32_C(127)
///< DAC2 global Interrupt
3160
#define MCCI_STM32H7_IRQ_DMAMUX2_OVR UINT32_C(128)
///< DMAMUX2 Overrun interrupt
3161
#define MCCI_STM32H7_IRQ_BDMA2_Channel0 UINT32_C(129)
///< BDMA2 Channel 0 global Interrupt
3162
#define MCCI_STM32H7_IRQ_BDMA2_Channel1 UINT32_C(130)
///< BDMA2 Channel 1 global Interrupt
3163
#define MCCI_STM32H7_IRQ_BDMA2_Channel2 UINT32_C(131)
///< BDMA2 Channel 2 global Interrupt
3164
#define MCCI_STM32H7_IRQ_BDMA2_Channel3 UINT32_C(132)
///< BDMA2 Channel 3 global Interrupt
3165
#define MCCI_STM32H7_IRQ_BDMA2_Channel4 UINT32_C(133)
///< BDMA2 Channel 4 global Interrupt
3166
#define MCCI_STM32H7_IRQ_BDMA2_Channel5 UINT32_C(134)
///< BDMA2 Channel 5 global Interrupt
3167
#define MCCI_STM32H7_IRQ_BDMA2_Channel6 UINT32_C(135)
///< BDMA2 Channel 6 global Interrupt
3168
#define MCCI_STM32H7_IRQ_BDMA2_Channel7 UINT32_C(136)
///< BDMA2 Channel 7 global Interrupt
3169
#define MCCI_STM32H7_IRQ_COMP UINT32_C(137)
///< COMP global Interrupt
3170
#define MCCI_STM32H7_IRQ_LPTIM2 UINT32_C(138)
///< LP TIM2 global interrupt
3171
#define MCCI_STM32H7_IRQ_LPTIM3 UINT32_C(139)
///< LP TIM3 global interrupt
3172
#define MCCI_STM32H7_IRQ_UART9 UINT32_C(140)
///< UART9 global interrupt
3173
#define MCCI_STM32H7_IRQ_USART10 UINT32_C(141)
///< USART10 global interrupt
3174
#define MCCI_STM32H7_IRQ_LPUART1 UINT32_C(142)
///< LP UART1 interrupt
3175
#define MCCI_STM32H7_IRQ_WWDG_RST UINT32_C(143)
///< Window Watchdog Event interrupt
3176
#define MCCI_STM32H7_IRQ_CRS UINT32_C(144)
///< Clock Recovery Global Interrupt
3177
#define MCCI_STM32H7_IRQ_ECC UINT32_C(145)
///< ECC diagnostic Global Interrupt
3178
#define MCCI_STM32H7_IRQ_DTS UINT32_C(147)
///< Digital Temperature Sensor Global Interrupt
3179
#define MCCI_STM32H7_IRQ_WAKEUP_PIN UINT32_C(149)
///< Interrupt for all 6 wake-up pins
3180
#define MCCI_STM32H7_IRQ_OCTOSPI2 UINT32_C(150)
///< OctoSPI2 global interrupt
3181
#define MCCI_STM32H7_IRQ_OTFDEC1 UINT32_C(151)
///< OTFDEC1 global interrupt
3182
#define MCCI_STM32H7_IRQ_OTFDEC2 UINT32_C(152)
///< OTFDEC2 global interrupt
3183
#define MCCI_STM32H7_IRQ_GFXMMU UINT32_C(153)
///< GFXMMU global interrupt
3184
#define MCCI_STM32H7_IRQ_BDMA1 UINT32_C(154)
///< BDMA1 for DFSM global interrupt
3185
/// @}
3186
3187
/****************************************************************************\
3188
|
3189
| End of file
3190
|
3191
\****************************************************************************/
3192
3193
#ifdef __cplusplus
3194
}
3195
#endif
3196
3197
#endif
/* _mcci_stm32h7xx_h_ */
mcci_arm_cm7.h
mcci_bootloader_bits.h
platform
soc
stm32h7
i
mcci_stm32h7xx.h
Generated on Fri Apr 3 2026 07:39:06 for MCCI Trusted Bootloader by
1.9.8
1.9.8