MCCI Trusted Bootloader
Simple trusted bootloader and tools for small embedded systems
Macros
mcci_stm32h7xx.h File Reference
#include "mcci_bootloader_bits.h"
#include "mcci_arm_cm7.h"
#include <stdint.h>

Go to the source code of this file.

Macros

#define _mcci_stm32h7xx_h_   /* prevent multiple includes */
 
#define MCCI_STM32H7_GPIO_AFSEL_P(p)   (UINT32_C(0xF) << (((p) & UINT32_C(0x7)) * UINT32_C(4)))
 get AFRx mask for port bit p.
 
#define MCCI_STM32H7_GPIO_AFSEL_PV(p, v)   ((v) << (((p) & UINT32_C(0x7)) * UINT32_C(4)))
 
#define MCCI_STM32H7_GPIO_MODE_P(p)   (UINT32_C(3) << (2 * (p)))
 compute the mask for the mode bits for port bits 0..31
 
#define MCCI_STM32H7_GPIO_MODE_PV(p, v)   ((v) << (2 * (p)))
 
#define MCCI_STM32H7_GPIO_OSPEED_P(p)   (UINT32_C(3) << (2 * (p)))
 compute the mask for the mode bits for port bits 0..31
 
#define MCCI_STM32H7_GPIO_OSPEED_PV(p, v)   ((v) << (2 * (p)))
 
#define MCCI_STM32H7_GPIO_OTYPE_P(p)   (UINT32_C(1) << (p))
 compute the mask for the mode bits for port bits 0..15
 
#define MCCI_STM32H7_GPIO_OTYPE_PV(p, v)   ((v) << (p))
 
#define MCCI_STM32H7_GPIO_PUPD_P(p)   (UINT32_C(3) << (2 * (p)))
 compute the mask for the mode bits for port bits 0..31
 
#define MCCI_STM32H7_GPIO_PUPD_PV(p, v)   ((v) << (2 * (p)))
 
STM32H7xx top-level address breakdown
#define MCCI_STM32H7_MEMORY_AHB_SRAM1   UINT32_C(0x30000000)
 AHB SRAM1 (up to 64K)
 
#define MCCI_STM32H7_MEMORY_AHB_SRAM2   UINT32_C(0x30010000)
 AHB SRAM2 (up to 64K)
 
#define MCCI_STM32H7_MEMORY_AXI_SRAM1   UINT32_C(0x24000000)
 AXI SRAM1 (up to 256K)
 
#define MCCI_STM32H7_MEMORY_AXI_SRAM2   UINT32_C(0x24040000)
 AXI SRAM2 (up to 384K)
 
#define MCCI_STM32H7_MEMORY_AXI_SRAM3   UINT32_C(0x240A0000)
 AXI SRAM3 (up to 384K)
 
#define MCCI_STM32H7_MEMORY_DTCM_RAM   UINT32_C(0x20000000)
 DTCM RAM (128K)
 
#define MCCI_STM32H7_MEMORY_FLASH   UINT32_C(0x08000000)
 Flash program memory (up to 2M)
 
#define MCCI_STM32H7_MEMORY_FLASH1   UINT32_C(0x08000000)
 Flash program memory (up to 1M)
 
#define MCCI_STM32H7_MEMORY_FLASH2   UINT32_C(0x08100000)
 Flash program memory (up to 1M)
 
#define MCCI_STM32H7_MEMORY_FLASH_END   UINT32_C(0x081FFFFF)
 End of Flash program memory.
 
#define MCCI_STM32H7_MEMORY_ITCM_RAM   UINT32_C(0x00000000)
 ITCM RAM (64K)
 
#define MCCI_STM32H7_MEMORY_OTP   UINT32_C(0x08FFF000)
 OTP Area (1K)
 
#define MCCI_STM32H7_MEMORY_OTP_END   UINT32_C(0x08FFF3FF)
 End of OTP Area.
 
#define MCCI_STM32H7_MEMORY_READ_ONLY   UINT32_C(0x08FFF800)
 read-only area (512)
 
#define MCCI_STM32H7_MEMORY_SRD_BKPSRAM   UINT32_C(0x38800000)
 SRD Backup SRAM (up to 4K)
 
#define MCCI_STM32H7_MEMORY_SRD_SRAM   UINT32_C(0x38000000)
 SRD SRAM (up to 32K)
 
#define MCCI_STM32H7_MEMORY_SYSTEM   UINT32_C(0x1FF00000)
 System memory (128K)
 
#define MCCI_STM32H7_MEMORY_SYSTEM_END   UINT32_C(0x1FF1FFFF)
 End of System memory.
 
#define MCCI_STM32H7_REG_ADC1   UINT32_C(0x40022000)
 Section 27.7: ADC register map (1K)
 
#define MCCI_STM32H7_REG_BDMA1   UINT32_C(0x48022C00)
 Section 16.6: BDMA register map (1K)
 
#define MCCI_STM32H7_REG_BDMA2   UINT32_C(0x58025400)
 Section 16.6: BDMA register map (1K)
 
#define MCCI_STM32H7_REG_CAN_CCU   UINT32_C(0x4000A800)
 Section 61.5: FDCAN register map (1K)
 
#define MCCI_STM32H7_REG_CAN_MSG_RAM   UINT32_C(0x4000AC00)
 Section 61.5: FDCAN register map (1K)
 
#define MCCI_STM32H7_REG_COMP   UINT32_C(0x58003800)
 Section 31.6: COMP register map (1K)
 
#define MCCI_STM32H7_REG_CRC   UINT32_C(0x40023000)
 Section 22.4: CRC register map (1K)
 
#define MCCI_STM32H7_REG_CRS   UINT32_C(0x40008400)
 Section 9.8: CRS register map (1K)
 
#define MCCI_STM32H7_REG_CRYPTO   UINT32_C(0x48021000)
 Section 39.7: CRYPTO register map (1K)
 
#define MCCI_STM32H7_REG_DAC1   UINT32_C(0x40007400)
 Section 29.7: DAC register map (1K)
 
#define MCCI_STM32H7_REG_DAC2   UINT32_C(0x58003400)
 Section 29.7: DAC register map (1K)
 
#define MCCI_STM32H7_REG_DCMI   UINT32_C(0x48020000)
 Section 34.5: DCMI register map (1K)
 
#define MCCI_STM32H7_REG_DFSDM1   UINT32_C(0x40017800)
 Section 33.7: 33.8: DFSDM register map (1K)
 
#define MCCI_STM32H7_REG_DFSDM2   UINT32_C(0x58006C00)
 Section 33.7: DFSDM register map (1K)
 
#define MCCI_STM32H7_REG_DLYB_OCTOSPI1   UINT32_C(0x52006000)
 Section 26.4: DLYB register map (4K)
 
#define MCCI_STM32H7_REG_DLYB_OCTOSPI2   UINT32_C(0x5200B000)
 Section 26.4: DLYB register map (1K)
 
#define MCCI_STM32H7_REG_DLYB_SDMMC1   UINT32_C(0x52008000)
 Section 26.4: DLYB register map (1K)
 
#define MCCI_STM32H7_REG_DLYB_SDMMC2   UINT32_C(0x48022800)
 Section 26.4: DLYB register map (1K)
 
#define MCCI_STM32H7_REG_DMA1   UINT32_C(0x40020000)
 Section 15.5: DMA register map (1K)
 
#define MCCI_STM32H7_REG_DMA2   UINT32_C(0x40020400)
 Section 15.5: DMA register map (1K)
 
#define MCCI_STM32H7_REG_DMA2D   UINT32_C(0x52001000)
 Section 18.5: DMA2D register map (4K)
 
#define MCCI_STM32H7_REG_DMAMUX1   UINT32_C(0x40020800)
 Section 17.6: DMAMUX register map (1K)
 
#define MCCI_STM32H7_REG_DMAMUX2   UINT32_C(0x58025800)
 Section 17.6: DMAMUX register map (1K)
 
#define MCCI_STM32H7_REG_DTS   UINT32_C(0x58006800)
 Section 28.6: DTS register map (1K)
 
#define MCCI_STM32H7_REG_EXTI   UINT32_C(0x58000000)
 Section 20.6: EXTI register map (1K)
 
#define MCCI_STM32H7_REG_FDCAN   UINT32_C(0x4000A400)
 Section 61.5: FDCAN register map (1K)
 
#define MCCI_STM32H7_REG_FLASH   UINT32_C(0x52002000)
 Section 4.9: FLASH register map (4K)
 
#define MCCI_STM32H7_REG_FMC   UINT32_C(0x52004000)
 Section 23.7.6: 23.8.7: 23.9.5: FMC register map (4K)
 
#define MCCI_STM32H7_REG_GFXMMU   UINT32_C(0x5200C000)
 Section 21.5: GFXMMU register map (8K)
 
#define MCCI_STM32H7_REG_GPIOA   UINT32_C(0x58020000)
 Section 11.4: GPIO register map (1K)
 
#define MCCI_STM32H7_REG_GPIOB   UINT32_C(0x58020400)
 Section 11.4: GPIO register map (1K)
 
#define MCCI_STM32H7_REG_GPIOC   UINT32_C(0x58020800)
 Section 11.4: GPIO register map (1K)
 
#define MCCI_STM32H7_REG_GPIOD   UINT32_C(0x58020C00)
 Section 11.4: GPIO register map (1K)
 
#define MCCI_STM32H7_REG_GPIOE   UINT32_C(0x58021000)
 Section 11.4: GPIO register map (1K)
 
#define MCCI_STM32H7_REG_GPIOF   UINT32_C(0x58021400)
 Section 11.4: GPIO register map (1K)
 
#define MCCI_STM32H7_REG_GPIOG   UINT32_C(0x58021800)
 Section 11.4: GPIO register map (1K)
 
#define MCCI_STM32H7_REG_GPIOH   UINT32_C(0x58021C00)
 Section 11.4: GPIO register map (1K)
 
#define MCCI_STM32H7_REG_GPIOI   UINT32_C(0x58022000)
 Section 11.4: GPIO register map (1K)
 
#define MCCI_STM32H7_REG_GPIOJ   UINT32_C(0x58022400)
 Section 11.4: GPIO register map (1K)
 
#define MCCI_STM32H7_REG_GPIOK   UINT32_C(0x58022800)
 Section 11.4: GPIO register map (1K)
 
#define MCCI_STM32H7_REG_GPV   UINT32_C(0x51000000)
 Section 2.2.4: AXI interconnect register map (1M)
 
#define MCCI_STM32H7_REG_HASH   UINT32_C(0x48021400)
 Section 40.7: HASH register map (1K)
 
#define MCCI_STM32H7_REG_HDMI_CEC   UINT32_C(0x40006C00)
 Section 63.7: HDMI-CEC register map (1K)
 
#define MCCI_STM32H7_REG_HSEM   UINT32_C(0x48020800)
 Section 10.4: HSEM register map (1K)
 
#define MCCI_STM32H7_REG_I2C1   UINT32_C(0x40005400)
 Section 52.7: I2C register map (1K)
 
#define MCCI_STM32H7_REG_I2C2   UINT32_C(0x40005800)
 Section 52.7: I2C register map (1K)
 
#define MCCI_STM32H7_REG_I2C3   UINT32_C(0x40005C00)
 Section 52.7: I2C register map (1K)
 
#define MCCI_STM32H7_REG_I2C4   UINT32_C(0x58001C00)
 Section 52.7: I2C register map (1K)
 
#define MCCI_STM32H7_REG_I2S1   UINT32_C(0x40013000)
 Section 55.11: SPI register map (1K)
 
#define MCCI_STM32H7_REG_I2S6   UINT32_C(0x58001400)
 Section 55.11: I2S register map (1K)
 
#define MCCI_STM32H7_REG_IWDG   UINT32_C(0x58004800)
 Section 49.4: IWDG register map (1K)
 
#define MCCI_STM32H7_REG_JPEG   UINT32_C(0x52003000)
 Section 4.9: JPEG register map (4K)
 
#define MCCI_STM32H7_REG_LPTIM1   UINT32_C(0x40002400)
 Section 47.7: LPTIM register map (1K)
 
#define MCCI_STM32H7_REG_LPTIM2   UINT32_C(0x58002400)
 Section 47.7: LPTIM register map (1K)
 
#define MCCI_STM32H7_REG_LPTIM3   UINT32_C(0x58002800)
 Section 47.7: LPTIM register map (1K)
 
#define MCCI_STM32H7_REG_LPUART1   UINT32_C(0x58000C00)
 Section 54.6: LPUART register map (1K)
 
#define MCCI_STM32H7_REG_LTDC   UINT32_C(0x50001000)
 Section 36.7: LTDC register map (4K)
 
#define MCCI_STM32H7_REG_MDIOS   UINT32_C(0x40009400)
 Section 59.4: MDIOS register map (1K)
 
#define MCCI_STM32H7_REG_MDMA   UINT32_C(0x52000000)
 Section 14.5: MDMA register map (4K)
 
#define MCCI_STM32H7_REG_OCTOSPI1   UINT32_C(0x52005000)
 Section 24.7: OCTOSPI register map (4K)
 
#define MCCI_STM32H7_REG_OCTOSPI2   UINT32_C(0x5200A000)
 Section 24.7: OCTOSPI register map (4K)
 
#define MCCI_STM32H7_REG_OPAMP   UINT32_C(0x40009000)
 Section 32.6: OPAMP register map (1K)
 
#define MCCI_STM32H7_REG_OTCOSPIM   UINT32_C(0x5200B400)
 Section 25.4: OTCOSPIM register map (1K)
 
#define MCCI_STM32H7_REG_OTFDEC1   UINT32_C(0x5200B800)
 Section 41.6: OTFDEC register map (1K)
 
#define MCCI_STM32H7_REG_OTFDEC2   UINT32_C(0x5200BC00)
 Section 41.6: OTFDEC register map (1K)
 
#define MCCI_STM32H7_REG_OTG_HS   UINT32_C(0x40040000)
 Section 62.14: OTG_HS register map (1K)
 
#define MCCI_STM32H7_REG_PSSI   UINT32_C(0x48020400)
 Section 35.5: PSSI register map (1K)
 
#define MCCI_STM32H7_REG_PWR   UINT32_C(0x58024800)
 Section 6.8: PWR register map (1K)
 
#define MCCI_STM32H7_REG_RAMECC   UINT32_C(0x52009000)
 Section 3.4: RAMECC register map (1K)
 
#define MCCI_STM32H7_REG_RCC   UINT32_C(0x58024400)
 Section 8.7: RCC register map (1K)
 
#define MCCI_STM32H7_REG_RNG   UINT32_C(0x48021800)
 Section 38.7: RNG register map (1K)
 
#define MCCI_STM32H7_REG_RTC   UINT32_C(0x58004000)
 Section 50.6: RTC register map (1K)
 
#define MCCI_STM32H7_REG_SAI1   UINT32_C(0x40015800)
 Section 56.6: SAI register map (1K)
 
#define MCCI_STM32H7_REG_SAI2   UINT32_C(0x40015C00)
 Section 56.6: SAI register map (1K)
 
#define MCCI_STM32H7_REG_SDMMC1   UINT32_C(0x52007000)
 Section 60.10: SDMMC register map (4K)
 
#define MCCI_STM32H7_REG_SDMMC2   UINT32_C(0x48022400)
 Section 60.10: SDMMC register map (1K)
 
#define MCCI_STM32H7_REG_SPDIFRX1   UINT32_C(0x40004000)
 Section 57.5: SPDIFRX interface register map (1K)
 
#define MCCI_STM32H7_REG_SPI1   UINT32_C(0x40013000)
 Section 55.11: SPI register map (1K)
 
#define MCCI_STM32H7_REG_SPI2   UINT32_C(0x40003800)
 Section 55.11: SPI register map (1K)
 
#define MCCI_STM32H7_REG_SPI3   UINT32_C(0x40003C00)
 Section 55.11: SPI register map (1K)
 
#define MCCI_STM32H7_REG_SPI4   UINT32_C(0x40013400)
 Section 55.11: SPI register map (1K)
 
#define MCCI_STM32H7_REG_SPI5   UINT32_C(0x40015000)
 Section 55.11: SPI register map (1K)
 
#define MCCI_STM32H7_REG_SPI6   UINT32_C(0x58001400)
 Section 55.11: SPI register map (1K)
 
#define MCCI_STM32H7_REG_SWPMI   UINT32_C(0x40008800)
 Section 58.6: SWPMI register map (1K)
 
#define MCCI_STM32H7_REG_SYSCFG   UINT32_C(0x58000400)
 Section 12.4: SYSCFG register map (1K)
 
#define MCCI_STM32H7_REG_TAMP   UINT32_C(0x58004400)
 Section 51.6: TAMP register map (1K)
 
#define MCCI_STM32H7_REG_TIMER1   UINT32_C(0x40010000)
 Section 42.4: TIMx register map (1K)
 
#define MCCI_STM32H7_REG_TIMER12   UINT32_C(0x40001800)
 Section 43.4: TIM6/7 register map (1K)
 
#define MCCI_STM32H7_REG_TIMER13   UINT32_C(0x40001C00)
 Section 43.4: TIM6/7 register map (1K)
 
#define MCCI_STM32H7_REG_TIMER14   UINT32_C(0x40002000)
 Section 43.4: TIM6/7 register map (1K)
 
#define MCCI_STM32H7_REG_TIMER15   UINT32_C(0x40014000)
 Section 45.5: TIMx register map (1K)
 
#define MCCI_STM32H7_REG_TIMER16   UINT32_C(0x40014400)
 Section 45.5: TIMx register map (1K)
 
#define MCCI_STM32H7_REG_TIMER17   UINT32_C(0x40014800)
 Section 45.5: TIMx register map (1K)
 
#define MCCI_STM32H7_REG_TIMER2   UINT32_C(0x40000000)
 Section 43.4: TIMx register map (1K)
 
#define MCCI_STM32H7_REG_TIMER3   UINT32_C(0x40000400)
 Section 43.4: TIMx register map (1K)
 
#define MCCI_STM32H7_REG_TIMER4   UINT32_C(0x40000800)
 Section 43.4: TIMx register map (1K)
 
#define MCCI_STM32H7_REG_TIMER5   UINT32_C(0x40000C00)
 Section 43.4: TIMx register map (1K)
 
#define MCCI_STM32H7_REG_TIMER6   UINT32_C(0x40001000)
 Section 46.4: TIM6/7 register map (1K)
 
#define MCCI_STM32H7_REG_TIMER7   UINT32_C(0x40001400)
 Section 46.4: TIM6/7 register map (1K)
 
#define MCCI_STM32H7_REG_TIMER8   UINT32_C(0x40010400)
 Section 42.4: TIMx register map (1K)
 
#define MCCI_STM32H7_REG_TT_FDCAN   UINT32_C(0x4000A000)
 Section 61.5: FDCAN register map (1K)
 
#define MCCI_STM32H7_REG_UART4   UINT32_C(0x40004C00)
 Section 53.7: USART register map (1K)
 
#define MCCI_STM32H7_REG_UART5   UINT32_C(0x40005000)
 Section 53.7: USART register map (1K)
 
#define MCCI_STM32H7_REG_UART7   UINT32_C(0x40007800)
 Section 53.7: USART register map (1K)
 
#define MCCI_STM32H7_REG_UART8   UINT32_C(0x40007C00)
 Section 53.7: USART register map (1K)
 
#define MCCI_STM32H7_REG_UART9   UINT32_C(0x40011800)
 Section 53.7: USART register map (1K)
 
#define MCCI_STM32H7_REG_USART1   UINT32_C(0x40011000)
 Section 53.7: USART register map (1K)
 
#define MCCI_STM32H7_REG_USART10   UINT32_C(0x40011C00)
 Section 53.7: USART register map (1K)
 
#define MCCI_STM32H7_REG_USART2   UINT32_C(0x40004400)
 Section 53.7: USART register map (1K)
 
#define MCCI_STM32H7_REG_USART3   UINT32_C(0x40004800)
 Section 53.7: USART register map (1K)
 
#define MCCI_STM32H7_REG_USART6   UINT32_C(0x40011400)
 Section 53.7: USART register map (1K)
 
#define MCCI_STM32H7_REG_VREF   UINT32_C(0x58003C00)
 Section 30.3: VREF register map (1K)
 
#define MCCI_STM32H7_REG_WWDG   UINT32_C(0x50003000)
 Section 48.4: WWDG register map (4K)
 
System values in system option memory
#define MCCI_STM32H7_OPTIONS_PACKAGE_DATA   UINT32_C(0x08FFF80E)
 package data (16 bits)
 
#define MCCI_STM32H7_OPTIONS_SYSTEM_FLASH_SIZE   UINT32_C(0x08FFF80C)
 memory size in k bytes (16 bits)
 
#define MCCI_STM32H7_OPTIONS_SYSTEM_FLASH_SIZE_TO_BYTES(h)
 convert flash_size_16 value to bytes
 
#define MCCI_STM32H7_OPTIONS_U_ID_0   UINT32_C(0x08FFF800)
 register address: unique ID bits 31:0
 
#define MCCI_STM32H7_OPTIONS_U_ID_4   (MCCI_STM32H7_OPTIONS_U_ID_0 + 0x04)
 register address: unique ID bits 63:32
 
#define MCCI_STM32H7_OPTIONS_U_ID_8   (MCCI_STM32H7_OPTIONS_U_ID_0 + 0x08)
 register address: unique ID bits 95:64
 
FLASH registers
#define MCCI_STM32H7_REG_FLASH_ACR   (MCCI_STM32H7_REG_FLASH + 0x000)
 Flash access control register.
 
#define MCCI_STM32H7_REG_FLASH_BOOT_CUR   (MCCI_STM32H7_REG_FLASH + 0x040)
 Flash boot address.
 
#define MCCI_STM32H7_REG_FLASH_BOOT_PRG   (MCCI_STM32H7_REG_FLASH + 0x044)
 Flash boot address.
 
#define MCCI_STM32H7_REG_FLASH_CCR1   (MCCI_STM32H7_REG_FLASH + 0x014)
 Flash clear control register for bank 1.
 
#define MCCI_STM32H7_REG_FLASH_CCR2   (MCCI_STM32H7_REG_FLASH + 0x114)
 Flash clear control register for bank 2.
 
#define MCCI_STM32H7_REG_FLASH_CR1   (MCCI_STM32H7_REG_FLASH + 0x00C)
 Flash control register for bank 1.
 
#define MCCI_STM32H7_REG_FLASH_CR2   (MCCI_STM32H7_REG_FLASH + 0x10C)
 Flash control register for bank 2.
 
#define MCCI_STM32H7_REG_FLASH_CRCCR1   (MCCI_STM32H7_REG_FLASH + 0x050)
 Flash CRC control register for bank 1.
 
#define MCCI_STM32H7_REG_FLASH_CRCCR2   (MCCI_STM32H7_REG_FLASH + 0x150)
 Flash CRC control register for bank 2.
 
#define MCCI_STM32H7_REG_FLASH_CRCDATA   (MCCI_STM32H7_REG_FLASH + 0x05C)
 Flash CRC data register.
 
#define MCCI_STM32H7_REG_FLASH_CRCEADD1   (MCCI_STM32H7_REG_FLASH + 0x058)
 Flash CRC end address register for bank 1.
 
#define MCCI_STM32H7_REG_FLASH_CRCEADD2   (MCCI_STM32H7_REG_FLASH + 0x158)
 Flash CRC end address register for bank 2.
 
#define MCCI_STM32H7_REG_FLASH_CRCSADD1   (MCCI_STM32H7_REG_FLASH + 0x054)
 Flash CRC start address register for bank 1.
 
#define MCCI_STM32H7_REG_FLASH_CRCSADD2   (MCCI_STM32H7_REG_FLASH + 0x154)
 Flash CRC start address register for bank 2.
 
#define MCCI_STM32H7_REG_FLASH_ECC_FA1   (MCCI_STM32H7_REG_FLASH + 0x060)
 Flash ECC fail address for bank 1.
 
#define MCCI_STM32H7_REG_FLASH_ECC_FA2   (MCCI_STM32H7_REG_FLASH + 0x160)
 Flash ECC fail address for bank 2.
 
#define MCCI_STM32H7_REG_FLASH_KEYR1   (MCCI_STM32H7_REG_FLASH + 0x004)
 Flash key register for bank 1.
 
#define MCCI_STM32H7_REG_FLASH_KEYR2   (MCCI_STM32H7_REG_FLASH + 0x104)
 Flash key register for bank 2.
 
#define MCCI_STM32H7_REG_FLASH_OPTCCR   (MCCI_STM32H7_REG_FLASH + 0x024)
 Flash option clear control register.
 
#define MCCI_STM32H7_REG_FLASH_OPTCR   (MCCI_STM32H7_REG_FLASH + 0x018)
 Flash option control register.
 
#define MCCI_STM32H7_REG_FLASH_OPTKEYR   (MCCI_STM32H7_REG_FLASH + 0x008)
 Flash option key register.
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_CUR   (MCCI_STM32H7_REG_FLASH + 0x01C)
 Flash option status register.
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_PRG   (MCCI_STM32H7_REG_FLASH + 0x020)
 Flash option status register.
 
#define MCCI_STM32H7_REG_FLASH_OTPBL_CUR   (MCCI_STM32H7_REG_FLASH + 0x068)
 Flash OTP block lock.
 
#define MCCI_STM32H7_REG_FLASH_OTPBL_PRG   (MCCI_STM32H7_REG_FLASH + 0x06C)
 Flash OTP block lock.
 
#define MCCI_STM32H7_REG_FLASH_PRAR_CUR1   (MCCI_STM32H7_REG_FLASH + 0x028)
 Flash protection address for bank 1.
 
#define MCCI_STM32H7_REG_FLASH_PRAR_CUR2   (MCCI_STM32H7_REG_FLASH + 0x128)
 Flash protection address for bank 2.
 
#define MCCI_STM32H7_REG_FLASH_PRAR_PRG1   (MCCI_STM32H7_REG_FLASH + 0x02C)
 Flash protection address for bank 1.
 
#define MCCI_STM32H7_REG_FLASH_PRAR_PRG2   (MCCI_STM32H7_REG_FLASH + 0x12C)
 Flash protection address for bank 2.
 
#define MCCI_STM32H7_REG_FLASH_SCAR_CUR1   (MCCI_STM32H7_REG_FLASH + 0x030)
 Flash secure address for bank 1.
 
#define MCCI_STM32H7_REG_FLASH_SCAR_CUR2   (MCCI_STM32H7_REG_FLASH + 0x130)
 Flash secure address for bank 2.
 
#define MCCI_STM32H7_REG_FLASH_SCAR_PRG1   (MCCI_STM32H7_REG_FLASH + 0x034)
 Flash secure address for bank 1.
 
#define MCCI_STM32H7_REG_FLASH_SCAR_PRG2   (MCCI_STM32H7_REG_FLASH + 0x134)
 Flash secure address for bank 2.
 
#define MCCI_STM32H7_REG_FLASH_SR1   (MCCI_STM32H7_REG_FLASH + 0x010)
 Flash status register for bank 1.
 
#define MCCI_STM32H7_REG_FLASH_SR2   (MCCI_STM32H7_REG_FLASH + 0x110)
 Flash status register for bank 2.
 
#define MCCI_STM32H7_REG_FLASH_WPSGN_CUR1   (MCCI_STM32H7_REG_FLASH + 0x038)
 Flash write sector group protection for bank 1.
 
#define MCCI_STM32H7_REG_FLASH_WPSGN_CUR2   (MCCI_STM32H7_REG_FLASH + 0x138)
 Flash write sector group protection for bank 2.
 
#define MCCI_STM32H7_REG_FLASH_WPSGN_PRG1   (MCCI_STM32H7_REG_FLASH + 0x03C)
 Flash write sector group protection for bank 1.
 
#define MCCI_STM32H7_REG_FLASH_WPSGN_PRG2   (MCCI_STM32H7_REG_FLASH + 0x13C)
 Flash write sector group protection for bank 2.
 
FLASH_ACR bits
#define MCCI_STM32H7_REG_FLASH_ACR_LATENCY   (UINT32_C(0xF) << 0)
 Read latency:
 
#define MCCI_STM32H7_REG_FLASH_ACR_LATENCY_V(n)   (UINT32_C(n) << 0)
 Read latency: n wait state.
 
#define MCCI_STM32H7_REG_FLASH_ACR_RSV6   UINT32_C(0xFFFFFFC0)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_ACR_WRHIGHFREQ   (UINT32_C(3) << 4)
 Flash signal delay.
 
#define MCCI_STM32H7_REG_FLASH_ACR_WRHIGHFREQ_V(n)   (UINT32_C(n) << 4)
 Flash signal delay.
 
FLASH_KEYR1, FLASH_KEYR2 bits
#define MCCI_STM32H7_REG_FLASH_KEYR_UNLOCK1   UINT32_C(0x45670123)
 unlock word 1 for FLASH_CR1
 
#define MCCI_STM32H7_REG_FLASH_KEYR_UNLOCK2   UINT32_C(0xCDEF89AB)
 unlock word 2 for FLASH_CR1
 
FLASH_OPTKEYR bits
#define MCCI_STM32H7_REG_FLASH_OPTKEYR_UNLOCK1   UINT32_C(0x08192A3B)
 unlock word 1 for option bytes
 
#define MCCI_STM32H7_REG_FLASH_OPTKEYR_UNLOCK2   UINT32_C(0x4C5D6E7F)
 unlock word 2 for option bytes
 
FLASH_CR1, FLASH_CR2 bits
#define MCCI_STM32H7_REG_FLASH_CR_BER   (UINT32_C(1) << 3)
 Bank erase request.
 
#define MCCI_STM32H7_REG_FLASH_CR_CRC_EN   (UINT32_C(1) << 15)
 CRC control.
 
#define MCCI_STM32H7_REG_FLASH_CR_CRCENDIE   (UINT32_C(1) << 27)
 CRC end of calculation interrupt enable.
 
#define MCCI_STM32H7_REG_FLASH_CR_CRCRDERRIE   (UINT32_C(1) << 28)
 ECC CRC read error interrupt enable.
 
#define MCCI_STM32H7_REG_FLASH_CR_DBECCERRIE   (UINT32_C(1) << 26)
 ECC double detection error interrupt enable.
 
#define MCCI_STM32H7_REG_FLASH_CR_EOPIE   (UINT32_C(1) << 16)
 End-of-program interrupt control.
 
#define MCCI_STM32H7_REG_FLASH_CR_FW   (UINT32_C(1) << 4)
 Write forcing control.
 
#define MCCI_STM32H7_REG_FLASH_CR_INCERRIE   (UINT32_C(1) << 21)
 inconsistency error interrupt enable
 
#define MCCI_STM32H7_REG_FLASH_CR_LOCK   (UINT32_C(1) << 0)
 Lock the FLASH_CR register.
 
#define MCCI_STM32H7_REG_FLASH_CR_PG   (UINT32_C(1) << 1)
 Internal buffer control.
 
#define MCCI_STM32H7_REG_FLASH_CR_PGSERRIE   (UINT32_C(1) << 18)
 programming sequence error interrupt enable
 
#define MCCI_STM32H7_REG_FLASH_CR_RDPERRIE   (UINT32_C(1) << 23)
 read protection error interrupt enable
 
#define MCCI_STM32H7_REG_FLASH_CR_RDSERRIE   (UINT32_C(1) << 24)
 secure error interrupt enable
 
#define MCCI_STM32H7_REG_FLASH_CR_RSV13   (UINT32_C(3) << 13)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_CR_RSV20   (UINT32_C(1) << 20)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_CR_RSV22   (UINT32_C(1) << 22)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_CR_RSV29   (UINT32_C(7) << 29)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_CR_SER   (UINT32_C(1) << 2)
 Sector erase request.
 
#define MCCI_STM32H7_REG_FLASH_CR_SNECCERRIE   (UINT32_C(1) << 25)
 ECC single correction error interrupt enable.
 
#define MCCI_STM32H7_REG_FLASH_CR_SSN   (UINT32_C(0x7F) << 6)
 Sector erase selection number.
 
#define MCCI_STM32H7_REG_FLASH_CR_SSN_N(n)   ((n) << 6)
 Sector erase selection number.
 
#define MCCI_STM32H7_REG_FLASH_CR_START   (UINT32_C(1) << 5)
 Erase start control.
 
#define MCCI_STM32H7_REG_FLASH_CR_STRBERRIE   (UINT32_C(1) << 19)
 strobe error interrupt enable
 
#define MCCI_STM32H7_REG_FLASH_CR_WRPERRIE   (UINT32_C(1) << 17)
 write protection error interrupt enable
 
FLASH_SR1, FLASH_SR2 bits
#define MCCI_STM32H7_REG_FLASH_SR_BSY   (UINT32_C(1) << 0)
 Busy flag.
 
#define MCCI_STM32H7_REG_FLASH_SR_CRC_BUSY   (UINT32_C(1) << 3)
 CRC busy flag.
 
#define MCCI_STM32H7_REG_FLASH_SR_CRCEND   (UINT32_C(1) << 27)
 CRC end of calculation flag.
 
#define MCCI_STM32H7_REG_FLASH_SR_CRCRDERR   (UINT32_C(1) << 28)
 ECC CRC read error flag.
 
#define MCCI_STM32H7_REG_FLASH_SR_DBECCERR   (UINT32_C(1) << 26)
 ECC double detection error flag.
 
#define MCCI_STM32H7_REG_FLASH_SR_EOP   (UINT32_C(1) << 16)
 End-of-program flag.
 
#define MCCI_STM32H7_REG_FLASH_SR_INCERR   (UINT32_C(1) << 21)
 inconsistency error flag
 
#define MCCI_STM32H7_REG_FLASH_SR_PGSERR   (UINT32_C(1) << 18)
 programming sequence error flag
 
#define MCCI_STM32H7_REG_FLASH_SR_QW   (UINT32_C(1) << 2)
 wait queue flag
 
#define MCCI_STM32H7_REG_FLASH_SR_RDPERR   (UINT32_C(1) << 23)
 read protection error flag
 
#define MCCI_STM32H7_REG_FLASH_SR_RDSERR   (UINT32_C(1) << 24)
 secure error flag
 
#define MCCI_STM32H7_REG_FLASH_SR_RSV20   (UINT32_C(1) << 20)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_SR_RSV22   (UINT32_C(1) << 22)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_SR_RSV29   (UINT32_C(7) << 29)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_SR_RSV4   (UINT32_C(0xFFF) << 4)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_SR_SNECCERR   (UINT32_C(1) << 25)
 ECC single correction error flag.
 
#define MCCI_STM32H7_REG_FLASH_SR_STRBERR   (UINT32_C(1) << 19)
 strobe error flag
 
#define MCCI_STM32H7_REG_FLASH_SR_WBNE   (UINT32_C(1) << 1)
 write buffer not empty flag
 
#define MCCI_STM32H7_REG_FLASH_SR_WRPERR   (UINT32_C(1) << 17)
 write protection error flag
 
FLASH_CCR1, FLASH_CCR2 bits
#define MCCI_STM32H7_REG_FLASH_CCR_CRCEND   (UINT32_C(1) << 27)
 CRCEND flag clear.
 
#define MCCI_STM32H7_REG_FLASH_CCR_CRCRDERR   (UINT32_C(1) << 28)
 CRCRDERR flag clear.
 
#define MCCI_STM32H7_REG_FLASH_CCR_DBECCERR   (UINT32_C(1) << 26)
 DBECCERR flag clear.
 
#define MCCI_STM32H7_REG_FLASH_CCR_EOP   (UINT32_C(1) << 16)
 EOP flag clear.
 
#define MCCI_STM32H7_REG_FLASH_CCR_INCERR   (UINT32_C(1) << 21)
 INCERR flag clear.
 
#define MCCI_STM32H7_REG_FLASH_CCR_PGSERR   (UINT32_C(1) << 18)
 PGSERR flag clear.
 
#define MCCI_STM32H7_REG_FLASH_CCR_RDPERR   (UINT32_C(1) << 23)
 RDPERR flag clear.
 
#define MCCI_STM32H7_REG_FLASH_CCR_RDSERR   (UINT32_C(1) << 24)
 RDSERR flag clear.
 
#define MCCI_STM32H7_REG_FLASH_CCR_RSV0   (UINT32_C(0xFFFF) << 0)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_CCR_RSV20   (UINT32_C(1) << 20)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_CCR_RSV22   (UINT32_C(1) << 22)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_CCR_RSV29   (UINT32_C(7) << 29)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_CCR_SNECCERR   (UINT32_C(1) << 25)
 SNECCERR flag clear.
 
#define MCCI_STM32H7_REG_FLASH_CCR_STRBERR   (UINT32_C(1) << 19)
 STRBERR flag clear.
 
FLASH_OPTCR bits
#define MCCI_STM32H7_REG_FLASH_OPTCR_MER   (UINT32_C(1) << 4)
 mass erase request
 
#define MCCI_STM32H7_REG_FLASH_OPTCR_OPTCHANGEERRIE   (UINT32_C(1) << 30)
 Option byte change error interrupt enable.
 
#define MCCI_STM32H7_REG_FLASH_OPTCR_OPTLOCK   (UINT32_C(1) << 0)
 FLASH_OPTCR lock option configuration.
 
#define MCCI_STM32H7_REG_FLASH_OPTCR_OPTSTART   (UINT32_C(1) << 1)
 Option byte start change option configuration.
 
#define MCCI_STM32H7_REG_FLASH_OPTCR_PG_OTP   (UINT32_C(1) << 5)
 OTP program control.
 
#define MCCI_STM32H7_REG_FLASH_OPTCR_RSV22   (UINT32_C(3) << 2)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_OPTCR_RSV29   (UINT32_C(1) << 29)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_OPTCR_SWAP_BANK   (UINT32_C(1) << 31)
 Bank swapping option configuration.
 
FLASH_OPTSR_CUR, FLASH_OPTSR_PRG bits
#define MCCI_STM32H7_REG_FLASH_OPTSR_BOR_LEV   (UINT32_C(3) << 2)
 Brownout level option status.
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_BOR_LEV_1   (UINT32_C(1) << 2)
 BOR Level 1, the threshold level is low (around 2.1 V)
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_BOR_LEV_2   (UINT32_C(2) << 2)
 BOR Level 2, the threshold level is medium (around 2.4 V)
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_BOR_LEV_3   (UINT32_C(3) << 2)
 BOR Level 3, the threshold level is high (around 2.7 V)
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_BOR_LEV_OFF   (UINT32_C(0) << 2)
 BOR OFF.
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_IWDG_FZ_SDBY   (UINT32_C(1) << 18)
 IWDG Standby mode freeze option status.
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_IWDG_FZ_STOP   (UINT32_C(1) << 17)
 IWDG Stop mode freeze option status.
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_IWDG_SW   (UINT32_C(1) << 4)
 IWDG control mode option status.
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_NRST_STDY   (UINT32_C(1) << 7)
 Core domain Standby entry reset option status.
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_NRST_STOP   (UINT32_C(1) << 6)
 Core domain DStop entry reset option status.
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_OPT_BUSY   (UINT32_C(1) << 0)
 Option byte change ongoing flag.
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_OPTCHANGEERR   (UINT32_C(1) << 30)
 Option byte change error flag.
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_RDP   (UINT32_C(0xFF) << 8)
 Readout protection level option status.
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_RDP_LEVEL_0   (UINT32_C(0xAA) << 8)
 global readout protection level 0
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_RDP_LEVEL_1   (UINT32_C(0xBB) << 8)
 others values: global readout protection level 1
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_RDP_LEVEL_2   (UINT32_C(0xCC) << 8)
 global readout protection level 2
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_RSV1   (UINT32_C(1) << 1)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_RSV22   (UINT32_C(0xF) << 22)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_RSV26   (UINT32_C(7) << 26)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_RSV5   (UINT32_C(1) << 5)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_SECURITY   (UINT32_C(1) << 21)
 Security enable option status.
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_ST_RAM_SIZE   (UINT32_C(3) << 19)
 ST RAM size option.
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_ST_RAM_SIZE_16KB   (UINT32_C(3) << 19)
 2KB reserved to ST code
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_ST_RAM_SIZE_2KB   (UINT32_C(0) << 19)
 2KB reserved to ST code
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_ST_RAM_SIZE_4KB   (UINT32_C(1) << 19)
 2KB reserved to ST code
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_ST_RAM_SIZE_8KB   (UINT32_C(2) << 19)
 2KB reserved to ST code
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_SWAP_BANK_OPT   (UINT32_C(1) << 31)
 Bank swapping option status.
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_VDDIO_HSLV   (UINT32_C(1) << 29)
 VDD I/O high-speed at low-voltage status.
 
#define MCCI_STM32H7_REG_FLASH_OPTSR_VDDMMC_HSLV   (UINT32_C(1) << 16)
 VDDMMC I/O high-speed at low-voltage status.
 
FLASH_OPTCCR bits
#define MCCI_STM32H7_REG_FLASH_OPTCCR_OPTCHANGEERR   (UINT32_C(1) << 30)
 OPTCHANGEERR reset.
 
#define MCCI_STM32H7_REG_FLASH_OPTCCR_RSV0   (0x3FFFFFFF)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_OPTCCR_RSV31   (UINT32_C(1) << 31)
 Reserved, don't change.
 
FLASH_PRAR_CUR1, FLASH_PRAR_PRG1, FLASH_PRAR_CUR2, FLASH_PRAR_PRG2 bits
#define MCCI_STM32H7_REG_FLASH_PRAR_DMEP   (UINT32_C(1) << 31)
 PCROP protected erase enable option status.
 
#define MCCI_STM32H7_REG_FLASH_PRAR_PROT_AREA_END   (UINT32_C(0xFFF) << 16)
 PCROP area end status.
 
#define MCCI_STM32H7_REG_FLASH_PRAR_PROT_AREA_START   (UINT32_C(0xFFF) << 0)
 PCROP area start status.
 
#define MCCI_STM32H7_REG_FLASH_PRAR_RSV12   (UINT32_C(15) << 12)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_PRAR_RSV28   (UINT32_C(7) << 28)
 Reserved, don't change.
 
FLASH_SCAR_CUR1, FLASH_SCAR_PRG1, FLASH_SCAR_CUR2, FLASH_SCAR_PRG2 bits
#define MCCI_STM32H7_REG_FLASH_SCAR_DMES   (UINT32_C(1) << 31)
 secure access protected erase enable option status
 
#define MCCI_STM32H7_REG_FLASH_SCAR_RSV12   (UINT32_C(15) << 12)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_SCAR_RSV28   (UINT32_C(7) << 28)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_SCAR_SEC_AREA_END   (UINT32_C(0xFFF) << 16)
 secure-only area end status
 
#define MCCI_STM32H7_REG_FLASH_SCAR_SEC_AREA_START   (UINT32_C(0xFFF) << 0)
 secure-only area start status
 
FLASH_WPSGN_CUR1, FLASH_WPSGN_PRG1, FLASH_WPSGN_CUR2, FLASH_WPSGN_PRG2 bits
#define MCCI_STM32H7_REG_FLASH_WPSGN_SECT(n)   (UINT32_C(1) << (((n) & 127) >> 2))
 Group embedding sectors.
 
FLASH_BOOT_CUR, FLASH_BOOT_PRG bits
#define MCCI_STM32H7_REG_FLASH_BOOT_ADD0   (UINT32_C(0xFFFF) << 0)
 boot address 0
 
#define MCCI_STM32H7_REG_FLASH_BOOT_ADD1   (UINT32_C(0xFFFF) << 16)
 boot address 1
 
FLASH_CRCCR1, FLASH_CRCCR2 bits
#define MCCI_STM32H7_REG_FLASH_CRCCR_ADD_SECT   (UINT32_C(1) << 9)
 CRC sector select bit.
 
#define MCCI_STM32H7_REG_FLASH_CRCCR_ALL_BANK   (UINT32_C(1) << 22)
 all CRC select
 
#define MCCI_STM32H7_REG_FLASH_CRCCR_CLEAN_CRC   (UINT32_C(1) << 17)
 CRC clear bit.
 
#define MCCI_STM32H7_REG_FLASH_CRCCR_CLEAN_SECT   (UINT32_C(1) << 10)
 CRC sector list clear bit.
 
#define MCCI_STM32H7_REG_FLASH_CRCCR_CRC_BURST   (UINT32_C(3) << 20)
 CRC burst size.
 
#define MCCI_STM32H7_REG_FLASH_CRCCR_CRC_BY_SECT   (UINT32_C(1) << 8)
 CRC sector mode select bit.
 
#define MCCI_STM32H7_REG_FLASH_CRCCR_CRC_SECT   (UINT32_C(0x7F) << 0)
 CRC sector number.
 
#define MCCI_STM32H7_REG_FLASH_CRCCR_RSV11   (UINT32_C(0x1F) << 11)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_CRCCR_RSV18   (UINT32_C(3) << 18)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_CRCCR_RSV23   (UINT32_C(0x1FF) << 23)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_CRCCR_RSV7   (UINT32_C(1) << 7)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_CRCCR_START_CRC   (UINT32_C(1) << 16)
 CRC start bit.
 
FLASH_CRCSADD1, FLASH_CRCSADD2 bits
#define MCCI_STM32H7_REG_FLASH_CRCSADD_CRC_START_ADDR   (UINT32_C(0x3FFFF) << 2)
 CRC start address on bank 1/2.
 
#define MCCI_STM32H7_REG_FLASH_CRCSADD_RSV0   (UINT32_C(3) << 0)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_CRCSADD_RSV20   (UINT32_C(0xFFF) << 20)
 Reserved, don't change.
 
FLASH_CRCEADD1, FLASH_CRCEADD2 bits
#define MCCI_STM32H7_REG_FLASH_CRCEADD_CRC_START_ADDR   (UINT32_C(0x3FFFF) << 2)
 CRC end address on bank 1/2.
 
#define MCCI_STM32H7_REG_FLASH_CRCEADD_RSV0   (UINT32_C(3) << 0)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_FLASH_CRCEADD_RSV20   (UINT32_C(0xFFF) << 20)
 Reserved, don't change.
 
FLASH_ECC_FA1, FLASH_ECC_FA2 bits
#define MCCI_STM32H7_REG_FLASH_ECC_FA_FAIL_ECC_ADDR   (UINT32_C(0xFFFF) << 0)
 ECC error address.
 
#define MCCI_STM32H7_REG_FLASH_ECC_FA_OTP_FAIL_ECC   (UINT32_C(1) << 31)
 OTP ECC error bit.
 
#define MCCI_STM32H7_REG_FLASH_ECC_FA_RSV16   (UINT32_C(0x7FFF) << 16)
 Reserved, don't change.
 
FLASH_OTPBL_CUR, FLASH_OTPBL_PRG bits
#define MCCI_STM32H7_REG_FLASH_OTPBL_LOCKBL   (UINT32_C(0xFFFF) << 0)
 OTP Block Lock.
 
#define MCCI_STM32H7_REG_FLASH_OTPBL_RSV16   (UINT32_C(0xFFFF) << 16)
 Reserved, don't change.
 
Flash programming constants
#define MCCI_STM32H7_FLASH_GET_BANK(f)   (((f) >> 20) & 1)
 
#define MCCI_STM32H7_FLASH_GET_SECTOR(f)   (((f) >> 13) & 0x7F)
 
#define MCCI_STM32H7_FLASH_IS_BANK2(f)   ((f) & UINT32_C(0x100000))
 
#define MCCI_STM32H7_FLASH_IS_VALID(f)   ((f) >= MCCI_STM32H7_MEMORY_FLASH && (f) <= MCCI_STM32H7_MEMORY_FLASH_END)
 
#define MCCI_STM32H7_FLASH_PROGRAM_FLASH_SIZE   UINT32_C(16)
 size in bytes of a FLASH program
 
#define MCCI_STM32H7_FLASH_PROGRAM_OTP_SIZE   UINT32_C(2)
 size in bytes of a FLASH program
 
#define MCCI_STM32H7_FLASH_SECTOR_SIZE   UINT32_C(8192)
 size in bytes of a sector
 
PWR registers
#define MCCI_STM32H7_REG_PWR_CPUCR   (MCCI_STM32H7_REG_PWR + 0x10)
 CPU control.
 
#define MCCI_STM32H7_REG_PWR_CR1   (MCCI_STM32H7_REG_PWR + 0x00)
 control
 
#define MCCI_STM32H7_REG_PWR_CR2   (MCCI_STM32H7_REG_PWR + 0x08)
 control 2
 
#define MCCI_STM32H7_REG_PWR_CR3   (MCCI_STM32H7_REG_PWR + 0x0C)
 control 3
 
#define MCCI_STM32H7_REG_PWR_CSR1   (MCCI_STM32H7_REG_PWR + 0x04)
 control status
 
#define MCCI_STM32H7_REG_PWR_SRDCR   (MCCI_STM32H7_REG_PWR + 0x18)
 SmartRun domain control.
 
#define MCCI_STM32H7_REG_PWR_WKUPCR   (MCCI_STM32H7_REG_PWR + 0x20)
 wakeup clear
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR   (MCCI_STM32H7_REG_PWR + 0x28)
 wakeup enable and polarity
 
#define MCCI_STM32H7_REG_PWR_WKUPFR   (MCCI_STM32H7_REG_PWR + 0x24)
 wakeup flag
 
PWR_CR1 bits
#define MCCI_STM32H7_REG_PWR_CR1_AHBRAM1SO   (UINT32_C(1) << 22)
 AHB SRAM1 shut-off in DStop/DStop2 mode.
 
#define MCCI_STM32H7_REG_PWR_CR1_AHBRAM2SO   (UINT32_C(1) << 23)
 AHB SRAM2 shut-off in DStop/DStop2 mode.
 
#define MCCI_STM32H7_REG_PWR_CR1_ALS   (UINT32_C(3) << 17)
 analog voltage detector level selection
 
#define MCCI_STM32H7_REG_PWR_CR1_ALS_1_7V   (UINT32_C(0) << 17)
 1.7V
 
#define MCCI_STM32H7_REG_PWR_CR1_ALS_2_1V   (UINT32_C(1) << 17)
 2.1V
 
#define MCCI_STM32H7_REG_PWR_CR1_ALS_2_5V   (UINT32_C(2) << 17)
 2.5V
 
#define MCCI_STM32H7_REG_PWR_CR1_ALS_2_8V   (UINT32_C(3) << 17)
 2.8V
 
#define MCCI_STM32H7_REG_PWR_CR1_AVD_READY   (UINT32_C(1) << 13)
 analog voltage ready
 
#define MCCI_STM32H7_REG_PWR_CR1_AVDEN   (UINT32_C(1) << 16)
 peripheral voltage monitor on VDDA enable
 
#define MCCI_STM32H7_REG_PWR_CR1_AXIRAM1SO   (UINT32_C(1) << 19)
 AXI SRAM1 shut-off in DStop/DStop2 mode.
 
#define MCCI_STM32H7_REG_PWR_CR1_AXIRAM2SO   (UINT32_C(1) << 20)
 AXI SRAM2 shut-off in DStop/DStop2 mode.
 
#define MCCI_STM32H7_REG_PWR_CR1_AXIRAM3SO   (UINT32_C(1) << 21)
 AXI SRAM3 shut-off in DStop/DStop2 mode.
 
#define MCCI_STM32H7_REG_PWR_CR1_BOOSTE   (UINT32_C(1) << 12)
 analog switch VBoost control
 
#define MCCI_STM32H7_REG_PWR_CR1_DBP   (UINT32_C(1) << 8)
 disable Backup domain write protection
 
#define MCCI_STM32H7_REG_PWR_CR1_FLPS   (UINT32_C(1) << 9)
 Flash memory low-power mode in DStop or DStop2 mode.
 
#define MCCI_STM32H7_REG_PWR_CR1_GFXSO   (UINT32_C(1) << 25)
 GFXMMU and JPEG memory shut-off in DStop/DStop2 mode.
 
#define MCCI_STM32H7_REG_PWR_CR1_HSITFSO   (UINT32_C(1) << 26)
 high-speed interfaces USB and FDCAN memory shut-off in DStop/DStop2 mode
 
#define MCCI_STM32H7_REG_PWR_CR1_ITCMSO   (UINT32_C(1) << 24)
 instruction TCM and ETM memory shut-off in DStop/DStop2 mode
 
#define MCCI_STM32H7_REG_PWR_CR1_LPDS   (UINT32_C(1) << 0)
 low-power Deepsleep with SVOS3
 
#define MCCI_STM32H7_REG_PWR_CR1_PLS   (UINT32_C(7) << 5)
 programmable voltage detector level selection
 
#define MCCI_STM32H7_REG_PWR_CR1_PLS_1_95V   (UINT32_C(0) << 5)
 1.95V
 
#define MCCI_STM32H7_REG_PWR_CR1_PLS_2_1V   (UINT32_C(1) << 5)
 2.1V
 
#define MCCI_STM32H7_REG_PWR_CR1_PLS_2_25V   (UINT32_C(2) << 5)
 2.25V
 
#define MCCI_STM32H7_REG_PWR_CR1_PLS_2_4V   (UINT32_C(3) << 5)
 2.4V
 
#define MCCI_STM32H7_REG_PWR_CR1_PLS_2_55V   (UINT32_C(4) << 5)
 2.55V
 
#define MCCI_STM32H7_REG_PWR_CR1_PLS_2_7V   (UINT32_C(5) << 5)
 2.7V
 
#define MCCI_STM32H7_REG_PWR_CR1_PLS_2_85V   (UINT32_C(6) << 5)
 2.85V
 
#define MCCI_STM32H7_REG_PWR_CR1_PLS_PVD_IN   (UINT32_C(7) << 5)
 PVD_IN pin.
 
#define MCCI_STM32H7_REG_PWR_CR1_PVDE   (UINT32_C(1) << 4)
 programmable voltage detector enable
 
#define MCCI_STM32H7_REG_PWR_CR1_RSV1   (UINT32_C(7) << 1)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_CR1_RSV10   (UINT32_C(3) << 10)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_CR1_RSV28   (UINT32_C(15) << 28)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_CR1_SRDRAMSO   (UINT32_C(1) << 27)
 SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode.
 
#define MCCI_STM32H7_REG_PWR_CR1_SVOS   (UINT32_C(3) << 14)
 system stop mode voltage scaling selection
 
#define MCCI_STM32H7_REG_PWR_CR1_SVOS_3   (UINT32_C(3) << 14)
 SVOS5 scale 3.
 
#define MCCI_STM32H7_REG_PWR_CR1_SVOS_4   (UINT32_C(2) << 14)
 SVOS5 scale 4.
 
#define MCCI_STM32H7_REG_PWR_CR1_SVOS_5   (UINT32_C(1) << 14)
 SVOS5 scale 5.
 
PWR_CSR1 bits
#define MCCI_STM32H7_REG_PWR_CSR1_ACTVOS   (UINT32_C(3) << 14)
 VOS currently applied for VCORE voltage scaling selection.
 
#define MCCI_STM32H7_REG_PWR_CSR1_ACTVOSRDY   (UINT32_C(1) << 13)
 Regulator low-power flag.
 
#define MCCI_STM32H7_REG_PWR_CSR1_AVDO   (UINT32_C(1) << 16)
 analog voltage detector output on VDDA
 
#define MCCI_STM32H7_REG_PWR_CSR1_MMCVDO   (UINT32_C(1) << 17)
 voltage detector output on VDDMMC
 
#define MCCI_STM32H7_REG_PWR_CSR1_PVDO   (UINT32_C(1) << 4)
 programmable voltage detect output
 
#define MCCI_STM32H7_REG_PWR_CSR1_RSV0   (UINT32_C(0xF) << 0)
 Reserved, do not change.
 
#define MCCI_STM32H7_REG_PWR_CSR1_RSV18   UINT32C(0xFFFC0000)
 reserved, do not change
 
#define MCCI_STM32H7_REG_PWR_CSR1_RSV5   (UINT32_C(0xFF) << 5)
 Reserved, do not change.
 
PWR_CR2 bits
#define MCCI_STM32H7_REG_PWR_CR2_BREN   (UINT32_C(1) << 0)
 backup regulator enable
 
#define MCCI_STM32H7_REG_PWR_CR2_BRRDY   (UINT32_C(1) << 16)
 backup regulator ready
 
#define MCCI_STM32H7_REG_PWR_CR2_MONEN   (UINT32_C(1) << 4)
 VBAT and temperature monitoring enable.
 
#define MCCI_STM32H7_REG_PWR_CR2_RSV1   (UINT32_C(7) << 1)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_CR2_RSV17   (UINT32_C(0x1F) << 17)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_CR2_RSV24   (UINT32_C(0xFF) << 24)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_CR2_RSV5   (UINT32_C(0x7FF) << 5)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_CR2_TEMPH   (UINT32_C(1) << 23)
 temperature level monitoring versus high threshold
 
#define MCCI_STM32H7_REG_PWR_CR2_TEMPL   (UINT32_C(1) << 22)
 temperature level monitoring versus low threshold
 
PWR_CR3 bits
#define MCCI_STM32H7_REG_PWR_CR3_BYPASS   (UINT32_C(1) << 0)
 power management unit bypass
 
#define MCCI_STM32H7_REG_PWR_CR3_LDOEN   (UINT32_C(1) << 1)
 low drop-out regulator enable
 
#define MCCI_STM32H7_REG_PWR_CR3_RSV10   (UINT32_C(0x3F) << 10)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_CR3_RSV17   (UINT32_C(0x7F) << 17)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_CR3_RSV27   (UINT32_C(0x1F) << 27)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_CR3_RSV6   (UINT32_C(3) << 6)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_CR3_SMPSEN   (UINT32_C(1) << 2)
 SMPS step-down converter enable.
 
#define MCCI_STM32H7_REG_PWR_CR3_SMPSEXTHP   (UINT32_C(1) << 3)
 SMPS step-down converter external power delivery selection.
 
#define MCCI_STM32H7_REG_PWR_CR3_SMPSEXTRDY   (UINT32_C(1) << 16)
 SMPS step-down converter external supply ready.
 
#define MCCI_STM32H7_REG_PWR_CR3_SMPSLEVEL   (UINT32_C(3) << 4)
 SMPS step-down converter voltage output level selection.
 
#define MCCI_STM32H7_REG_PWR_CR3_SMPSLEVEL_1_8V   (UINT32_C(1) << 4)
 1.8V
 
#define MCCI_STM32H7_REG_PWR_CR3_SMPSLEVEL_2_5V   (UINT32_C(2) << 4)
 2.5V
 
#define MCCI_STM32H7_REG_PWR_CR3_SMPSLEVEL_2V5   (UINT32_C(3) << 4)
 2.5V
 
#define MCCI_STM32H7_REG_PWR_CR3_USB33DEN   (UINT32_C(1) << 24)
 VDD33USB voltage level detector enable.
 
#define MCCI_STM32H7_REG_PWR_CR3_USB33RDY   (UINT32_C(1) << 26)
 USB supply ready.
 
#define MCCI_STM32H7_REG_PWR_CR3_USBREGEN   (UINT32_C(1) << 25)
 USB regulator enable.
 
#define MCCI_STM32H7_REG_PWR_CR3_VBE   (UINT32_C(1) << 8)
 VBAT charging enable.
 
#define MCCI_STM32H7_REG_PWR_CR3_VBRS   (UINT32_C(1) << 9)
 VBAT charging resistor selection.
 
PWR_CPUCR bits
#define MCCI_STM32H7_REG_PWR_CPUCR_CSSF   (UINT32_C(1) << 9)
 clear Standby and Stop flags (always read as 0)
 
#define MCCI_STM32H7_REG_PWR_CPUCR_PDDS_SRD   (UINT32_C(1) << 2)
 system SmartRun domain power down Deepsleep
 
#define MCCI_STM32H7_REG_PWR_CPUCR_RETDS_CD   (UINT32_C(1) << 0)
 CPU domain power down Deepsleep selection.
 
#define MCCI_STM32H7_REG_PWR_CPUCR_RSV1   (UINT32_C(1) << 1)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_CPUCR_RSV10   (UINT32_C(1) << 10)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_CPUCR_RSV12   UINT32_C(0xFFFFF000)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_CPUCR_RSV3   (UINT32_C(3) << 3)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_CPUCR_RSV7   (UINT32_C(3) << 7)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_CPUCR_RUN_SRD   (UINT32_C(1) << 11)
 temperature level monitoring versus high threshold
 
#define MCCI_STM32H7_REG_PWR_CPUCR_SBF   (UINT32_C(1) << 6)
 system Standby flag
 
#define MCCI_STM32H7_REG_PWR_CPUCR_STOPF   (UINT32_C(1) << 5)
 STOP flag.
 
PWR_SRDCR bits
#define MCCI_STM32H7_REG_PWR_SRDCR_RSV0   UINT32_C(0x00001FFF)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_SRDCR_RSV16   UINT32_C(0xFFFF0000)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_SRDCR_VOS   (UINT32_C(3) << 14)
 voltage scaling selection according to performance
 
#define MCCI_STM32H7_REG_PWR_SRDCR_VOS_SCALE0   (UINT32_C(3) << 14)
 scale 0
 
#define MCCI_STM32H7_REG_PWR_SRDCR_VOS_SCALE1   (UINT32_C(2) << 14)
 scale 1
 
#define MCCI_STM32H7_REG_PWR_SRDCR_VOS_SCALE2   (UINT32_C(1) << 14)
 scale 2
 
#define MCCI_STM32H7_REG_PWR_SRDCR_VOS_SCALE3   (UINT32_C(0) << 14)
 scale 3
 
#define MCCI_STM32H7_REG_PWR_SRDCR_VOSRDY   (UINT32_C(1) << 13)
 VOS ready bit for VCORE voltage scaling output selection.
 
PWR_WKUPCR bits
#define MCCI_STM32H7_REG_PWR_WKUPCR_RSV6   UINT32_C(0xFFFFFC00)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC(n)   (UINT32_C(1) << ((n)-1))
 
#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC1   (UINT32_C(1) << 0)
 clear wakeup pin flag for WKUP1
 
#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC2   (UINT32_C(1) << 1)
 clear wakeup pin flag for WKUP2
 
#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC3   (UINT32_C(1) << 2)
 clear wakeup pin flag for WKUP3
 
#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC4   (UINT32_C(1) << 3)
 clear wakeup pin flag for WKUP4
 
#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC5   (UINT32_C(1) << 4)
 clear wakeup pin flag for WKUP5
 
#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC6   (UINT32_C(1) << 5)
 clear wakeup pin flag for WKUP6
 
PWR_WKUPFR bits
#define MCCI_STM32H7_REG_PWR_WKUPFR_RSV6   UINT32_C(0xFFFFFC00)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF(n)   (UINT32_C(1) << ((n)-1))
 
#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF1   (UINT32_C(1) << 0)
 wakeup pin flag for WKUP1
 
#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF2   (UINT32_C(1) << 1)
 wakeup pin flag for WKUP2
 
#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF3   (UINT32_C(1) << 2)
 wakeup pin flag for WKUP3
 
#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF4   (UINT32_C(1) << 3)
 wakeup pin flag for WKUP4
 
#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF5   (UINT32_C(1) << 4)
 wakeup pin flag for WKUP5
 
#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF6   (UINT32_C(1) << 5)
 wakeup pin flag for WKUP6
 
PWR_WKUPEPR bits
#define MCCI_STM32H7_REG_PWR_WKUPEPR_NOPU(n)   (UINT32_C(0) << ((((n)-1)*2)+16))
 no pull-up WKUPn
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_PD(n)   (UINT32_C(2) << ((((n)-1)*2)+16))
 pull-down WKUPn
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_PU(n)   (UINT32_C(1) << ((((n)-1)*2)+16))
 pull-up WKUPn
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD1   (UINT32_C(3) << 16)
 wakeup pin pull configuration for WKUP1
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD2   (UINT32_C(3) << 18)
 wakeup pin pull configuration for WKUP2
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD3   (UINT32_C(3) << 20)
 wakeup pin pull configuration for WKUP3
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD4   (UINT32_C(3) << 22)
 wakeup pin pull configuration for WKUP4
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD5   (UINT32_C(3) << 24)
 wakeup pin pull configuration for WKUP5
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD6   (UINT32_C(3) << 26)
 wakeup pin pull configuration for WKUP6
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_RSV14   (UINT32_C(3) << 14)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_RSV28   UINT32_C(0xF0000000)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_RSV6   (UINT32_C(3) << 6)
 Reserved, don't change.
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN1   (UINT32_C(1) << 0)
 enable wakeup pin for WKUP1
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN2   (UINT32_C(1) << 1)
 enable wakeup pin for WKUP2
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN3   (UINT32_C(1) << 2)
 enable wakeup pin for WKUP3
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN4   (UINT32_C(1) << 3)
 enable wakeup pin for WKUP4
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN5   (UINT32_C(1) << 4)
 enable wakeup pin for WKUP5
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN6   (UINT32_C(1) << 5)
 enable wakeup pin for WKUP6
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP1   (UINT32_C(1) << 8)
 wakeup pin polarity for WKUP1
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP2   (UINT32_C(1) << 9)
 wakeup pin polarity for WKUP2
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP3   (UINT32_C(1) << 10)
 wakeup pin polarity for WKUP3
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP4   (UINT32_C(1) << 11)
 wakeup pin polarity for WKUP4
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP5   (UINT32_C(1) << 12)
 wakeup pin polarity for WKUP5
 
#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP6   (UINT32_C(1) << 13)
 wakeup pin polarity for WKUP6
 
RCC registers
#define MCCI_STM32H7_REG_RCC_AHB1ENR   (MCCI_STM32H7_REG_RCC + 0x138)
 AHB1 clock.
 
#define MCCI_STM32H7_REG_RCC_AHB1LPENR   (MCCI_STM32H7_REG_RCC + 0x160)
 AHB1 sleep clock.
 
#define MCCI_STM32H7_REG_RCC_AHB1RSTR   (MCCI_STM32H7_REG_RCC + 0x80)
 AHB1 peripheral reset.
 
#define MCCI_STM32H7_REG_RCC_AHB2ENR   (MCCI_STM32H7_REG_RCC + 0x13C)
 AHB2 clock.
 
#define MCCI_STM32H7_REG_RCC_AHB2LPENR   (MCCI_STM32H7_REG_RCC + 0x164)
 AHB2 sleep clock.
 
#define MCCI_STM32H7_REG_RCC_AHB2RSTR   (MCCI_STM32H7_REG_RCC + 0x84)
 AHB2 peripheral reset.
 
#define MCCI_STM32H7_REG_RCC_AHB3ENR   (MCCI_STM32H7_REG_RCC + 0x134)
 AHB3 clock.
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR   (MCCI_STM32H7_REG_RCC + 0x15C)
 AHB3 sleep clock.
 
#define MCCI_STM32H7_REG_RCC_AHB3RSTR   (MCCI_STM32H7_REG_RCC + 0x7C)
 AHB3 reset.
 
#define MCCI_STM32H7_REG_RCC_AHB4ENR   (MCCI_STM32H7_REG_RCC + 0x140)
 AHB4 clock.
 
#define MCCI_STM32H7_REG_RCC_AHB4LPENR   (MCCI_STM32H7_REG_RCC + 0x168)
 AHB4 sleep clock.
 
#define MCCI_STM32H7_REG_RCC_AHB4RSTR   (MCCI_STM32H7_REG_RCC + 0x88)
 AHB4 peripheral reset.
 
#define MCCI_STM32H7_REG_RCC_APB1HENR   (MCCI_STM32H7_REG_RCC + 0x14C)
 APB1 clock.
 
#define MCCI_STM32H7_REG_RCC_APB1HLPENR   (MCCI_STM32H7_REG_RCC + 0x174)
 APB1 high-sleep clock.
 
#define MCCI_STM32H7_REG_RCC_APB1HRSTR   (MCCI_STM32H7_REG_RCC + 0x94)
 APB1 peripheral reset.
 
#define MCCI_STM32H7_REG_RCC_APB1LENR   (MCCI_STM32H7_REG_RCC + 0x148)
 APB1 clock.
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR   (MCCI_STM32H7_REG_RCC + 0x170)
 APB1 low-sleep clock.
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR   (MCCI_STM32H7_REG_RCC + 0x90)
 APB1 peripheral reset.
 
#define MCCI_STM32H7_REG_RCC_APB2ENR   (MCCI_STM32H7_REG_RCC + 0x150)
 APB2 clock.
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR   (MCCI_STM32H7_REG_RCC + 0x178)
 APB2 sleep clock.
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR   (MCCI_STM32H7_REG_RCC + 0x98)
 APB2 peripheral reset.
 
#define MCCI_STM32H7_REG_RCC_APB3ENR   (MCCI_STM32H7_REG_RCC + 0x144)
 APB3 clock.
 
#define MCCI_STM32H7_REG_RCC_APB3LPENR   (MCCI_STM32H7_REG_RCC + 0x16C)
 APB3 sleep clock.
 
#define MCCI_STM32H7_REG_RCC_APB3RSTR   (MCCI_STM32H7_REG_RCC + 0x8C)
 APB3 peripheral reset.
 
#define MCCI_STM32H7_REG_RCC_APB4ENR   (MCCI_STM32H7_REG_RCC + 0x154)
 APB4 clock.
 
#define MCCI_STM32H7_REG_RCC_APB4LPENR   (MCCI_STM32H7_REG_RCC + 0x17C)
 APB4 sleep clock.
 
#define MCCI_STM32H7_REG_RCC_APB4RSTR   (MCCI_STM32H7_REG_RCC + 0x9C)
 APB4 peripheral reset.
 
#define MCCI_STM32H7_REG_RCC_BDCR   (MCCI_STM32H7_REG_RCC + 0x70)
 Backup domain control.
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R   (MCCI_STM32H7_REG_RCC + 0x50)
 CPU domain kernel clock configuration.
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R   (MCCI_STM32H7_REG_RCC + 0x54)
 CPU domain kernel clock configuration.
 
#define MCCI_STM32H7_REG_RCC_CDCCIPR   (MCCI_STM32H7_REG_RCC + 0x4C)
 CPU domain kernel clock configuration.
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1   (MCCI_STM32H7_REG_RCC + 0x14)
 CPU domain clock configuration.
 
#define MCCI_STM32H7_REG_RCC_CDCFGR2   (MCCI_STM32H7_REG_RCC + 0x18)
 CPU domain clock configuration.
 
#define MCCI_STM32H7_REG_RCC_CFGR   (MCCI_STM32H7_REG_RCC + 0x10)
 Clock configuration.
 
#define MCCI_STM32H7_REG_RCC_CICR   (MCCI_STM32H7_REG_RCC + 0x68)
 clock source interrupt clear
 
#define MCCI_STM32H7_REG_RCC_CIER   (MCCI_STM32H7_REG_RCC + 0x60)
 clock source interrupt enable
 
#define MCCI_STM32H7_REG_RCC_CIFR   (MCCI_STM32H7_REG_RCC + 0x64)
 clock source interrupt flag
 
#define MCCI_STM32H7_REG_RCC_CKGAENR   (MCCI_STM32H7_REG_RCC + 0xB0)
 AXI clocks gating enable.
 
#define MCCI_STM32H7_REG_RCC_CR   (MCCI_STM32H7_REG_RCC + 0x00)
 source control
 
#define MCCI_STM32H7_REG_RCC_CRRCR   (MCCI_STM32H7_REG_RCC + 0x08)
 Clock recovery RC.
 
#define MCCI_STM32H7_REG_RCC_CSICFGR   (MCCI_STM32H7_REG_RCC + 0x0C)
 CSI calibration.
 
#define MCCI_STM32H7_REG_RCC_CSR   (MCCI_STM32H7_REG_RCC + 0x74)
 clock control and status
 
#define MCCI_STM32H7_REG_RCC_HSICFGR   (MCCI_STM32H7_REG_RCC + 0x04)
 HSI calibration.
 
#define MCCI_STM32H7_REG_RCC_PLL1DIVR   (MCCI_STM32H7_REG_RCC + 0x30)
 PLL1 dividers configuration.
 
#define MCCI_STM32H7_REG_RCC_PLL1FRACR   (MCCI_STM32H7_REG_RCC + 0x34)
 PLL1 fractional divider.
 
#define MCCI_STM32H7_REG_RCC_PLL2DIVR   (MCCI_STM32H7_REG_RCC + 0x38)
 PLL2 dividers configuration.
 
#define MCCI_STM32H7_REG_RCC_PLL2FRACR   (MCCI_STM32H7_REG_RCC + 0x3C)
 PLL2 fractional divider.
 
#define MCCI_STM32H7_REG_RCC_PLL3DIVR   (MCCI_STM32H7_REG_RCC + 0x40)
 PLL3 dividers configuration.
 
#define MCCI_STM32H7_REG_RCC_PLL3FRACR   (MCCI_STM32H7_REG_RCC + 0x44)
 PLL4 fractional divider.
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR   (MCCI_STM32H7_REG_RCC + 0x2C)
 PLLs configuration.
 
#define MCCI_STM32H7_REG_RCC_PLLCKSELR   (MCCI_STM32H7_REG_RCC + 0x28)
 PLLs clock source selection.
 
#define MCCI_STM32H7_REG_RCC_RSR   (MCCI_STM32H7_REG_RCC + 0x130)
 reset status
 
#define MCCI_STM32H7_REG_RCC_SRDAMR   (MCCI_STM32H7_REG_RCC + 0xA8)
 SmartRun domain Autonomous mode.
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR   (MCCI_STM32H7_REG_RCC + 0x58)
 SmartRun domain kernel clock configuration.
 
#define MCCI_STM32H7_REG_RCC_SRDCFGR   (MCCI_STM32H7_REG_RCC + 0x20)
 SmartRun domain clock configuration.
 
RCC_CR bits
#define MCCI_STM32H7_REG_RCC_CR_CDCKRDY   (UINT32_C(1) << 15)
 
#define MCCI_STM32H7_REG_RCC_CR_CPUCKRDY   (UINT32_C(1) << 14)
 
#define MCCI_STM32H7_REG_RCC_CR_CSIKERON   (UINT32_C(1) << 9)
 
#define MCCI_STM32H7_REG_RCC_CR_CSION   (UINT32_C(1) << 7)
 
#define MCCI_STM32H7_REG_RCC_CR_CSIRDY   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_CR_HSEBYP   (UINT32_C(1) << 18)
 
#define MCCI_STM32H7_REG_RCC_CR_HSECSSON   (UINT32_C(1) << 19)
 
#define MCCI_STM32H7_REG_RCC_CR_HSEEXT   (UINT32_C(1) << 20)
 
#define MCCI_STM32H7_REG_RCC_CR_HSEON   (UINT32_C(1) << 16)
 
#define MCCI_STM32H7_REG_RCC_CR_HSERDY   (UINT32_C(1) << 17)
 
#define MCCI_STM32H7_REG_RCC_CR_HSI48ON   (UINT32_C(1) << 12)
 
#define MCCI_STM32H7_REG_RCC_CR_HSI48RDY   (UINT32_C(1) << 13)
 
#define MCCI_STM32H7_REG_RCC_CR_HSIDIV   (UINT32_C(3) << 3)
 
#define MCCI_STM32H7_REG_RCC_CR_HSIDIV_1   (UINT32_C(0) << 3)
 
#define MCCI_STM32H7_REG_RCC_CR_HSIDIV_2   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_CR_HSIDIV_3   (UINT32_C(2) << 3)
 
#define MCCI_STM32H7_REG_RCC_CR_HSIDIV_8   (UINT32_C(3) << 3)
 
#define MCCI_STM32H7_REG_RCC_CR_HSIDIVF   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_CR_HSIKERON   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_CR_HSION   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_CR_HSIRDY   (UINT32_C(1) << 2)
 
#define MCCI_STM32H7_REG_RCC_CR_PLL1ON   (UINT32_C(1) << 24)
 
#define MCCI_STM32H7_REG_RCC_CR_PLL1RDY   (UINT32_C(1) << 25)
 
#define MCCI_STM32H7_REG_RCC_CR_PLL2ON   (UINT32_C(1) << 26)
 
#define MCCI_STM32H7_REG_RCC_CR_PLL2RDY   (UINT32_C(1) << 27)
 
#define MCCI_STM32H7_REG_RCC_CR_PLL3ON   (UINT32_C(1) << 28)
 
#define MCCI_STM32H7_REG_RCC_CR_PLL3RDY   (UINT32_C(1) << 29)
 
#define MCCI_STM32H7_REG_RCC_CR_RSV10   (UINT32_C(3) << 10)
 
#define MCCI_STM32H7_REG_RCC_CR_RSV21   (UINT32_C(7) << 21)
 
#define MCCI_STM32H7_REG_RCC_CR_RSV30   (UINT32_C(3) << 30)
 
#define MCCI_STM32H7_REG_RCC_CR_RSV6   (UINT32_C(1) << 6)
 
RCC_HSICFGR bits
#define MCCI_STM32H7_REG_RCC_HSICFGR_HSICAL   (UINT32_C(0xFFF) << 0)
 
#define MCCI_STM32H7_REG_RCC_HSICFGR_HSITRIM   (UINT32_C(0x7F) << 24)
 
#define MCCI_STM32H7_REG_RCC_HSICFGR_RSV12   (UINT32_C(0xFFF) << 12)
 
#define MCCI_STM32H7_REG_RCC_HSICFGR_RSV31   (UINT32_C(1) << 31)
 
RCC_CRRCR bits
#define MCCI_STM32H7_REG_RCC_CRRCR_HSI48CAL   (UINT32_C(0x3FF) << 0)
 
#define MCCI_STM32H7_REG_RCC_CRRCR_RSV10   UINT32_C(0xFFFFFC00)
 
RCC_CSICFGR bits
#define MCCI_STM32H7_REG_RCC_CSICFGR_CSICAL   (UINT32_C(0xFF) << 0)
 
#define MCCI_STM32H7_REG_RCC_CSICFGR_CSITRIM   (UINT32_C(0x3F) << 24)
 
#define MCCI_STM32H7_REG_RCC_CSICFGR_RSV30   (UINT32_C(3) << 30)
 
#define MCCI_STM32H7_REG_RCC_CSICFGR_RSV8   (UINT32_C(0xFFFF) << 8)
 
RCC_CFGR bits
#define MCCI_STM32H7_REG_RCC_CFGR_MCO1PRE   (UINT32_C(0xF) << 18)
 
#define MCCI_STM32H7_REG_RCC_CFGR_MCO1PRE_DIS   (UINT32_C(0) << 18)
 
#define MCCI_STM32H7_REG_RCC_CFGR_MCO1PRE_N(n)   ((n) << 18)
 
#define MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL   (UINT32_C(7) << 22)
 
#define MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL_HSE   (UINT32_C(2) << 22)
 
#define MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL_HSI   (UINT32_C(0) << 22)
 
#define MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL_HSI48   (UINT32_C(4) << 22)
 
#define MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL_LSE   (UINT32_C(1) << 22)
 
#define MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL_PLL1   (UINT32_C(3) << 22)
 
#define MCCI_STM32H7_REG_RCC_CFGR_MCO2PRE   (UINT32_C(0xF) << 25)
 
#define MCCI_STM32H7_REG_RCC_CFGR_MCO2PRE_DIS   (UINT32_C(0) << 25)
 
#define MCCI_STM32H7_REG_RCC_CFGR_MCO2PRE_N(n)   ((n) << 25)
 
#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL   (UINT32_C(7) << 29)
 
#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_CSI   (UINT32_C(4) << 29)
 
#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_HSE   (UINT32_C(2) << 29)
 
#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_LSI   (UINT32_C(5) << 29)
 
#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_PLL1   (UINT32_C(3) << 29)
 
#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_PLL2   (UINT32_C(1) << 29)
 
#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_SYS   (UINT32_C(0) << 29)
 
#define MCCI_STM32H7_REG_RCC_CFGR_RSV14   (UINT32_C(1) << 14)
 
#define MCCI_STM32H7_REG_RCC_CFGR_RSV16   (UINT32_C(3) << 16)
 
#define MCCI_STM32H7_REG_RCC_CFGR_RTCPRE   (UINT32_C(0x3F) << 8)
 
#define MCCI_STM32H7_REG_RCC_CFGR_RTCPRE_DIS   (UINT32_C(0) << 8)
 
#define MCCI_STM32H7_REG_RCC_CFGR_RTCPRE_N(n)   ((n) << 8)
 
#define MCCI_STM32H7_REG_RCC_CFGR_STOPKERWUCK   (UINT32_C(1) << 7)
 
#define MCCI_STM32H7_REG_RCC_CFGR_STOPWUCK   (UINT32_C(1) << 6)
 
#define MCCI_STM32H7_REG_RCC_CFGR_SW   (UINT32_C(3) << 0)
 
#define MCCI_STM32H7_REG_RCC_CFGR_SW_CSI   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_CFGR_SW_HSE   (UINT32_C(2) << 0)
 
#define MCCI_STM32H7_REG_RCC_CFGR_SW_HSI   (UINT32_C(0) << 0)
 
#define MCCI_STM32H7_REG_RCC_CFGR_SW_PLL1   (UINT32_C(3) << 0)
 
#define MCCI_STM32H7_REG_RCC_CFGR_SWS   (UINT32_C(7) << 3)
 
#define MCCI_STM32H7_REG_RCC_CFGR_SWS_CSI   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_CFGR_SWS_HSE   (UINT32_C(2) << 3)
 
#define MCCI_STM32H7_REG_RCC_CFGR_SWS_HSI   (UINT32_C(0) << 3)
 
#define MCCI_STM32H7_REG_RCC_CFGR_SWS_PLL1   (UINT32_C(3) << 3)
 
#define MCCI_STM32H7_REG_RCC_CFGR_TIMPRE   (UINT32_C(1) << 15)
 
RCC_CDCFGR1 bits
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE   (UINT32_C(0xF) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_1   (UINT32_C(0) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_128   (UINT32_C(0xD) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_16   (UINT32_C(0xB) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_2   (UINT32_C(0x8) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_256   (UINT32_C(0xE) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_4   (UINT32_C(0x9) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_5   (UINT32_C(0xA) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_512   (UINT32_C(0xF) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_64   (UINT32_C(0xC) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE   (UINT32_C(7) << 4)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE_1   (UINT32_C(0) << 4)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE_16   (UINT32_C(7) << 4)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE_2   (UINT32_C(4) << 4)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE_3   (UINT32_C(5) << 4)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE_8   (UINT32_C(6) << 4)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE   (UINT32_C(0xF) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_1   (UINT32_C(0) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_128   (UINT32_C(0xD) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_16   (UINT32_C(0xB) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_2   (UINT32_C(0x8) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_256   (UINT32_C(0xE) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_4   (UINT32_C(0x9) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_512   (UINT32_C(0xF) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_64   (UINT32_C(0xC) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_8   (UINT32_C(0xA) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_RSV12   UINT32_C(0xFFFFF000)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR1_RSV7   (UINT32_C(1) << 7)
 
RCC_CDCFGR2 bits
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1   (UINT32_C(7) << 4)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1_1   (UINT32_C(0) << 4)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1_16   (UINT32_C(7) << 4)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1_2   (UINT32_C(4) << 4)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1_3   (UINT32_C(5) << 4)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1_8   (UINT32_C(6) << 4)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2   (UINT32_C(7) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2_1   (UINT32_C(0) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2_16   (UINT32_C(7) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2_2   (UINT32_C(4) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2_3   (UINT32_C(5) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2_8   (UINT32_C(6) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR2_RSV0   (UINT32_C(0xF) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR2_RSV11   UINT32_C(0xFFFFF800)
 
#define MCCI_STM32H7_REG_RCC_CDCFGR2_RSV7   (UINT32_C(1) << 7)
 
RCC_SRDCFGR bits
#define MCCI_STM32H7_REG_RCC_SRDCFGR_RSV0   (UINT32_C(0xF) << 0)
 
#define MCCI_STM32H7_REG_RCC_SRDCFGR_RSV7   UINT32_C(0xFFFFFF80)
 
#define MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE   (UINT32_C(7) << 4)
 
#define MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE_1   (UINT32_C(0) << 4)
 
#define MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE_16   (UINT32_C(7) << 4)
 
#define MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE_2   (UINT32_C(4) << 4)
 
#define MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE_3   (UINT32_C(5) << 4)
 
#define MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE_8   (UINT32_C(6) << 4)
 
RCC_PLLCKSELR bits
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM1   (UINT32_C(0x3F) << 14)
 
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM1_DIS   (UINT32_C(0x3F) << 14)
 
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM1_N(n)   ((n) << 14)
 
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM2   (UINT32_C(0x3F) << 12)
 
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM2_DIS   (UINT32_C(0x3F) << 12)
 
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM2_N(n)   ((n) << 12)
 
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM3   (UINT32_C(0x3F) << 20)
 
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM3_DIS   (UINT32_C(0x3F) << 20)
 
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM3_N(n)   ((n) << 20)
 
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_PLLSRC   (UINT32_C(3) << 0)
 
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_PLLSRC_CSI   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_PLLSRC_HSE   (UINT32_C(2) << 0)
 
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_PLLSRC_HSI   (UINT32_C(0) << 0)
 
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_RSV10   (UINT32_C(3) << 10)
 
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_RSV18   (UINT32_C(3) << 18)
 
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_RSV2   (UINT32_C(3) << 2)
 
#define MCCI_STM32H7_REG_RCC_PLLCKSELR_RSV26   (UINT32_C(0x3F) << 26)
 
RCC_PLLCFGR bits
#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVP1EN   (UINT32_C(1) << 16)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVP2EN   (UINT32_C(1) << 19)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVP3EN   (UINT32_C(1) << 22)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVQ1EN   (UINT32_C(1) << 17)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVQ2EN   (UINT32_C(1) << 20)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVQ3EN   (UINT32_C(1) << 23)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVR1EN   (UINT32_C(1) << 18)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVR2EN   (UINT32_C(1) << 21)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVR3EN   (UINT32_C(1) << 24)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL1FRACEN   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL1RGE   (UINT32_C(3) << 2)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL1RGE_N(n)   ((n) << 2)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL1VCOSEL   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL2FRACEN   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL2RGE   (UINT32_C(3) << 6)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL2RGE_N(n)   ((n) << 6)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL2VCOSEL   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL3FRACEN   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL3RGE   (UINT32_C(3) << 10)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL3RGE_N(n)   ((n) << 10)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL3VCOSEL   (UINT32_C(1) << 9)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_RSV12   (UINT32_C(0xF) << 12)
 
#define MCCI_STM32H7_REG_RCC_PLLCFGR_RSV25   (UINT32_C(0x7F) << 25)
 
RCC_PLL1DIVR bits
#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVN   (UINT32_C(0x1FF) << 0)
 
#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVN_N(n)   ((n) << 0)
 
#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVP   (UINT32_C(0x7F) << 9)
 
#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVP_N(n)   ((n) << 9)
 
#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVQ   (UINT32_C(0x7F) << 16)
 
#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVQ_N(n)   ((n) << 16)
 
#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVR   (UINT32_C(0x7F) << 24)
 
#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVR_N(n)   ((n) << 24)
 
#define MCCI_STM32H7_REG_RCC_PLL1DIVR_RSV23   (UINT32_C(1) << 23)
 
#define MCCI_STM32H7_REG_RCC_PLL1DIVR_RSV31   (UINT32_C(1) << 31)
 
RCC_PLL1FRACR bits
#define MCCI_STM32H7_REG_RCC_PLL1FRACR_FRACN   (UINT32_C(0x1FFF) << 3)
 
#define MCCI_STM32H7_REG_RCC_PLL1FRACR_FRACN_N(n)   ((n) << 3)
 
#define MCCI_STM32H7_REG_RCC_PLL1FRACR_RSV0   (UINT32_C(7) << 0)
 
#define MCCI_STM32H7_REG_RCC_PLL1FRACR_RSV16   UINT32_C(0xFFFF0000)
 
RCC_PLL2DIVR bits
#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVN   (UINT32_C(0x1FF) << 0)
 
#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVN_N(n)   ((n) << 0)
 
#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVP   (UINT32_C(0x7F) << 9)
 
#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVP_N(n)   ((n) << 9)
 
#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVQ   (UINT32_C(0x7F) << 16)
 
#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVQ_N(n)   ((n) << 16)
 
#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVR   (UINT32_C(0x7F) << 24)
 
#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVR_N(n)   ((n) << 24)
 
#define MCCI_STM32H7_REG_RCC_PLL2DIVR_RSV23   (UINT32_C(1) << 23)
 
#define MCCI_STM32H7_REG_RCC_PLL2DIVR_RSV31   (UINT32_C(1) << 31)
 
RCC_PLL2FRACR bits
#define MCCI_STM32H7_REG_RCC_PLL2FRACR_FRACN   (UINT32_C(0x1FFF) << 3)
 
#define MCCI_STM32H7_REG_RCC_PLL2FRACR_FRACN_N(n)   ((n) << 3)
 
#define MCCI_STM32H7_REG_RCC_PLL2FRACR_RSV0   (UINT32_C(7) << 0)
 
#define MCCI_STM32H7_REG_RCC_PLL2FRACR_RSV16   UINT32_C(0xFFFF0000)
 
RCC_PLL3DIVR bits
#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVN   (UINT32_C(0x1FF) << 0)
 
#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVN_N(n)   ((n) << 0)
 
#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVP   (UINT32_C(0x7F) << 9)
 
#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVP_N(n)   ((n) << 9)
 
#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVQ   (UINT32_C(0x7F) << 16)
 
#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVQ_N(n)   ((n) << 16)
 
#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVR   (UINT32_C(0x7F) << 24)
 
#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVR_N(n)   ((n) << 24)
 
#define MCCI_STM32H7_REG_RCC_PLL3DIVR_RSV23   (UINT32_C(1) << 23)
 
#define MCCI_STM32H7_REG_RCC_PLL3DIVR_RSV31   (UINT32_C(1) << 31)
 
RCC_PLL3FRACR bits
#define MCCI_STM32H7_REG_RCC_PLL3FRACR_FRACN   (UINT32_C(0x1FFF) << 3)
 
#define MCCI_STM32H7_REG_RCC_PLL3FRACR_FRACN_N(n)   ((n) << 3)
 
#define MCCI_STM32H7_REG_RCC_PLL3FRACR_RSV0   (UINT32_C(7) << 0)
 
#define MCCI_STM32H7_REG_RCC_PLL3FRACR_RSV16   UINT32_C(0xFFFF0000)
 
RCC_CDCCIPR bits
#define MCCI_STM32H7_REG_RCC_CDCCIPR_CKPERSEL   (UINT32_C(3) << 28)
 
#define MCCI_STM32H7_REG_RCC_CDCCIPR_CKPERSEL_CSI   (UINT32_C(1) << 28)
 
#define MCCI_STM32H7_REG_RCC_CDCCIPR_CKPERSEL_HSE   (UINT32_C(2) << 28)
 
#define MCCI_STM32H7_REG_RCC_CDCCIPR_CKPERSEL_HSI   (UINT32_C(0) << 28)
 
#define MCCI_STM32H7_REG_RCC_CDCCIPR_FMCSEL   (UINT32_C(3) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCCIPR_FMCSEL_HCLK3   (UINT32_C(0) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCCIPR_FMCSEL_PER   (UINT32_C(3) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCCIPR_FMCSEL_PLL1   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCCIPR_FMCSEL_PLL2   (UINT32_C(2) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCCIPR_OCTOSPISEL   (UINT32_C(3) << 4)
 
#define MCCI_STM32H7_REG_RCC_CDCCIPR_OCTOSPISEL_HCLK3   (UINT32_C(0) << 4)
 
#define MCCI_STM32H7_REG_RCC_CDCCIPR_OCTOSPISEL_PER   (UINT32_C(3) << 4)
 
#define MCCI_STM32H7_REG_RCC_CDCCIPR_OCTOSPISEL_PLL1   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_CDCCIPR_OCTOSPISEL_PLL2   (UINT32_C(2) << 4)
 
#define MCCI_STM32H7_REG_RCC_CDCCIPR_RSV0   (UINT32_C(3) << 2)
 
#define MCCI_STM32H7_REG_RCC_CDCCIPR_RSV17   UINT32_C(0x0FFE0000)
 
#define MCCI_STM32H7_REG_RCC_CDCCIPR_RSV30   (UINT32_C(3) << 30)
 
#define MCCI_STM32H7_REG_RCC_CDCCIPR_RSV6   (UINT32_C(0x3F) << 6)
 
#define MCCI_STM32H7_REG_RCC_CDCCIPR_SDMMCSEL   (UINT32_C(1) << 16)
 
RCC_CDCCIP1R bits
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_DFSDM1SEL   (UINT32_C(1) << 24)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_FDCANSEL   (UINT32_C(3) << 28)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_FDCANSEL_HSE   (UINT32_C(0) << 28)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_FDCANSEL_PLL1   (UINT32_C(1) << 28)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_FDCANSEL_PLL2   (UINT32_C(2) << 28)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV15   (UINT32_C(1) << 15)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV19   (UINT32_C(1) << 19)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV22   (UINT32_C(3) << 22)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV25   (UINT32_C(7) << 25)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV3   (UINT32_C(7) << 3)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV30   (UINT32_C(1) << 30)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL   (UINT32_C(7) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL_I2S   (UINT32_C(3) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL_PER   (UINT32_C(4) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL_PLL1   (UINT32_C(0) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL_PLL2   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL_PLL3   (UINT32_C(2) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL   (UINT32_C(7) << 6)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_I2S   (UINT32_C(3) << 6)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_PER   (UINT32_C(4) << 6)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_PLL1   (UINT32_C(0) << 6)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_PLL2   (UINT32_C(1) << 6)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_PLL3   (UINT32_C(2) << 6)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_SPDIFRX   (UINT32_C(5) << 6)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL   (UINT32_C(7) << 9)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_I2S   (UINT32_C(3) << 9)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_PER   (UINT32_C(4) << 9)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_PLL1   (UINT32_C(0) << 9)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_PLL2   (UINT32_C(1) << 9)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_PLL3   (UINT32_C(2) << 9)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_SPDIFRX   (UINT32_C(5) << 9)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPDIFRXSEL   (UINT32_C(3) << 20)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPDIFRXSEL_HSI   (UINT32_C(3) << 20)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPDIFRXSEL_PLL1   (UINT32_C(0) << 20)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPDIFRXSEL_PLL2   (UINT32_C(1) << 20)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPDIFRXSEL_PLL3   (UINT32_C(2) << 20)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL   (UINT32_C(7) << 12)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL_I2S   (UINT32_C(3) << 12)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL_PER   (UINT32_C(4) << 12)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL_PLL1   (UINT32_C(0) << 12)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL_PLL2   (UINT32_C(1) << 12)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL_PLL3   (UINT32_C(2) << 12)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL   (UINT32_C(7) << 16)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_CSI   (UINT32_C(4) << 16)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_HSE   (UINT32_C(5) << 16)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_HSI   (UINT32_C(3) << 16)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_PCLK2   (UINT32_C(0) << 16)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_PLL2   (UINT32_C(1) << 16)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_PLL3   (UINT32_C(2) << 16)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SWPMISEL   (UINT32_C(1) << 31)
 
RCC_CDCCIP2R bits
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_CECSEL   (UINT32_C(3) << 22)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_CECSEL_CSI   (UINT32_C(2) << 22)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_CECSEL_LSE   (UINT32_C(0) << 22)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_CECSEL_LSI   (UINT32_C(1) << 22)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_I2C123SEL   (UINT32_C(7) << 12)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_I2C123SEL_CSI   (UINT32_C(3) << 12)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_I2C123SEL_HSI   (UINT32_C(2) << 12)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_I2C123SEL_PCLK1   (UINT32_C(0) << 12)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_I2C123SEL_PLL3   (UINT32_C(1) << 12)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL   (UINT32_C(7) << 28)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_LSE   (UINT32_C(3) << 28)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_LSI   (UINT32_C(4) << 28)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_PCLK1   (UINT32_C(0) << 28)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_PER   (UINT32_C(5) << 28)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_PLL2   (UINT32_C(1) << 28)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_PLL3   (UINT32_C(2) << 28)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RNGSEL   (UINT32_C(3) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RNGSEL_HSI48   (UINT32_C(0) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RNGSEL_LSE   (UINT32_C(2) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RNGSEL_LSI   (UINT32_C(3) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RNGSEL_PLL1   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RSV10   (UINT32_C(3) << 10)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RSV14   (UINT32_C(0x3F) << 14)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RSV24   (UINT32_C(0xF) << 24)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RSV31   (UINT32_C(1) << 31)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RSV6   (UINT32_C(3) << 6)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL   (UINT32_C(7) << 3)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_CSI   (UINT32_C(4) << 3)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_HSI   (UINT32_C(3) << 3)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_LSE   (UINT32_C(5) << 3)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_PCLK2   (UINT32_C(0) << 3)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_PLL2   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_PLL3   (UINT32_C(2) << 3)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL   (UINT32_C(7) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_CSI   (UINT32_C(4) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_HSI   (UINT32_C(3) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_LSE   (UINT32_C(5) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_PCLK1   (UINT32_C(0) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_PLL2   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_PLL3   (UINT32_C(2) << 0)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USBSEL   (UINT32_C(3) << 20)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USBSEL_DIS   (UINT32_C(0) << 20)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USBSEL_HSI48   (UINT32_C(3) << 20)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USBSEL_PLL1   (UINT32_C(1) << 20)
 
#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USBSEL_PLL3   (UINT32_C(2) << 20)
 
RCC_SRDCCIPR bits
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_ADCSEL   (UINT32_C(3) << 16)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_ADCSEL_PER   (UINT32_C(2) << 16)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_ADCSEL_PLL2   (UINT32_C(0) << 16)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_ADCSEL_PLL3   (UINT32_C(1) << 16)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_DFSDM2SEL   (UINT32_C(1) << 27)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_I2C4SEL   (UINT32_C(3) << 8)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_I2C4SEL_CSI   (UINT32_C(3) << 8)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_I2C4SEL_HSI   (UINT32_C(2) << 8)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_I2C4SEL_PCLK4   (UINT32_C(0) << 8)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_I2C4SEL_PLL3   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL   (UINT32_C(7) << 10)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_LSE   (UINT32_C(3) << 10)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_LSI   (UINT32_C(4) << 10)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_PCLK4   (UINT32_C(0) << 10)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_PER   (UINT32_C(5) << 10)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_PLL2   (UINT32_C(1) << 10)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_PLL3   (UINT32_C(2) << 10)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL   (UINT32_C(7) << 13)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_LSE   (UINT32_C(3) << 13)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_LSI   (UINT32_C(4) << 13)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_PCLK4   (UINT32_C(0) << 13)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_PER   (UINT32_C(5) << 13)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_PLL2   (UINT32_C(1) << 13)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_PLL3   (UINT32_C(2) << 13)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL   (UINT32_C(7) << 0)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_CSI   (UINT32_C(4) << 0)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_HSI   (UINT32_C(3) << 0)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_LSE   (UINT32_C(5) << 0)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_PCLK4   (UINT32_C(0) << 0)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_PLL2   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_PLL3   (UINT32_C(2) << 0)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_RSV18   (UINT32_C(0x1FF) << 18)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_RSV3   (UINT32_C(0x1F) << 3)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_RSV31   (UINT32_C(1) << 31)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL   (UINT32_C(7) << 28)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_CSI   (UINT32_C(4) << 28)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_HSE   (UINT32_C(5) << 28)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_HSI   (UINT32_C(3) << 28)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_I2S   (UINT32_C(6) << 28)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_PCLK4   (UINT32_C(0) << 28)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_PLL2   (UINT32_C(1) << 28)
 
#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_PLL3   (UINT32_C(2) << 28)
 
RCC_CIER bits
#define MCCI_STM32H7_REG_RCC_CIER_CSIRDYIE   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_CIER_HSERDYIE   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_CIER_HSI48RDYIE   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_CIER_HSIRDYIE   (UINT32_C(1) << 2)
 
#define MCCI_STM32H7_REG_RCC_CIER_LSECSSIE   (UINT32_C(1) << 9)
 
#define MCCI_STM32H7_REG_RCC_CIER_LSERDYIE   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_CIER_LSIRDYIE   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_CIER_PLL1RDYIE   (UINT32_C(1) << 6)
 
#define MCCI_STM32H7_REG_RCC_CIER_PLL2RDYIE   (UINT32_C(1) << 7)
 
#define MCCI_STM32H7_REG_RCC_CIER_PLL3RDYIE   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_CIER_RSV10   UINT32_C(0xFFFFFC00)
 
RCC_CIFR bits
#define MCCI_STM32H7_REG_RCC_CIFR_CSIRDYF   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_CIFR_HSECSSF   (UINT32_C(1) << 10)
 
#define MCCI_STM32H7_REG_RCC_CIFR_HSERDYF   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_CIFR_HSI48RDYF   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_CIFR_HSIRDYF   (UINT32_C(1) << 2)
 
#define MCCI_STM32H7_REG_RCC_CIFR_LSECSSF   (UINT32_C(1) << 9)
 
#define MCCI_STM32H7_REG_RCC_CIFR_LSERDYF   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_CIFR_LSIRDYF   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_CIFR_PLL1RDYF   (UINT32_C(1) << 6)
 
#define MCCI_STM32H7_REG_RCC_CIFR_PLL2RDYF   (UINT32_C(1) << 7)
 
#define MCCI_STM32H7_REG_RCC_CIFR_PLL3RDYF   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_CIFR_RSV11   UINT32_C(0xFFFFF800)
 
RCC_CICR bits
#define MCCI_STM32H7_REG_RCC_CICR_CSIRDYC   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_CICR_HSECSSC   (UINT32_C(1) << 10)
 
#define MCCI_STM32H7_REG_RCC_CICR_HSERDYC   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_CICR_HSI48RDYC   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_CICR_HSIRDYC   (UINT32_C(1) << 2)
 
#define MCCI_STM32H7_REG_RCC_CICR_LSECSSC   (UINT32_C(1) << 9)
 
#define MCCI_STM32H7_REG_RCC_CICR_LSERDYC   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_CICR_LSIRDYC   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_CICR_PLL1RDYC   (UINT32_C(1) << 6)
 
#define MCCI_STM32H7_REG_RCC_CICR_PLL2RDYC   (UINT32_C(1) << 7)
 
#define MCCI_STM32H7_REG_RCC_CICR_PLL3RDYC   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_CICR_RSV11   UINT32_C(0xFFFFF800)
 
RCC_BDCR bits
#define MCCI_STM32H7_REG_RCC_BDCR_LSEBYP   (UINT32_C(1) << 2)
 
#define MCCI_STM32H7_REG_RCC_BDCR_LSECSSD   (UINT32_C(1) << 6)
 
#define MCCI_STM32H7_REG_RCC_BDCR_LSECSSON   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_BDCR_LSEDRV   (UINT32_C(3) << 3)
 
#define MCCI_STM32H7_REG_RCC_BDCR_LSEDRV_HIEST   (UINT32_C(3) << 3)
 
#define MCCI_STM32H7_REG_RCC_BDCR_LSEDRV_LOWEST   (UINT32_C(0) << 3)
 
#define MCCI_STM32H7_REG_RCC_BDCR_LSEDRV_MEDHI   (UINT32_C(2) << 3)
 
#define MCCI_STM32H7_REG_RCC_BDCR_LSEDRV_MEDLOW   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_BDCR_LSEEXT   (UINT32_C(1) << 7)
 
#define MCCI_STM32H7_REG_RCC_BDCR_LSEON   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_BDCR_LSERDY   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_BDCR_RSV10   (UINT32_C(0x1F) << 10)
 
#define MCCI_STM32H7_REG_RCC_BDCR_RSV17   UINT32_C(0xFFFE0000)
 
#define MCCI_STM32H7_REG_RCC_BDCR_RTCEN   (UINT32_C(1) << 15)
 
#define MCCI_STM32H7_REG_RCC_BDCR_RTCSEL   (UINT32_C(3) << 8)
 
#define MCCI_STM32H7_REG_RCC_BDCR_RTCSEL_HSE   (UINT32_C(3) << 8)
 
#define MCCI_STM32H7_REG_RCC_BDCR_RTCSEL_LSE   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_BDCR_RTCSEL_LSI   (UINT32_C(2) << 8)
 
#define MCCI_STM32H7_REG_RCC_BDCR_RTCSEL_NO   (UINT32_C(0) << 8)
 
#define MCCI_STM32H7_REG_RCC_BDCR_VSWRST   (UINT32_C(1) << 16)
 
RCC_CSR bits
#define MCCI_STM32H7_REG_RCC_CSR_LSION   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_CSR_LSIRDY   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_CSR_RSV2   UINT32_C(0xFFFFFFFC)
 
RCC_AHB3RSTR bits
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_DMA2DRST   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_FMCRST   (UINT32_C(1) << 12)
 
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_GFXMMURST   (UINT32_C(1) << 24)
 
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_JPGDECRST   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_MDMARST   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_OCTOSPI1RST   (UINT32_C(1) << 14)
 
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_OCTOSPI2RST   (UINT32_C(1) << 19)
 
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_OCTOSPIMRST   (UINT32_C(1) << 21)
 
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_OTFD1RST   (UINT32_C(1) << 22)
 
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_OTFD2RST   (UINT32_C(1) << 23)
 
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV1   (UINT32_C(7) << 1)
 
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV13   (UINT32_C(1) << 13)
 
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV15   (UINT32_C(1) << 15)
 
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV17   (UINT32_C(3) << 17)
 
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV20   (UINT32_C(1) << 20)
 
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV25   (UINT32_C(0x7F) << 25)
 
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV6   (UINT32_C(0x3F) << 6)
 
#define MCCI_STM32H7_REG_RCC_AHB3RSTR_SDMMC1RST   (UINT32_C(1) << 16)
 
RCC_AHB1RSTR bits
#define MCCI_STM32H7_REG_RCC_AHB1RSTR_ADC12RST   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_AHB1RSTR_CRCRST   (UINT32_C(1) << 9)
 
#define MCCI_STM32H7_REG_RCC_AHB1RSTR_DMA1RST   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_AHB1RSTR_DMA2RST   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_AHB1RSTR_RSV10   (UINT32_C(0x7FFF) << 10)
 
#define MCCI_STM32H7_REG_RCC_AHB1RSTR_RSV2   (UINT32_C(7) << 2)
 
#define MCCI_STM32H7_REG_RCC_AHB1RSTR_RSV26   (UINT32_C(0x3F) << 26)
 
#define MCCI_STM32H7_REG_RCC_AHB1RSTR_RSV6   (UINT32_C(7) << 6)
 
#define MCCI_STM32H7_REG_RCC_AHB1RSTR_USB1OTGRST   (UINT32_C(1) << 25)
 
RCC_AHB2RSTR bits
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_BDMA1RST   (UINT32_C(1) << 11)
 
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_CRYPTRST   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_DCMIRST   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_HASHRST   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_HSEMRST   (UINT32_C(1) << 2)
 
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_PSSIRST   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_RNGRST   (UINT32_C(1) << 6)
 
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_RSV1   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_RSV10   (UINT32_C(1) << 10)
 
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_RSV12   UINT32_C(0xFFFFF000)
 
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_RSV3   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_RSV7   (UINT32_C(3) << 7)
 
#define MCCI_STM32H7_REG_RCC_AHB2RSTR_SDMMC2RST   (UINT32_C(1) << 9)
 
RCC_AHB4RSTR bits
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_BDMA2RST   (UINT32_C(1) << 21)
 
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOARST   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOBRST   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOCRST   (UINT32_C(1) << 2)
 
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIODRST   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOERST   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOFRST   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOGRST   (UINT32_C(1) << 6)
 
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOHRST   (UINT32_C(1) << 7)
 
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOIRST   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOJRST   (UINT32_C(1) << 9)
 
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOKRST   (UINT32_C(1) << 10)
 
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_RSV11   (UINT32_C(0x3FF) << 11)
 
#define MCCI_STM32H7_REG_RCC_AHB4RSTR_RSV22   UINT32_C(0xFFC00000)
 
RCC_APB3RSTR bits
#define MCCI_STM32H7_REG_RCC_APB3RSTR_LTDCRST   (UINT32_C(1) << 3)
 LTDCRST block reset.
 
#define MCCI_STM32H7_REG_RCC_APB3RSTR_RSV0   (UINT32_C(7) << 0)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB3RSTR_RSV4   UINT32_C(0xFFFFFFF0)
 reserved, don't change
 
RCC_APB1LRSTR bits
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_CECRST   (UINT32_C(1) << 27)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_DAC1RST   (UINT32_C(1) << 29)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_I2C1RST   (UINT32_C(1) << 21)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_I2C2RST   (UINT32_C(1) << 22)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_I2C3RST   (UINT32_C(1) << 23)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_LPTIM1RST   (UINT32_C(1) << 9)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_RSV10   (UINT32_C(0xF) << 10)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_RSV24   (UINT32_C(7) << 24)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_RSV28   (UINT32_C(1) << 28)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_SPDIFRXRST   (UINT32_C(1) << 16)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_SPI2RST   (UINT32_C(1) << 14)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_SPI3RST   (UINT32_C(1) << 15)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM12RST   (UINT32_C(1) << 6)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM13RST   (UINT32_C(1) << 7)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM14RST   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM2RST   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM3RST   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM4RST   (UINT32_C(1) << 2)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM5RST   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM6RST   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM7RST   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_UART7RST   (UINT32_C(1) << 30)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_UART8RST   (UINT32_C(1) << 31)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_USART2RST   (UINT32_C(1) << 17)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_USART3RST   (UINT32_C(1) << 18)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_USART4RST   (UINT32_C(1) << 19)
 
#define MCCI_STM32H7_REG_RCC_APB1LRSTR_USART5RST   (UINT32_C(1) << 20)
 
RCC_APB1HRSTR bits
#define MCCI_STM32H7_REG_RCC_APB1HRSTR_CRSRST   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_APB1HRSTR_FDCANRST   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_APB1HRSTR_MDIOSRST   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_APB1HRSTR_OPAMPRST   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_APB1HRSTR_RSV0   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_APB1HRSTR_RSV3   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_APB1HRSTR_RSV6   (UINT32_C(3) << 6)
 
#define MCCI_STM32H7_REG_RCC_APB1HRSTR_RSV9   UINT32_C(0xFFFFFE00)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB1HRSTR_SWPMIRST   (UINT32_C(1) << 2)
 
RCC_APB2RSTR bits
#define MCCI_STM32H7_REG_RCC_APB2RSTR_DFSDM1RST   (UINT32_C(1) << 30)
 DFSDM1 reset.
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV14   (UINT32_C(3) << 14)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV19   (UINT32_C(1) << 19)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV2   (UINT32_C(3) << 2)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV21   (UINT32_C(1) << 21)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV24   (UINT32_C(0x3F) << 24)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV31   (UINT32_C(1) << 31)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV8   (UINT32_C(0xF) << 8)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_SAI1RST   (UINT32_C(1) << 22)
 SAI1 reset.
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_SAI2RST   (UINT32_C(1) << 23)
 SAI2 reset.
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_SPI1RST   (UINT32_C(1) << 12)
 SPI1 reset.
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_SPI4RST   (UINT32_C(1) << 13)
 SPI4 reset.
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_SPI5RST   (UINT32_C(1) << 20)
 SPI5 reset.
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_TIM15RST   (UINT32_C(1) << 16)
 TIM15 reset.
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_TIM16RST   (UINT32_C(1) << 17)
 TIM16 reset.
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_TIM17RST   (UINT32_C(1) << 18)
 TIM17 reset.
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_TIM1RST   (UINT32_C(1) << 0)
 TIM1 reset.
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_TIM8RST   (UINT32_C(1) << 1)
 TIM8 reset.
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_UART9RST   (UINT32_C(1) << 6)
 UART9 reset.
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_USART10RST   (UINT32_C(1) << 7)
 USART10 reset.
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_USART1RST   (UINT32_C(1) << 4)
 USART1 reset.
 
#define MCCI_STM32H7_REG_RCC_APB2RSTR_USART6RST   (UINT32_C(1) << 5)
 USART6 reset.
 
RCC_APB4RSTR bits
#define MCCI_STM32H7_REG_RCC_APB4RSTR_COMP12RST   (UINT32_C(1) << 14)
 
#define MCCI_STM32H7_REG_RCC_APB4RSTR_DAC2RST   (UINT32_C(1) << 13)
 
#define MCCI_STM32H7_REG_RCC_APB4RSTR_DFSDM2RST   (UINT32_C(1) << 27)
 
#define MCCI_STM32H7_REG_RCC_APB4RSTR_DTSRST   (UINT32_C(1) << 26)
 
#define MCCI_STM32H7_REG_RCC_APB4RSTR_I2C4RST   (UINT32_C(1) << 7)
 
#define MCCI_STM32H7_REG_RCC_APB4RSTR_LPTIM2RST   (UINT32_C(1) << 9)
 
#define MCCI_STM32H7_REG_RCC_APB4RSTR_LPTIM3RST   (UINT32_C(1) << 10)
 
#define MCCI_STM32H7_REG_RCC_APB4RSTR_LPUART1RST   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV0   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV11   (UINT32_C(3) << 11)
 
#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV16   (UINT32_C(0x3FF) << 16)
 
#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV2   (UINT32_C(1) << 2)
 
#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV28   (UINT32_C(0xF) << 28)
 
#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV4   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV6   (UINT32_C(1) << 6)
 
#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV8   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_APB4RSTR_SPI6RST   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_APB4RSTR_SYSCFGRST   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_APB4RSTR_VREFRST   (UINT32_C(1) << 15)
 
RCC_SRDAMR bits
#define MCCI_STM32H7_REG_RCC_SRDAMR_BDMA2AMEN   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_BKPRAMAMEN   (UINT32_C(1) << 28)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_COMP12AMEN   (UINT32_C(1) << 14)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_DAC2AMEN   (UINT32_C(1) << 13)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_DFSDM2AMEN   (UINT32_C(1) << 27)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_DTSAMEN   (UINT32_C(1) << 26)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_GPIOAMEN   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_I2C4AMEN   (UINT32_C(1) << 7)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_LPTIM2AMEN   (UINT32_C(1) << 9)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_LPTIM3AMEN   (UINT32_C(1) << 10)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_LPUART1AMEN   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV11   (UINT32_C(3) << 11)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV17   (UINT32_C(0x1FF) << 17)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV2   (UINT32_C(1) << 2)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV25   (UINT32_C(3) << 30)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV4   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV6   (UINT32_C(1) << 6)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV8   (UINT32_C(7) << 8)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_RTCAMEN   (UINT32_C(1) << 16)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_SPI6AMEN   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_SRDSRAMAMEN   (UINT32_C(1) << 29)
 
#define MCCI_STM32H7_REG_RCC_SRDAMR_VREFAMEN   (UINT32_C(1) << 15)
 
RCC_CKGAENR bits
#define MCCI_STM32H7_REG_RCC_CKGAENR_AHB12CKG   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_AHB34CKG   (UINT32_C(1) << 9)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_AHBCKG   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_AXICKG   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_AXIRAM1CKG   (UINT32_C(1) << 14)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_AXIRAM2CKG   (UINT32_C(1) << 15)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_AXIRAM3CKG   (UINT32_C(1) << 16)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_CPUCKG   (UINT32_C(1) << 2)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_DMA2DCKG   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_ECCRAMCKG   (UINT32_C(1) << 29)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_EXTICKG   (UINT32_C(1) << 30)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_FLIFTCKG   (UINT32_C(1) << 10)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_FMCCKG   (UINT32_C(1) << 12)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_GFXMMUMCKG   (UINT32_C(1) << 7)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_GFXMMUSCKG   (UINT32_C(1) << 17)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_JTAGCKG   (UINT32_C(1) << 31)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_LTDCCKG   (UINT32_C(1) << 6)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_MDMACKG   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_OCTOSPI1CKG   (UINT32_C(1) << 13)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_OCTOSPI2CKG   (UINT32_C(1) << 11)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_RSV18   UINT32_C(0x1FFC0000)
 
#define MCCI_STM32H7_REG_RCC_CKGAENR_SDMMCCKG   (UINT32_C(1) << 3)
 
RCC_RSR bits
#define MCCI_STM32H7_REG_RCC_RSR_BORRSTF   (UINT32_C(1) << 21)
 
#define MCCI_STM32H7_REG_RCC_RSR_CDRSTF   (UINT32_C(1) << 19)
 
#define MCCI_STM32H7_REG_RCC_RSR_IWDGRSTF   (UINT32_C(1) << 26)
 
#define MCCI_STM32H7_REG_RCC_RSR_LPWRRSTF   (UINT32_C(1) << 30)
 
#define MCCI_STM32H7_REG_RCC_RSR_PINRSTF   (UINT32_C(1) << 22)
 
#define MCCI_STM32H7_REG_RCC_RSR_PORRSTF   (UINT32_C(1) << 23)
 
#define MCCI_STM32H7_REG_RCC_RSR_RMVF   (UINT32_C(1) << 16)
 
#define MCCI_STM32H7_REG_RCC_RSR_RSV0   UINT32_C(0x0000FFFF)
 
#define MCCI_STM32H7_REG_RCC_RSR_RSV18   (UINT32_C(3) << 18)
 
#define MCCI_STM32H7_REG_RCC_RSR_RSV20   (UINT32_C(1) << 20)
 
#define MCCI_STM32H7_REG_RCC_RSR_RSV25   (UINT32_C(1) << 25)
 
#define MCCI_STM32H7_REG_RCC_RSR_RSV27   (UINT32_C(1) << 27)
 
#define MCCI_STM32H7_REG_RCC_RSR_RSV29   (UINT32_C(1) << 29)
 
#define MCCI_STM32H7_REG_RCC_RSR_RSV31   (UINT32_C(1) << 31)
 
#define MCCI_STM32H7_REG_RCC_RSR_SFTRSTF   (UINT32_C(1) << 24)
 
#define MCCI_STM32H7_REG_RCC_RSR_WWDGRSTF   (UINT32_C(1) << 28)
 
RCC_AHB3ENR bits
#define MCCI_STM32H7_REG_RCC_AHB3ENR_DMA2DEN   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_AHB3ENR_FMCEN   (UINT32_C(1) << 12)
 
#define MCCI_STM32H7_REG_RCC_AHB3ENR_GFXMMUEN   (UINT32_C(1) << 24)
 
#define MCCI_STM32H7_REG_RCC_AHB3ENR_JPGDECEN   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_AHB3ENR_MDMAEN   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_AHB3ENR_OCTOSPI1EN   (UINT32_C(1) << 14)
 
#define MCCI_STM32H7_REG_RCC_AHB3ENR_OCTOSPI2EN   (UINT32_C(1) << 19)
 
#define MCCI_STM32H7_REG_RCC_AHB3ENR_OCTOSPIMEN   (UINT32_C(1) << 21)
 
#define MCCI_STM32H7_REG_RCC_AHB3ENR_OTFD1EN   (UINT32_C(1) << 22)
 
#define MCCI_STM32H7_REG_RCC_AHB3ENR_OTFD2EN   (UINT32_C(1) << 23)
 
#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV1   (UINT32_C(7) << 1)
 
#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV13   (UINT32_C(1) << 13)
 
#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV15   (UINT32_C(1) << 15)
 
#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV17   (UINT32_C(3) << 17)
 
#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV20   (UINT32_C(1) << 20)
 
#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV25   (UINT32_C(0x7F) << 25)
 
#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV6   (UINT32_C(0x3F) << 6)
 
#define MCCI_STM32H7_REG_RCC_AHB3ENR_SDMMC1EN   (UINT32_C(1) << 16)
 
RCC_AHB1ENR bits
#define MCCI_STM32H7_REG_RCC_AHB1ENR_ADC12EN   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_AHB1ENR_CRCEN   (UINT32_C(1) << 9)
 
#define MCCI_STM32H7_REG_RCC_AHB1ENR_DMA1EN   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_AHB1ENR_DMA2EN   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_AHB1ENR_RSV10   (UINT32_C(0x7FFF) << 10)
 
#define MCCI_STM32H7_REG_RCC_AHB1ENR_RSV2   (UINT32_C(7) << 2)
 
#define MCCI_STM32H7_REG_RCC_AHB1ENR_RSV27   (UINT32_C(0x1F) << 27)
 
#define MCCI_STM32H7_REG_RCC_AHB1ENR_RSV6   (UINT32_C(7) << 6)
 
#define MCCI_STM32H7_REG_RCC_AHB1ENR_USB1OTGEN   (UINT32_C(1) << 25)
 
#define MCCI_STM32H7_REG_RCC_AHB1ENR_USB1ULPIEN   (UINT32_C(1) << 26)
 
RCC_AHB2ENR bits
#define MCCI_STM32H7_REG_RCC_AHB2ENR_AHBSRAM1EN   (UINT32_C(1) << 29)
 
#define MCCI_STM32H7_REG_RCC_AHB2ENR_AHBSRAM2EN   (UINT32_C(1) << 30)
 
#define MCCI_STM32H7_REG_RCC_AHB2ENR_BDMA1EN   (UINT32_C(1) << 11)
 
#define MCCI_STM32H7_REG_RCC_AHB2ENR_CRYPTEN   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_AHB2ENR_DCMIEN   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_AHB2ENR_HASHEN   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_AHB2ENR_HSEMEN   (UINT32_C(1) << 2)
 
#define MCCI_STM32H7_REG_RCC_AHB2ENR_PSSIEN   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_AHB2ENR_RNGEN   (UINT32_C(1) << 6)
 
#define MCCI_STM32H7_REG_RCC_AHB2ENR_RSV1   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_AHB2ENR_RSV10   (UINT32_C(1) << 10)
 
#define MCCI_STM32H7_REG_RCC_AHB2ENR_RSV12   (UINT32_C(0x1FFFF) << 12)
 
#define MCCI_STM32H7_REG_RCC_AHB2ENR_RSV3   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_AHB2ENR_RSV31   (UINT32_C(1) << 31)
 
#define MCCI_STM32H7_REG_RCC_AHB2ENR_RSV7   (UINT32_C(3) << 7)
 
#define MCCI_STM32H7_REG_RCC_AHB2ENR_SDMMC2EN   (UINT32_C(1) << 9)
 
RCC_AHB4ENR bits
#define MCCI_STM32H7_REG_RCC_AHB4ENR_BDMA2EN   (UINT32_C(1) << 21)
 
#define MCCI_STM32H7_REG_RCC_AHB4ENR_BKPRAMEN   (UINT32_C(1) << 28)
 
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOAEN   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOBEN   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOCEN   (UINT32_C(1) << 2)
 
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIODEN   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOEEN   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOFEN   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOGEN   (UINT32_C(1) << 6)
 
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOHEN   (UINT32_C(1) << 7)
 
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOIEN   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOJEN   (UINT32_C(1) << 9)
 
#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOKEN   (UINT32_C(1) << 10)
 
#define MCCI_STM32H7_REG_RCC_AHB4ENR_RSV11   (UINT32_C(0x3FF) << 11)
 
#define MCCI_STM32H7_REG_RCC_AHB4ENR_RSV22   (UINT32_C(0x3F) << 22)
 
#define MCCI_STM32H7_REG_RCC_AHB4ENR_RSV30   (UINT32_C(3) << 30)
 
#define MCCI_STM32H7_REG_RCC_AHB4ENR_SRDSRAMEN   (UINT32_C(1) << 29)
 
RCC_APB3ENR bits
#define MCCI_STM32H7_REG_RCC_APB3ENR_LTDCEN   (UINT32_C(1) << 25)
 
#define MCCI_STM32H7_REG_RCC_APB3ENR_RSV0   (UINT32_C(7) << 0)
 
#define MCCI_STM32H7_REG_RCC_APB3ENR_RSV4   (UINT32_C(3) << 4)
 
#define MCCI_STM32H7_REG_RCC_APB3ENR_RSV7   UINT32_C(0xFFFFFF80)
 
#define MCCI_STM32H7_REG_RCC_APB3ENR_WWDGEN   (UINT32_C(1) << 26)
 
RCC_APB1LENR bits
#define MCCI_STM32H7_REG_RCC_APB1LENR_CECEN   (UINT32_C(1) << 27)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_DAC1EN   (UINT32_C(1) << 29)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_I2C1EN   (UINT32_C(1) << 21)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_I2C2EN   (UINT32_C(1) << 22)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_I2C3EN   (UINT32_C(1) << 23)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_LPTIM1EN   (UINT32_C(1) << 9)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_RSV10   (UINT32_C(0xF) << 10)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_RSV24   (UINT32_C(7) << 24)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_RSV28   (UINT32_C(1) << 28)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_SPDIFRXEN   (UINT32_C(1) << 16)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_SPI2EN   (UINT32_C(1) << 14)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_SPI3EN   (UINT32_C(1) << 15)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM12EN   (UINT32_C(1) << 6)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM13EN   (UINT32_C(1) << 7)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM14EN   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM2EN   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM3EN   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM4EN   (UINT32_C(1) << 2)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM5EN   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM6EN   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM7EN   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_UART7EN   (UINT32_C(1) << 30)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_UART8EN   (UINT32_C(1) << 31)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_USART2EN   (UINT32_C(1) << 17)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_USART3EN   (UINT32_C(1) << 18)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_USART4EN   (UINT32_C(1) << 19)
 
#define MCCI_STM32H7_REG_RCC_APB1LENR_USART5EN   (UINT32_C(1) << 20)
 
RCC_APB1HENR bits
#define MCCI_STM32H7_REG_RCC_APB1HENR_CRSEN   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_APB1HENR_FDCANEN   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_APB1HENR_MDIOSEN   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_APB1HENR_OPAMPEN   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_APB1HENR_RSV0   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_APB1HENR_RSV3   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_APB1HENR_RSV6   (UINT32_C(3) << 6)
 
#define MCCI_STM32H7_REG_RCC_APB1HENR_RSV9   UINT32_C(0xFFFFFE00)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB1HENR_SWPMIEN   (UINT32_C(1) << 2)
 
RCC_APB2ENR bits
#define MCCI_STM32H7_REG_RCC_APB2ENR_DFSDM1EN   (UINT32_C(1) << 30)
 DFSDM1 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV14   (UINT32_C(3) << 14)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV19   (UINT32_C(1) << 19)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV2   (UINT32_C(3) << 2)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV21   (UINT32_C(1) << 21)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV24   (UINT32_C(0x3F) << 24)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV31   (UINT32_C(1) << 31)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV8   (UINT32_C(0xF) << 8)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_SAI1EN   (UINT32_C(1) << 22)
 SAI1 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_SAI2EN   (UINT32_C(1) << 23)
 SAI2 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_SPI1EN   (UINT32_C(1) << 12)
 SPI1 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_SPI4EN   (UINT32_C(1) << 13)
 SPI4 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_SPI5EN   (UINT32_C(1) << 20)
 SPI5 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_TIM15EN   (UINT32_C(1) << 16)
 TIM15 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_TIM16EN   (UINT32_C(1) << 17)
 TIM16 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_TIM17EN   (UINT32_C(1) << 18)
 TIM17 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_TIM1EN   (UINT32_C(1) << 0)
 TIM1 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_TIM8EN   (UINT32_C(1) << 1)
 TIM8 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_UART9EN   (UINT32_C(1) << 6)
 UART9 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_USART10EN   (UINT32_C(1) << 7)
 USART10 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_USART1EN   (UINT32_C(1) << 4)
 USART1 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2ENR_USART6EN   (UINT32_C(1) << 5)
 USART6 clock enable.
 
RCC_APB4ENR bits
#define MCCI_STM32H7_REG_RCC_APB4ENR_COMP12EN   (UINT32_C(1) << 14)
 
#define MCCI_STM32H7_REG_RCC_APB4ENR_DAC2EN   (UINT32_C(1) << 13)
 
#define MCCI_STM32H7_REG_RCC_APB4ENR_DFSDM2EN   (UINT32_C(1) << 27)
 
#define MCCI_STM32H7_REG_RCC_APB4ENR_DTSEN   (UINT32_C(1) << 26)
 
#define MCCI_STM32H7_REG_RCC_APB4ENR_I2C4EN   (UINT32_C(1) << 7)
 
#define MCCI_STM32H7_REG_RCC_APB4ENR_LPTIM2EN   (UINT32_C(1) << 9)
 
#define MCCI_STM32H7_REG_RCC_APB4ENR_LPTIM3EN   (UINT32_C(1) << 10)
 
#define MCCI_STM32H7_REG_RCC_APB4ENR_LPUART1EN   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV0   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV11   (UINT32_C(3) << 11)
 
#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV17   (UINT32_C(0x1FF) << 17)
 
#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV2   (UINT32_C(1) << 2)
 
#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV28   (UINT32_C(0xF) << 28)
 
#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV4   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV6   (UINT32_C(1) << 6)
 
#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV8   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_APB4ENR_RTCAPBEN   (UINT32_C(1) << 16)
 
#define MCCI_STM32H7_REG_RCC_APB4ENR_SPI6EN   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_APB4ENR_SYSCFGEN   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_APB4ENR_VREFEN   (UINT32_C(1) << 15)
 
RCC_AHB3LPENR bits
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_AXISRAM1LPEN   (UINT32_C(1) << 31)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_AXISRAM2LPEN   (UINT32_C(1) << 26)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_AXISRAM3LPEN   (UINT32_C(1) << 27)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_DMA2DLPEN   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_DTCM1LPEN   (UINT32_C(1) << 28)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_DTCM2LPEN   (UINT32_C(1) << 29)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_FLITFLPEN   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_FMCLPEN   (UINT32_C(1) << 12)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_GFXMMULPEN   (UINT32_C(1) << 24)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_ITCMLPEN   (UINT32_C(1) << 30)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_JPGDECLPEN   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_MDMALPEN   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_OCTOSPI1LPEN   (UINT32_C(1) << 14)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_OCTOSPI2LPEN   (UINT32_C(1) << 19)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_OCTOSPIMLPEN   (UINT32_C(1) << 21)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_OTFD1LPEN   (UINT32_C(1) << 22)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_OTFD2LPEN   (UINT32_C(1) << 23)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV1   (UINT32_C(7) << 1)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV13   (UINT32_C(1) << 13)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV15   (UINT32_C(1) << 15)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV17   (UINT32_C(3) << 17)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV20   (UINT32_C(1) << 20)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV25   (UINT32_C(1) << 25)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV6   (UINT32_C(3) << 6)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV9   (UINT32_C(7) << 9)
 
#define MCCI_STM32H7_REG_RCC_AHB3LPENR_SDMMC1LPEN   (UINT32_C(1) << 16)
 
RCC_AHB1LPENR bits
#define MCCI_STM32H7_REG_RCC_AHB1LPENR_ADC12LPEN   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_AHB1LPENR_CRCLPEN   (UINT32_C(1) << 9)
 
#define MCCI_STM32H7_REG_RCC_AHB1LPENR_DMA1LPEN   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_AHB1LPENR_DMA2LPEN   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_AHB1LPENR_RSV10   (UINT32_C(0x7FFF) << 10)
 
#define MCCI_STM32H7_REG_RCC_AHB1LPENR_RSV2   (UINT32_C(7) << 2)
 
#define MCCI_STM32H7_REG_RCC_AHB1LPENR_RSV27   (UINT32_C(0x1F) << 27)
 
#define MCCI_STM32H7_REG_RCC_AHB1LPENR_RSV6   (UINT32_C(7) << 6)
 
#define MCCI_STM32H7_REG_RCC_AHB1LPENR_USB1OTGLPEN   (UINT32_C(1) << 25)
 
#define MCCI_STM32H7_REG_RCC_AHB1LPENR_USB1ULPILPEN   (UINT32_C(1) << 26)
 
RCC_AHB2LPENR bits
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_AHBSRAM1LPEN   (UINT32_C(1) << 29)
 
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_AHBSRAM2LPEN   (UINT32_C(1) << 30)
 
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_CRYPTLPEN   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_DCMILPEN   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_DFSDMDMALPEN   (UINT32_C(1) << 11)
 
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_HASHLPEN   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_PSSILPEN   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_RNGLPEN   (UINT32_C(1) << 6)
 
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_RSV1   (UINT32_C(7) << 1)
 
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_RSV10   (UINT32_C(1) << 10)
 
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_RSV12   (UINT32_C(0x1FFFF) << 12)
 
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_RSV31   (UINT32_C(1) << 31)
 
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_RSV7   (UINT32_C(3) << 7)
 
#define MCCI_STM32H7_REG_RCC_AHB2LPENR_SDMMC2LPEN   (UINT32_C(1) << 9)
 
RCC_AHB4LPENR bits
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_BDMA2LPEN   (UINT32_C(1) << 21)
 
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_BKPRAMLPEN   (UINT32_C(1) << 28)
 
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOALPEN   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOBLPEN   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOCLPEN   (UINT32_C(1) << 2)
 
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIODLPEN   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOELPEN   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOFLPEN   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOGLPEN   (UINT32_C(1) << 6)
 
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOHLPEN   (UINT32_C(1) << 7)
 
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOILPEN   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOJLPEN   (UINT32_C(1) << 9)
 
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOKLPEN   (UINT32_C(1) << 10)
 
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_RSV11   (UINT32_C(0x3FF) << 11)
 
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_RSV22   (UINT32_C(0x3F) << 22)
 
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_RSV30   (UINT32_C(3) << 30)
 
#define MCCI_STM32H7_REG_RCC_AHB4LPENR_SRDSRAMLPEN   (UINT32_C(1) << 29)
 
RCC_APB3LPENR bits
#define MCCI_STM32H7_REG_RCC_APB3LPENR_LTDCLPEN   (UINT32_C(1) << 25)
 
#define MCCI_STM32H7_REG_RCC_APB3LPENR_RSV0   (UINT32_C(7) << 0)
 
#define MCCI_STM32H7_REG_RCC_APB3LPENR_RSV4   (UINT32_C(3) << 4)
 
#define MCCI_STM32H7_REG_RCC_APB3LPENR_RSV7   UINT32_C(0xFFFFFF80)
 
#define MCCI_STM32H7_REG_RCC_APB3LPENR_WWDGLPEN   (UINT32_C(1) << 26)
 
RCC_APB1LLPENR bits
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_CECLPEN   (UINT32_C(1) << 27)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_DAC1LPEN   (UINT32_C(1) << 29)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_I2C1LPEN   (UINT32_C(1) << 21)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_I2C2LPEN   (UINT32_C(1) << 22)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_I2C3LPEN   (UINT32_C(1) << 23)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_LPTIM1LPEN   (UINT32_C(1) << 9)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_RSV10   (UINT32_C(0xF) << 10)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_RSV24   (UINT32_C(7) << 24)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_RSV28   (UINT32_C(1) << 28)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_SPDIFRXLPEN   (UINT32_C(1) << 16)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_SPI2LPEN   (UINT32_C(1) << 14)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_SPI3LPEN   (UINT32_C(1) << 15)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM12LPEN   (UINT32_C(1) << 6)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM13LPEN   (UINT32_C(1) << 7)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM14LPEN   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM2LPEN   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM3LPEN   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM4LPEN   (UINT32_C(1) << 2)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM5LPEN   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM6LPEN   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM7LPEN   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_UART7LPEN   (UINT32_C(1) << 30)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_UART8LPEN   (UINT32_C(1) << 31)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_USART2LPEN   (UINT32_C(1) << 17)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_USART3LPEN   (UINT32_C(1) << 18)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_USART4LPEN   (UINT32_C(1) << 19)
 
#define MCCI_STM32H7_REG_RCC_APB1LLPENR_USART5LPEN   (UINT32_C(1) << 20)
 
RCC_APB1HLPENR bits
#define MCCI_STM32H7_REG_RCC_APB1HLPENR_CRSLPEN   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_APB1HLPENR_FDCANLPEN   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_APB1HLPENR_MDIOSLPEN   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_APB1HLPENR_OPAMPLPEN   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_APB1HLPENR_RSV0   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_APB1HLPENR_RSV3   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_APB1HLPENR_RSV6   (UINT32_C(3) << 6)
 
#define MCCI_STM32H7_REG_RCC_APB1HLPENR_RSV9   UINT32_C(0xFFFFFE00)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB1HLPENR_SWPMILPEN   (UINT32_C(1) << 2)
 
RCC_APB2LPENR bits
#define MCCI_STM32H7_REG_RCC_APB2LPENR_DFSDM1LPEN   (UINT32_C(1) << 30)
 DFSDM1 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV14   (UINT32_C(3) << 14)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV19   (UINT32_C(1) << 19)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV2   (UINT32_C(3) << 2)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV21   (UINT32_C(1) << 21)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV24   (UINT32_C(0x3F) << 24)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV31   (UINT32_C(1) << 31)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV8   (UINT32_C(0xF) << 8)
 reserved, don't change
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_SAI1LPEN   (UINT32_C(1) << 22)
 SAI1 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_SAI2LPEN   (UINT32_C(1) << 23)
 SAI2 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_SPI1LPEN   (UINT32_C(1) << 12)
 SPI1 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_SPI4LPEN   (UINT32_C(1) << 13)
 SPI4 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_SPI5LPEN   (UINT32_C(1) << 20)
 SPI5 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_TIM15LPEN   (UINT32_C(1) << 16)
 TIM15 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_TIM16LPEN   (UINT32_C(1) << 17)
 TIM16 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_TIM17LPEN   (UINT32_C(1) << 18)
 TIM17 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_TIM1LPEN   (UINT32_C(1) << 0)
 TIM1 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_TIM8LPEN   (UINT32_C(1) << 1)
 TIM8 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_UART9LPEN   (UINT32_C(1) << 6)
 UART9 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_USART10LPEN   (UINT32_C(1) << 7)
 USART10 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_USART1LPEN   (UINT32_C(1) << 4)
 USART1 clock enable.
 
#define MCCI_STM32H7_REG_RCC_APB2LPENR_USART6LPEN   (UINT32_C(1) << 5)
 USART6 clock enable.
 
RCC_APB4LPENR bits
#define MCCI_STM32H7_REG_RCC_APB4LPENR_COMP12LPEN   (UINT32_C(1) << 14)
 
#define MCCI_STM32H7_REG_RCC_APB4LPENR_DAC2LPEN   (UINT32_C(1) << 13)
 
#define MCCI_STM32H7_REG_RCC_APB4LPENR_DFSDM2LPEN   (UINT32_C(1) << 27)
 
#define MCCI_STM32H7_REG_RCC_APB4LPENR_DTSLPEN   (UINT32_C(1) << 26)
 
#define MCCI_STM32H7_REG_RCC_APB4LPENR_I2C4LPEN   (UINT32_C(1) << 7)
 
#define MCCI_STM32H7_REG_RCC_APB4LPENR_LPTIM2LPEN   (UINT32_C(1) << 9)
 
#define MCCI_STM32H7_REG_RCC_APB4LPENR_LPTIM3LPEN   (UINT32_C(1) << 10)
 
#define MCCI_STM32H7_REG_RCC_APB4LPENR_LPUART1LPEN   (UINT32_C(1) << 3)
 
#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV0   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV11   (UINT32_C(3) << 11)
 
#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV17   (UINT32_C(0x1FF) << 17)
 
#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV2   (UINT32_C(1) << 2)
 
#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV28   (UINT32_C(0xF) << 28)
 
#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV4   (UINT32_C(1) << 4)
 
#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV6   (UINT32_C(1) << 6)
 
#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV8   (UINT32_C(1) << 8)
 
#define MCCI_STM32H7_REG_RCC_APB4LPENR_RTCAPBLPEN   (UINT32_C(1) << 16)
 
#define MCCI_STM32H7_REG_RCC_APB4LPENR_SPI6LPEN   (UINT32_C(1) << 5)
 
#define MCCI_STM32H7_REG_RCC_APB4LPENR_SYSCFGLPEN   (UINT32_C(1) << 1)
 
#define MCCI_STM32H7_REG_RCC_APB4LPENR_VREFLPEN   (UINT32_C(1) << 15)
 
GPIO register offsets
#define MCCI_STM32H7_GPIO_AFRH   UINT32_C(0x24)
 
#define MCCI_STM32H7_GPIO_AFRL   UINT32_C(0x20)
 
#define MCCI_STM32H7_GPIO_BSRR   UINT32_C(0x18)
 
#define MCCI_STM32H7_GPIO_IDR   UINT32_C(0x10)
 
#define MCCI_STM32H7_GPIO_LCKR   UINT32_C(0x1C)
 
#define MCCI_STM32H7_GPIO_MODER   UINT32_C(0x00)
 
#define MCCI_STM32H7_GPIO_ODR   UINT32_C(0x14)
 
#define MCCI_STM32H7_GPIO_OSPEEDR   UINT32_C(0x08)
 
#define MCCI_STM32H7_GPIO_OTYPER   UINT32_C(0x04)
 
#define MCCI_STM32H7_GPIO_PUPDR   UINT32_C(0x0C)
 
GPIO_MODER bits – used to select pin mode, two bits per pin
#define MCCI_STM32H7_GPIO_MODE_AF   UINT32_C(2)
 
#define MCCI_STM32H7_GPIO_MODE_ANALOG   UINT32_C(3)
 
#define MCCI_STM32H7_GPIO_MODE_IN   UINT32_C(0)
 
#define MCCI_STM32H7_GPIO_MODE_MASK   UINT32_C(3)
 
#define MCCI_STM32H7_GPIO_MODE_OUT   UINT32_C(1)
 
GPIO_OTYPER bits
#define MCCI_STM32H7_GPIO_OTYPE_OD   UINT32_C(1)
 
#define MCCI_STM32H7_GPIO_OTYPE_PP   UINT32_C(0)
 
GPIO_OSPEEDR bits – used to select pin speed, two bits per pin
#define MCCI_STM32H7_GPIO_OSPEED_HIGH   UINT32_C(2)
 
#define MCCI_STM32H7_GPIO_OSPEED_LOW   UINT32_C(0)
 
#define MCCI_STM32H7_GPIO_OSPEED_MASK   UINT32_C(3)
 
#define MCCI_STM32H7_GPIO_OSPEED_MEDIUM   UINT32_C(1)
 
#define MCCI_STM32H7_GPIO_OSPEED_VHIGH   UINT32_C(3)
 
GPIO_PUPDR bits – used to select pin speed, two bits per pin
#define MCCI_STM32H7_GPIO_PUPD_MASK   UINT32_C(3)
 
#define MCCI_STM32H7_GPIO_PUPD_NONE   UINT32_C(0)
 
#define MCCI_STM32H7_GPIO_PUPD_PULLDOWN   UINT32_C(2)
 
#define MCCI_STM32H7_GPIO_PUPD_PULLUP   UINT32_C(1)
 
GPIO_BSRR bits
#define MCCI_STM32H7_GPIO_BSRR_BR   (UINT32_C(0xFFFF) << 16)
 
#define MCCI_STM32H7_GPIO_BSRR_BR0   (UINT32_C(1) << 16)
 
#define MCCI_STM32H7_GPIO_BSRR_BR_P(p)   (MCCI_STM32H7_GPIO_BSRR_BR0 << (p))
 compute port-bit reset mask for bit p.
 
#define MCCI_STM32H7_GPIO_BSRR_BS   (UINT32_C(0xFFFF) << 0)
 
#define MCCI_STM32H7_GPIO_BSRR_BS0   (UINT32_C(1) << 0)
 
#define MCCI_STM32H7_GPIO_BSRR_BS_P(p)   (MCCI_STM32H7_GPIO_BSRR_BS0 << (p))
 compute port-bit set mask for bit p.
 
GPIO_LCKR bits
#define MCCI_STM32H7_GPIO_LCKR_LCK   (UINT32_C(0xFFFF) << 0)
 
#define MCCI_STM32H7_GPIO_LCKR_LCK_P(p)   (UINT32_C(1) << (p))
 compute GPIO lock bit fmask for bit p.
 
#define MCCI_STM32H7_GPIO_LCKR_LCKK   (UINT32_C(1) << 16)
 
#define MCCI_STM32H7_GPIO_LCKR_RSV17   UINT32_C(0xFFFE0000)
 
GPIO_AFRx bits

get reg offset for GPIO_AFRx

#define MCCI_STM32H7_GPIO_AFRx_P(p)   (MCCI_STM32H7_GPIO_AFRL + (((p) / UINT32_C(8)) * UINT32_C(4)))
 
SPI offsets
#define MCCI_STM32H7_SPI_CFG1   UINT32_C(0x08)
 offset to SPI configuration register 1
 
#define MCCI_STM32H7_SPI_CFG2   UINT32_C(0x0C)
 offset to SPI configuration register 2
 
#define MCCI_STM32H7_SPI_CR1   UINT32_C(0x00)
 offset to SPI control register 1
 
#define MCCI_STM32H7_SPI_CR2   UINT32_C(0x04)
 offset to SPI control register 2
 
#define MCCI_STM32H7_SPI_CRCPOLY   UINT32_C(0x40)
 offset to SPI CRC polynomial
 
#define MCCI_STM32H7_SPI_I2SCFGR   UINT32_C(0x50)
 offset to SPI I2S config register
 
#define MCCI_STM32H7_SPI_IER   UINT32_C(0x10)
 offset to SPI interrupt enable register
 
#define MCCI_STM32H7_SPI_IFCR   UINT32_C(0x18)
 offset to SPI interrupt/status flags clear register
 
#define MCCI_STM32H7_SPI_RXCRC   UINT32_C(0x48)
 offset to SPI receive CRC
 
#define MCCI_STM32H7_SPI_RXDR   UINT32_C(0x30)
 offset to SPI receive data register
 
#define MCCI_STM32H7_SPI_SR   UINT32_C(0x14)
 offset to SPI status register
 
#define MCCI_STM32H7_SPI_TXCRC   UINT32_C(0x44)
 offset to SPI transmit CRC
 
#define MCCI_STM32H7_SPI_TXDR   UINT32_C(0x20)
 offset to SPI transmit data register
 
#define MCCI_STM32H7_SPI_UDRDR   UINT32_C(0x4C)
 offset to SPI underrun data CRC
 
SPI_CR1 bits
#define MCCI_STM32H7_SPI_CR1_CRC33_17   (UINT32_C(1) << 13)
 32-bit CRC polynomial configuration
 
#define MCCI_STM32H7_SPI_CR1_CSTART   (UINT32_C(1) << 9)
 master transfer start
 
#define MCCI_STM32H7_SPI_CR1_CSUSP   (UINT32_C(1) << 10)
 master suspend request
 
#define MCCI_STM32H7_SPI_CR1_HDDIR   (UINT32_C(1) << 11)
 Rx/Tx direction at Half-duplex mode.
 
#define MCCI_STM32H7_SPI_CR1_IOLOCK   (UINT32_C(1) << 16)
 locking the AF configuration of associated IOs
 
#define MCCI_STM32H7_SPI_CR1_MASRX   (UINT32_C(1) << 8)
 master automatic SUSP in Receive mode
 
#define MCCI_STM32H7_SPI_CR1_RCRCINI   (UINT32_C(1) << 14)
 CRC calculation initialization pattern control for receiver.
 
#define MCCI_STM32H7_SPI_CR1_RSV1   (UINT32_C(0x7F) << 1)
 reserved, don't change
 
#define MCCI_STM32H7_SPI_CR1_RSV17   UINT32_C(0xFFFE0000)
 reserved, don't change
 
#define MCCI_STM32H7_SPI_CR1_SPE   (UINT32_C(1) << 0)
 serial peripheral enable
 
#define MCCI_STM32H7_SPI_CR1_SSI   (UINT32_C(1) << 12)
 internal SS signal input level
 
#define MCCI_STM32H7_SPI_CR1_TCRCINI   (UINT32_C(1) << 15)
 CRC calculation initialization pattern control for transmitter.
 
SPI_CR2 bits
#define MCCI_STM32H7_SPI_CR2_TSER   UINT32_C(0xFFFF0000)
 number of data transfer extension to be reload into TSIZE
 
#define MCCI_STM32H7_SPI_CR2_TSIZE   UINT32_C(0x0000FFFF)
 number of data at current transfer
 
SPI_CFG1 bits
#define MCCI_STM32H7_SPI_CFG1_CRCEN   (UINT32_C(1) << 22)
 hardware CRC computation enable
 
#define MCCI_STM32H7_SPI_CFG1_CRCSIZE   (UINT32_C(0x1F) << 16)
 length of CRC frame to be transacted and compared
 
#define MCCI_STM32H7_SPI_CFG1_CRCSIZE_N(n)   ((n) << 16)
 n+1 bits
 
#define MCCI_STM32H7_SPI_CFG1_DSIZE   (UINT32_C(0x1F) << 0)
 number of bits in at single SPI data frame
 
#define MCCI_STM32H7_SPI_CFG1_DSIZE_N(n)   ((n) << 0)
 n+1 bits
 
#define MCCI_STM32H7_SPI_CFG1_FTHLV   (UINT32_C(0xF) << 5)
 FIFO threshold level.
 
#define MCCI_STM32H7_SPI_CFG1_FTHLV_N(n)   ((n) << 5)
 n+1 data
 
#define MCCI_STM32H7_SPI_CFG1_MBR   (UINT32_C(7) << 28)
 master baud rate
 
#define MCCI_STM32H7_SPI_CFG1_MBR_128   (UINT32_C(6) << 28)
 SPI master clock/128.
 
#define MCCI_STM32H7_SPI_CFG1_MBR_16   (UINT32_C(3) << 28)
 SPI master clock/16.
 
#define MCCI_STM32H7_SPI_CFG1_MBR_2   (UINT32_C(0) << 28)
 SPI master clock/2.
 
#define MCCI_STM32H7_SPI_CFG1_MBR_256   (UINT32_C(7) << 28)
 SPI master clock/256.
 
#define MCCI_STM32H7_SPI_CFG1_MBR_32   (UINT32_C(4) << 28)
 SPI master clock/32.
 
#define MCCI_STM32H7_SPI_CFG1_MBR_4   (UINT32_C(1) << 28)
 SPI master clock/4.
 
#define MCCI_STM32H7_SPI_CFG1_MBR_64   (UINT32_C(5) << 28)
 SPI master clock/64.
 
#define MCCI_STM32H7_SPI_CFG1_MBR_8   (UINT32_C(2) << 28)
 SPI master clock/8.
 
#define MCCI_STM32H7_SPI_CFG1_RSV13   (UINT32_C(1) << 13)
 reserved, don't change
 
#define MCCI_STM32H7_SPI_CFG1_RSV21   (UINT32_C(1) << 21)
 reserved, don't change
 
#define MCCI_STM32H7_SPI_CFG1_RSV23   (UINT32_C(0x1F) << 23)
 reserved, don't change
 
#define MCCI_STM32H7_SPI_CFG1_RSV31   (UINT32_C(1) << 31)
 reserved, don't change
 
#define MCCI_STM32H7_SPI_CFG1_RXDMAEN   (UINT32_C(1) << 14)
 Rx DMA stream enable.
 
#define MCCI_STM32H7_SPI_CFG1_TXDMAEN   (UINT32_C(1) << 15)
 Tx DMA stream enable.
 
#define MCCI_STM32H7_SPI_CFG1_UDRCFG   (UINT32_C(3) << 9)
 behavior of slave transmitter at underrun condition
 
#define MCCI_STM32H7_SPI_CFG1_UDRCFG_CONST   (UINT32_C(0) << 9)
 slave sends a constant pattern defined by the user at SPI_UDRDR register
 
#define MCCI_STM32H7_SPI_CFG1_UDRCFG_RX   (UINT32_C(1) << 9)
 slave repeats lastly received data frame from master
 
#define MCCI_STM32H7_SPI_CFG1_UDRCFG_TX   (UINT32_C(2) << 9)
 slave repeats its lastly transmitted data frame
 
#define MCCI_STM32H7_SPI_CFG1_UDRDET   (UINT32_C(3) << 11)
 detection of underrun condition at slave transmitter
 
#define MCCI_STM32H7_SPI_CFG1_UDRDET_BEGIN   (UINT32_C(0) << 11)
 underrun is detected at begin of data frame
 
#define MCCI_STM32H7_SPI_CFG1_UDRDET_BEGIN_SS   (UINT32_C(2) << 11)
 underrun is detected at begin of active SS signal
 
#define MCCI_STM32H7_SPI_CFG1_UDRDET_END   (UINT32_C(1) << 11)
 underrun is detected at end of data frame
 
SPI_CFG2 bits
#define MCCI_STM32H7_SPI_CFG2_AFCNTR   (UINT32_C(1) << 31)
 alternate function GPIOs control
 
#define MCCI_STM32H7_SPI_CFG2_COMM   (UINT32_C(3) << 17)
 SPI communication mode.
 
#define MCCI_STM32H7_SPI_CFG2_COMM_FULL_DUPLEX   (UINT32_C(0) << 17)
 full-duplex
 
#define MCCI_STM32H7_SPI_CFG2_COMM_HALF_DUPLEX   (UINT32_C(3) << 17)
 half-duplex
 
#define MCCI_STM32H7_SPI_CFG2_COMM_SIMPLEX_RX   (UINT32_C(2) << 17)
 simplex receiver
 
#define MCCI_STM32H7_SPI_CFG2_COMM_SIMPLEX_TX   (UINT32_C(1) << 17)
 simplex transmitter
 
#define MCCI_STM32H7_SPI_CFG2_CPHA   (UINT32_C(1) << 24)
 clock phase
 
#define MCCI_STM32H7_SPI_CFG2_CPOL   (UINT32_C(1) << 25)
 clock polarity
 
#define MCCI_STM32H7_SPI_CFG2_IOSWP   (UINT32_C(1) << 15)
 swap functionality of MISO and MOSI pins
 
#define MCCI_STM32H7_SPI_CFG2_LSBFRST   (UINT32_C(1) << 23)
 data frame format
 
#define MCCI_STM32H7_SPI_CFG2_MASTER   (UINT32_C(1) << 22)
 SPI master.
 
#define MCCI_STM32H7_SPI_CFG2_MIDI   (UINT32_C(15) << 4)
 master Inter-Data Idleness
 
#define MCCI_STM32H7_SPI_CFG2_MIDI_N(n)   ((n) << 4)
 n clock cycle period delay
 
#define MCCI_STM32H7_SPI_CFG2_MSSI   (UINT32_C(15) << 0)
 master SS idleness
 
#define MCCI_STM32H7_SPI_CFG2_MSSI_N(n)   ((n) << 0)
 n clock cycle period delay added
 
#define MCCI_STM32H7_SPI_CFG2_RSV16   (UINT32_C(1) << 16)
 reserved, don't change
 
#define MCCI_STM32H7_SPI_CFG2_RSV27   (UINT32_C(1) << 27)
 reserved, don't change
 
#define MCCI_STM32H7_SPI_CFG2_RSV8   (UINT32_C(0x7F) << 8)
 reserved, don't change
 
#define MCCI_STM32H7_SPI_CFG2_SP   (UINT32_C(7) << 19)
 Serial protocol.
 
#define MCCI_STM32H7_SPI_CFG2_SSIOP   (UINT32_C(1) << 28)
 SS input/output polarity.
 
#define MCCI_STM32H7_SPI_CFG2_SSM   (UINT32_C(1) << 26)
 software management of SS signal input
 
#define MCCI_STM32H7_SPI_CFG2_SSOE   (UINT32_C(1) << 29)
 SS output enable.
 
#define MCCI_STM32H7_SPI_CFG2_SSOM   (UINT32_C(1) << 30)
 SS output management in master mode.
 
SPI_IER bits
#define MCCI_STM32H7_SPI_IER_CRCEIE   (UINT32_C(1) << 7)
 CRC error interrupt enable.
 
#define MCCI_STM32H7_SPI_IER_DXPIE   (UINT32_C(1) << 2)
 DXP interrupt enabled.
 
#define MCCI_STM32H7_SPI_IER_EOTIE   (UINT32_C(1) << 3)
 EOT, SUSP and TXC interrupt enable.
 
#define MCCI_STM32H7_SPI_IER_MODFIE   (UINT32_C(1) << 9)
 mode fault interrupt enable
 
#define MCCI_STM32H7_SPI_IER_OVRIE   (UINT32_C(1) << 6)
 OVR interrupt enable.
 
#define MCCI_STM32H7_SPI_IER_RSV11   UINT32_C(0xFFFFFF80)
 reserved, don't change
 
#define MCCI_STM32H7_SPI_IER_RXPIE   (UINT32_C(1) << 0)
 RXP Interrupt Enable.
 
#define MCCI_STM32H7_SPI_IER_TIFREIE   (UINT32_C(1) << 8)
 TIFRE interrupt enable.
 
#define MCCI_STM32H7_SPI_IER_TSERFIE   (UINT32_C(1) << 10)
 additional number of transactions reload interrupt enable
 
#define MCCI_STM32H7_SPI_IER_TXPIE   (UINT32_C(1) << 1)
 TXP interrupt enable.
 
#define MCCI_STM32H7_SPI_IER_TXTFIE   (UINT32_C(1) << 4)
 TXTFIE interrupt enable.
 
#define MCCI_STM32H7_SPI_IER_UDRIE   (UINT32_C(1) << 5)
 UDR interrupt enable.
 
SPI_SR bits
#define MCCI_STM32H7_SPI_SR_CRCE   (UINT32_C(1) << 7)
 CRC error.
 
#define MCCI_STM32H7_SPI_SR_CTSIZE   UINT32_C(0xFFFF0000)
 number of data frames remaining in current TSIZE session
 
#define MCCI_STM32H7_SPI_SR_DXP   (UINT32_C(1) << 2)
 duplex packet
 
#define MCCI_STM32H7_SPI_SR_EOT   (UINT32_C(1) << 3)
 end of transfer
 
#define MCCI_STM32H7_SPI_SR_MODF   (UINT32_C(1) << 9)
 mode fault
 
#define MCCI_STM32H7_SPI_SR_OVR   (UINT32_C(1) << 6)
 overrun
 
#define MCCI_STM32H7_SPI_SR_RXP   (UINT32_C(1) << 0)
 Rx-packet available.
 
#define MCCI_STM32H7_SPI_SR_RXPLVL   (UINT32_C(3) << 13)
 RxFIFO packing leveL.
 
#define MCCI_STM32H7_SPI_SR_RXPLVL_N(n)   ((n) << 13)
 n frame is available
 
#define MCCI_STM32H7_SPI_SR_RXWNE   (UINT32_C(1) << 15)
 RxFIFO word not empty.
 
#define MCCI_STM32H7_SPI_SR_SUSP   (UINT32_C(1) << 11)
 suspension status
 
#define MCCI_STM32H7_SPI_SR_TIFRE   (UINT32_C(1) << 8)
 TI frame format error.
 
#define MCCI_STM32H7_SPI_SR_TSERF   (UINT32_C(1) << 10)
 additional number of SPI data to be transacted was reload
 
#define MCCI_STM32H7_SPI_SR_TXC   (UINT32_C(1) << 12)
 TxFIFO transmission complete.
 
#define MCCI_STM32H7_SPI_SR_TXP   (UINT32_C(1) << 1)
 Tx-packet space available.
 
#define MCCI_STM32H7_SPI_SR_TXTF   (UINT32_C(1) << 4)
 transmission transfer filled
 
#define MCCI_STM32H7_SPI_SR_UDR   (UINT32_C(1) << 5)
 underrun at slave transmission mode
 
SPI_IFCR bits
#define MCCI_STM32H7_SPI_IFCR_CRCEC   (UINT32_C(1) << 7)
 CRC error flag clear.
 
#define MCCI_STM32H7_SPI_IFCR_EOTC   (UINT32_C(1) << 3)
 EOT, SUSP and TXC flag clear.
 
#define MCCI_STM32H7_SPI_IFCR_MODFC   (UINT32_C(1) << 9)
 mode fault flag clear
 
#define MCCI_STM32H7_SPI_IFCR_OVRC   (UINT32_C(1) << 6)
 OVR flag clear.
 
#define MCCI_STM32H7_SPI_IFCR_RSV0   (UINT32_C(7) << 0)
 reserved, don't change
 
#define MCCI_STM32H7_SPI_IFCR_RSV12   UINT32_C(0xFFFFFF00)
 reserved, don't change
 
#define MCCI_STM32H7_SPI_IFCR_SUSPC   (UINT32_C(1) << 11)
 SUSPend flag clear.
 
#define MCCI_STM32H7_SPI_IFCR_TIFREC   (UINT32_C(1) << 8)
 TIFRE flag clear.
 
#define MCCI_STM32H7_SPI_IFCR_TSERFC   (UINT32_C(1) << 10)
 additional number of transactions reload flag clear
 
#define MCCI_STM32H7_SPI_IFCR_TXTFC   (UINT32_C(1) << 4)
 TXTFC flag clear.
 
#define MCCI_STM32H7_SPI_IFCR_UDRC   (UINT32_C(1) << 5)
 UDR flag clear.
 
SPI_I2SCFGR bits
#define MCCI_STM32H7_SPI_I2SCFGR_CHLEN   (UINT32_C(1) << 10)
 channel length
 
#define MCCI_STM32H7_SPI_I2SCFGR_CKPOL   (UINT32_C(1) << 11)
 serial audio clock polarity
 
#define MCCI_STM32H7_SPI_I2SCFGR_DATFMT   (UINT32_C(1) << 14)
 data format
 
#define MCCI_STM32H7_SPI_I2SCFGR_DATLEN   (UINT32_C(3) << 8)
 data length to be transferred
 
#define MCCI_STM32H7_SPI_I2SCFGR_DATLEN_16   (UINT32_C(0) << 8)
 16 bit
 
#define MCCI_STM32H7_SPI_I2SCFGR_DATLEN_24   (UINT32_C(1) << 8)
 24 bit
 
#define MCCI_STM32H7_SPI_I2SCFGR_DATLEN_32   (UINT32_C(2) << 8)
 32 bit
 
#define MCCI_STM32H7_SPI_I2SCFGR_FIXCH   (UINT32_C(1) << 12)
 fixed channel length in slave
 
#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG   (UINT32_C(7) << 1)
 I2S configuration mode.
 
#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_MFD   (UINT32_C(5) << 1)
 master - full duplex
 
#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_MRX   (UINT32_C(3) << 1)
 master - receive
 
#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_MTX   (UINT32_C(2) << 1)
 master - transmit
 
#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_SFD   (UINT32_C(4) << 1)
 slave - full duplex
 
#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_SRX   (UINT32_C(1) << 1)
 slave - receive
 
#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_STX   (UINT32_C(0) << 1)
 slave - transmit
 
#define MCCI_STM32H7_SPI_I2SCFGR_I2SDIV   (UINT32_C(0xFF) << 16)
 I2S linear prescaler.
 
#define MCCI_STM32H7_SPI_I2SCFGR_I2SDIV_N(n)   ((n) << 16)
 
#define MCCI_STM32H7_SPI_I2SCFGR_I2SMOD   (UINT32_C(1) << 0)
 I2S mode selection.
 
#define MCCI_STM32H7_SPI_I2SCFGR_I2SSTD   (UINT32_C(3) << 4)
 I2S standard selection.
 
#define MCCI_STM32H7_SPI_I2SCFGR_I2SSTD_LSB   (UINT32_C(2) << 4)
 LSB justified standard.
 
#define MCCI_STM32H7_SPI_I2SCFGR_I2SSTD_MSB   (UINT32_C(1) << 4)
 MSB justified standard.
 
#define MCCI_STM32H7_SPI_I2SCFGR_I2SSTD_PCM   (UINT32_C(3) << 4)
 PCM standard.
 
#define MCCI_STM32H7_SPI_I2SCFGR_I2SSTD_PHILIPS   (UINT32_C(0) << 4)
 I2S Philips standard.
 
#define MCCI_STM32H7_SPI_I2SCFGR_MCKOE   (UINT32_C(1) << 25)
 master clock output enable
 
#define MCCI_STM32H7_SPI_I2SCFGR_ODD   (UINT32_C(1) << 24)
 odd factor for the prescaler
 
#define MCCI_STM32H7_SPI_I2SCFGR_PCMSYNC   (UINT32_C(1) << 7)
 PCM frame synchronization.
 
#define MCCI_STM32H7_SPI_I2SCFGR_RSV15   (UINT32_C(1) << 15)
 reserved (do not change)
 
#define MCCI_STM32H7_SPI_I2SCFGR_RSV26   (UINT32_C(0x3F) << 26)
 reserved (do not change)
 
#define MCCI_STM32H7_SPI_I2SCFGR_RSV6   (UINT32_C(1) << 6)
 reserved (do not change)
 
#define MCCI_STM32H7_SPI_I2SCFGR_WSINV   (UINT32_C(1) << 13)
 Word select inversion.
 
DMA offsets
#define MCCI_STM32H7_DMA_HIFCR   UINT32_C(0x0C)
 offset to DMA high interrupt flag clear register
 
#define MCCI_STM32H7_DMA_HISR   UINT32_C(0x04)
 offset to DMA high interrupt status register
 
#define MCCI_STM32H7_DMA_LIFCR   UINT32_C(0x08)
 offset to DMA low interrupt flag clear register
 
#define MCCI_STM32H7_DMA_LISR   UINT32_C(0x00)
 offset to DMA low interrupt status register
 
#define MCCI_STM32H7_DMA_SCR   UINT32_C(0x00)
 offset to DMA stream configuration register
 
#define MCCI_STM32H7_DMA_SFCR   UINT32_C(0x14)
 offset to DMA stream FIFO control register
 
#define MCCI_STM32H7_DMA_SM0AR   UINT32_C(0x0C)
 offset to DMA stream memory 0 address register
 
#define MCCI_STM32H7_DMA_SM1AR   UINT32_C(0x10)
 offset to DMA stream memory 1 address register
 
#define MCCI_STM32H7_DMA_SNDTR   UINT32_C(0x04)
 offset to DMA stream number of data register
 
#define MCCI_STM32H7_DMA_SPAR   UINT32_C(0x08)
 offset to DMA stream peripheral address register
 
#define MCCI_STM32H7_DMA_STREAM_BASE(x)   (((x) * UINT32_C(0x18)) + UINT32_C(0x10))
 offset to DMA stream x base
 
#define MCCI_STM32H7_DMA_SxCR(x)   (((x) * UINT32_C(0x18)) + UINT32_C(0x10))
 offset to DMA stream x configuration register
 
#define MCCI_STM32H7_DMA_SxFCR(x)   (((x) * UINT32_C(0x18)) + UINT32_C(0x24))
 offset to DMA stream x FIFO control register
 
#define MCCI_STM32H7_DMA_SxM0AR(x)   (((x) * UINT32_C(0x18)) + UINT32_C(0x1C))
 offset to DMA stream x memory 0 address register
 
#define MCCI_STM32H7_DMA_SxM1AR(x)   (((x) * UINT32_C(0x18)) + UINT32_C(0x20))
 offset to DMA stream x memory 1 address register
 
#define MCCI_STM32H7_DMA_SxNDTR(x)   (((x) * UINT32_C(0x18)) + UINT32_C(0x14))
 offset to DMA stream x number of data register
 
#define MCCI_STM32H7_DMA_SxPAR(x)   (((x) * UINT32_C(0x18)) + UINT32_C(0x18))
 offset to DMA stream x peripheral address register
 
DMA stream base address
#define MCCI_STM32H7_DMA1_STREAM_BASE(x)    (MCCI_STM32H7_REG_DMA1 + MCCI_STM32H7_DMA_STREAM_BASE(x))
 
#define MCCI_STM32H7_DMA2_STREAM_BASE(x)    (MCCI_STM32H7_REG_DMA2 + MCCI_STM32H7_DMA_STREAM_BASE(x))
 
#define MCCI_STM32H7_DMA_GET_STREAM(b)   ((((b) & UINT32_C(0xFF)) - UINT32_C(0x10)) / UINT32_C(0x18))
 
DMA_LISR and DMA_FISR bits
#define MCCI_STM32H7_DMA_ISR_DMEIF   (UINT32_C(1) << 2)
 direct mode error interrupt flag
 
#define MCCI_STM32H7_DMA_ISR_DMEIF0   (UINT32_C(1) << 2)
 direct mode error interrupt flag
 
#define MCCI_STM32H7_DMA_ISR_DMEIF1   (UINT32_C(1) << 8)
 direct mode error interrupt flag
 
#define MCCI_STM32H7_DMA_ISR_DMEIF2   (UINT32_C(1) << 18)
 direct mode error interrupt flag
 
#define MCCI_STM32H7_DMA_ISR_DMEIF3   (UINT32_C(1) << 24)
 direct mode error interrupt flag
 
#define MCCI_STM32H7_DMA_ISR_FEIF   (UINT32_C(1) << 0)
 FIFO error interrupt flag.
 
#define MCCI_STM32H7_DMA_ISR_FEIF0   (UINT32_C(1) << 0)
 FIFO error interrupt flag.
 
#define MCCI_STM32H7_DMA_ISR_FEIF1   (UINT32_C(1) << 6)
 FIFO error interrupt flag.
 
#define MCCI_STM32H7_DMA_ISR_FEIF2   (UINT32_C(1) << 16)
 FIFO error interrupt flag.
 
#define MCCI_STM32H7_DMA_ISR_FEIF3   (UINT32_C(1) << 22)
 FIFO error interrupt flag.
 
#define MCCI_STM32H7_DMA_ISR_HTIF   (UINT32_C(1) << 4)
 half transfer interrupt flag
 
#define MCCI_STM32H7_DMA_ISR_HTIF0   (UINT32_C(1) << 4)
 half transfer interrupt flag
 
#define MCCI_STM32H7_DMA_ISR_HTIF1   (UINT32_C(1) << 10)
 half transfer interrupt flag
 
#define MCCI_STM32H7_DMA_ISR_HTIF2   (UINT32_C(1) << 20)
 half transfer interrupt flag
 
#define MCCI_STM32H7_DMA_ISR_HTIF3   (UINT32_C(1) << 26)
 half transfer interrupt flag
 
#define MCCI_STM32H7_DMA_ISR_MASK   UINT32_C(0x3D)
 ISR stream mask.
 
#define MCCI_STM32H7_DMA_ISR_RSV1   (UINT32_C(1) << 1)
 reserved, don't change
 
#define MCCI_STM32H7_DMA_ISR_RSV12   UINT32_C(0x0000F000)
 reserved, don't change
 
#define MCCI_STM32H7_DMA_ISR_RSV17   (UINT32_C(1) << 17)
 reserved, don't change
 
#define MCCI_STM32H7_DMA_ISR_RSV23   (UINT32_C(1) << 23)
 reserved, don't change
 
#define MCCI_STM32H7_DMA_ISR_RSV28   UINT32_C(0xF0000000)
 reserved, don't change
 
#define MCCI_STM32H7_DMA_ISR_RSV7   (UINT32_C(1) << 7)
 reserved, don't change
 
#define MCCI_STM32H7_DMA_ISR_TCIF   (UINT32_C(1) << 5)
 transfer complete interrupt flag
 
#define MCCI_STM32H7_DMA_ISR_TCIF0   (UINT32_C(1) << 5)
 transfer complete interrupt flag
 
#define MCCI_STM32H7_DMA_ISR_TCIF1   (UINT32_C(1) << 11)
 transfer complete interrupt flag
 
#define MCCI_STM32H7_DMA_ISR_TCIF2   (UINT32_C(1) << 21)
 transfer complete interrupt flag
 
#define MCCI_STM32H7_DMA_ISR_TCIF3   (UINT32_C(1) << 27)
 transfer complete interrupt flag
 
#define MCCI_STM32H7_DMA_ISR_TEIF   (UINT32_C(1) << 3)
 transfer error interrupt flag
 
#define MCCI_STM32H7_DMA_ISR_TEIF0   (UINT32_C(1) << 3)
 transfer error interrupt flag
 
#define MCCI_STM32H7_DMA_ISR_TEIF1   (UINT32_C(1) << 9)
 transfer error interrupt flag
 
#define MCCI_STM32H7_DMA_ISR_TEIF2   (UINT32_C(1) << 19)
 transfer error interrupt flag
 
#define MCCI_STM32H7_DMA_ISR_TEIF3   (UINT32_C(1) << 25)
 transfer error interrupt flag
 
DMA_SCR bits
#define MCCI_STM32H7_DMA_SCR_CIRC   (UINT32_C(1) << 8)
 circular mode
 
#define MCCI_STM32H7_DMA_SCR_CT   (UINT32_C(1) << 19)
 current target (only in double-buffer mode)
 
#define MCCI_STM32H7_DMA_SCR_DBM   (UINT32_C(1) << 18)
 double-buffer mode
 
#define MCCI_STM32H7_DMA_SCR_DIR   (UINT32_C(3) << 6)
 data transfer direction
 
#define MCCI_STM32H7_DMA_SCR_DIR_MEM_TO_MEM   (UINT32_C(2) << 6)
 memory-to-memory
 
#define MCCI_STM32H7_DMA_SCR_DIR_MEM_TO_PERI   (UINT32_C(1) << 6)
 memory-to-peripheral
 
#define MCCI_STM32H7_DMA_SCR_DIR_PERI_TO_MEM   (UINT32_C(0) << 6)
 peripheral-to-memory
 
#define MCCI_STM32H7_DMA_SCR_DMEIE   (UINT32_C(1) << 1)
 direct mode error interrupt enable
 
#define MCCI_STM32H7_DMA_SCR_EN   (UINT32_C(1) << 0)
 stream enable / flag stream ready when read low
 
#define MCCI_STM32H7_DMA_SCR_HTIE   (UINT32_C(1) << 3)
 half transfer interrupt enable
 
#define MCCI_STM32H7_DMA_SCR_MBURST   (UINT32_C(3) << 23)
 memory burst transfer configuration
 
#define MCCI_STM32H7_DMA_SCR_MBURST_INCR16   (UINT32_C(3) << 23)
 INCR16 (incremental burst of 16 beats)
 
#define MCCI_STM32H7_DMA_SCR_MBURST_INCR4   (UINT32_C(1) << 23)
 INCR4 (incremental burst of 4 beats)
 
#define MCCI_STM32H7_DMA_SCR_MBURST_INCR8   (UINT32_C(2) << 23)
 INCR8 (incremental burst of 8 beats)
 
#define MCCI_STM32H7_DMA_SCR_MBURST_SINGLE   (UINT32_C(0) << 23)
 single transfer
 
#define MCCI_STM32H7_DMA_SCR_MINC   (UINT32_C(1) << 10)
 memory increment mode
 
#define MCCI_STM32H7_DMA_SCR_MSIZE   (UINT32_C(3) << 13)
 memory data size
 
#define MCCI_STM32H7_DMA_SCR_MSIZE_BYTE   (UINT32_C(0) << 13)
 byte (8-bit)
 
#define MCCI_STM32H7_DMA_SCR_MSIZE_HALF   (UINT32_C(1) << 13)
 hlaf-word (16-bit)
 
#define MCCI_STM32H7_DMA_SCR_MSIZE_WORD   (UINT32_C(2) << 13)
 word (32-bit)
 
#define MCCI_STM32H7_DMA_SCR_PBURST   (UINT32_C(3) << 21)
 peripheral burst transfer configuration
 
#define MCCI_STM32H7_DMA_SCR_PBURST_INCR16   (UINT32_C(3) << 21)
 INCR16 (incremental burst of 16 beats)
 
#define MCCI_STM32H7_DMA_SCR_PBURST_INCR4   (UINT32_C(1) << 21)
 INCR4 (incremental burst of 4 beats)
 
#define MCCI_STM32H7_DMA_SCR_PBURST_INCR8   (UINT32_C(2) << 21)
 INCR8 (incremental burst of 8 beats)
 
#define MCCI_STM32H7_DMA_SCR_PBURST_SINGLE   (UINT32_C(0) << 21)
 single transfer
 
#define MCCI_STM32H7_DMA_SCR_PFCTRL   (UINT32_C(1) << 5)
 peripheral flow controller
 
#define MCCI_STM32H7_DMA_SCR_PINC   (UINT32_C(1) << 9)
 peripheral increment mode
 
#define MCCI_STM32H7_DMA_SCR_PINCOS   (UINT32_C(1) << 15)
 peripheral increment offset size
 
#define MCCI_STM32H7_DMA_SCR_PL   (UINT32_C(3) << 16)
 priority level
 
#define MCCI_STM32H7_DMA_SCR_PL_HIGH   (UINT32_C(0) << 16)
 high
 
#define MCCI_STM32H7_DMA_SCR_PL_LOW   (UINT32_C(0) << 16)
 low
 
#define MCCI_STM32H7_DMA_SCR_PL_MEDIUM   (UINT32_C(0) << 16)
 medium
 
#define MCCI_STM32H7_DMA_SCR_PL_VERY_HIGH   (UINT32_C(0) << 16)
 very high
 
#define MCCI_STM32H7_DMA_SCR_PSIZE   (UINT32_C(3) << 11)
 peripheral data size
 
#define MCCI_STM32H7_DMA_SCR_PSIZE_BYTE   (UINT32_C(0) << 11)
 byte (8-bit)
 
#define MCCI_STM32H7_DMA_SCR_PSIZE_HALF   (UINT32_C(1) << 11)
 hlaf-word (16-bit)
 
#define MCCI_STM32H7_DMA_SCR_PSIZE_WORD   (UINT32_C(2) << 11)
 word (32-bit)
 
#define MCCI_STM32H7_DMA_SCR_RSV25   UINT32_C(0xFE000000)
 reserved, don't change
 
#define MCCI_STM32H7_DMA_SCR_TCIE   (UINT32_C(1) << 4)
 transfer complete interrupt enable
 
#define MCCI_STM32H7_DMA_SCR_TEIE   (UINT32_C(1) << 2)
 transfer error interrupt enable
 
#define MCCI_STM32H7_DMA_SCR_TRBUFF   (UINT32_C(1) << 20)
 Enable the DMA to handle bufferable transfers.
 
DMA_SFCR bits
#define MCCI_STM32H7_DMA_SFCR_DMDIS   (UINT32_C(1) << 2)
 direct mode disable
 
#define MCCI_STM32H7_DMA_SFCR_FEIE   (UINT32_C(1) << 7)
 FIFO error interrupt enable.
 
#define MCCI_STM32H7_DMA_SFCR_FS   (UINT32_C(7) << 3)
 FIFO status.
 
#define MCCI_STM32H7_DMA_SFCR_FS_EMPTY   (UINT32_C(4) << 3)
 FIFO is empty.
 
#define MCCI_STM32H7_DMA_SFCR_FS_FULL   (UINT32_C(5) << 3)
 FIFO is full.
 
#define MCCI_STM32H7_DMA_SFCR_FS_LESS_1P2   (UINT32_C(1) << 3)
 1/4 <= fifo_level < 1/2
 
#define MCCI_STM32H7_DMA_SFCR_FS_LESS_1P4   (UINT32_C(0) << 3)
 0 < fifo_level < 1/4
 
#define MCCI_STM32H7_DMA_SFCR_FS_LESS_3P4   (UINT32_C(2) << 3)
 1/2 <= fifo_level < 3/4
 
#define MCCI_STM32H7_DMA_SFCR_FS_LESS_FULL   (UINT32_C(3) << 3)
 3/4 <= fifo_level < full
 
#define MCCI_STM32H7_DMA_SFCR_FTH   (UINT32_C(3) << 0)
 FIFO threshold selection.
 
#define MCCI_STM32H7_DMA_SFCR_FTH_1P2_FULL   (UINT32_C(1) << 0)
 1/4 full FIFO
 
#define MCCI_STM32H7_DMA_SFCR_FTH_1P4_FULL   (UINT32_C(0) << 0)
 1/4 full FIFO
 
#define MCCI_STM32H7_DMA_SFCR_FTH_3P4_FULL   (UINT32_C(2) << 0)
 1/4 full FIFO
 
#define MCCI_STM32H7_DMA_SFCR_FTH_FULL   (UINT32_C(3) << 0)
 1/4 full FIFO
 
#define MCCI_STM32H7_DMA_SFCR_RSV6   (UINT32_C(1) << 6)
 reserved, don't change
 
#define MCCI_STM32H7_DMA_SFCR_RSV8   UINT32_C(0xFFFFFF00)
 reserved, don't change
 
DMAMUX offsets
#define MCCI_STM32H7_DMAMUX1_C0CR   UINT32_C(0x00)
 offset to DMAMUX1 request line multiplexer channel 0 configuration register
 
#define MCCI_STM32H7_DMAMUX1_C10CR   UINT32_C(0x28)
 offset to DMAMUX1 request line multiplexer channel 10 configuration register
 
#define MCCI_STM32H7_DMAMUX1_C11CR   UINT32_C(0x2C)
 offset to DMAMUX1 request line multiplexer channel 11 configuration register
 
#define MCCI_STM32H7_DMAMUX1_C12CR   UINT32_C(0x30)
 offset to DMAMUX1 request line multiplexer channel 12 configuration register
 
#define MCCI_STM32H7_DMAMUX1_C13CR   UINT32_C(0x34)
 offset to DMAMUX1 request line multiplexer channel 13 configuration register
 
#define MCCI_STM32H7_DMAMUX1_C14CR   UINT32_C(0x38)
 offset to DMAMUX1 request line multiplexer channel 14 configuration register
 
#define MCCI_STM32H7_DMAMUX1_C15CR   UINT32_C(0x3C)
 offset to DMAMUX1 request line multiplexer channel 15 configuration register
 
#define MCCI_STM32H7_DMAMUX1_C1CR   UINT32_C(0x04)
 offset to DMAMUX1 request line multiplexer channel 1 configuration register
 
#define MCCI_STM32H7_DMAMUX1_C2CR   UINT32_C(0x08)
 offset to DMAMUX1 request line multiplexer channel 2 configuration register
 
#define MCCI_STM32H7_DMAMUX1_C3CR   UINT32_C(0x0C)
 offset to DMAMUX1 request line multiplexer channel 3 configuration register
 
#define MCCI_STM32H7_DMAMUX1_C4CR   UINT32_C(0x10)
 offset to DMAMUX1 request line multiplexer channel 4 configuration register
 
#define MCCI_STM32H7_DMAMUX1_C5CR   UINT32_C(0x14)
 offset to DMAMUX1 request line multiplexer channel 5 configuration register
 
#define MCCI_STM32H7_DMAMUX1_C6CR   UINT32_C(0x18)
 offset to DMAMUX1 request line multiplexer channel 6 configuration register
 
#define MCCI_STM32H7_DMAMUX1_C7CR   UINT32_C(0x1C)
 offset to DMAMUX1 request line multiplexer channel 7 configuration register
 
#define MCCI_STM32H7_DMAMUX1_C8CR   UINT32_C(0x20)
 offset to DMAMUX1 request line multiplexer channel 8 configuration register
 
#define MCCI_STM32H7_DMAMUX1_C9CR   UINT32_C(0x24)
 offset to DMAMUX1 request line multiplexer channel 9 configuration register
 
#define MCCI_STM32H7_DMAMUX1_CCR(x)   ((x) * UINT32_C(0x04))
 offset to DMAMUX1 request line multiplexer channel x configuration register
 
#define MCCI_STM32H7_DMAMUX1_CFR   UINT32_C(0x84)
 offset to DMAMUX1 request line multiplexer interrupt clear flag register
 
#define MCCI_STM32H7_DMAMUX1_CSR   UINT32_C(0x80)
 offset to DMAMUX1 request line multiplexer interrupt channel status register
 
#define MCCI_STM32H7_DMAMUX1_RG0CR   UINT32_C(0x100)
 offset to DMAMUX1 request generator channel 0 configuration register
 
#define MCCI_STM32H7_DMAMUX1_RG1CR   UINT32_C(0x104)
 offset to DMAMUX1 request generator channel 1 configuration register
 
#define MCCI_STM32H7_DMAMUX1_RG2CR   UINT32_C(0x108)
 offset to DMAMUX1 request generator channel 2 configuration register
 
#define MCCI_STM32H7_DMAMUX1_RG3CR   UINT32_C(0x10C)
 offset to DMAMUX1 request generator channel 3 configuration register
 
#define MCCI_STM32H7_DMAMUX1_RG4CR   UINT32_C(0x110)
 offset to DMAMUX1 request generator channel 4 configuration register
 
#define MCCI_STM32H7_DMAMUX1_RG5CR   UINT32_C(0x114)
 offset to DMAMUX1 request generator channel 5 configuration register
 
#define MCCI_STM32H7_DMAMUX1_RG6CR   UINT32_C(0x118)
 offset to DMAMUX1 request generator channel 6 configuration register
 
#define MCCI_STM32H7_DMAMUX1_RG7CR   UINT32_C(0x11C)
 offset to DMAMUX1 request generator channel 7 configuration register
 
#define MCCI_STM32H7_DMAMUX1_RGCFR   UINT32_C(0x144)
 offset to DMAMUX1 request generator interrupt clear flag register
 
#define MCCI_STM32H7_DMAMUX1_RGCR(x)   (UINT32_C(0x100) + ((x) * UINT32_C(0x04)))
 offset to DMAMUX1 request generator channel x configuration register
 
#define MCCI_STM32H7_DMAMUX1_RGSR   UINT32_C(0x140)
 offset to DMAMUX1 request generator interrupt channel status register
 
#define MCCI_STM32H7_DMAMUX2_C0CR   UINT32_C(0x00)
 offset to DMAMUX2 request line multiplexer channel 0 configuration register
 
#define MCCI_STM32H7_DMAMUX2_C1CR   UINT32_C(0x04)
 offset to DMAMUX2 request line multiplexer channel 1 configuration register
 
#define MCCI_STM32H7_DMAMUX2_C2CR   UINT32_C(0x08)
 offset to DMAMUX2 request line multiplexer channel 2 configuration register
 
#define MCCI_STM32H7_DMAMUX2_C3CR   UINT32_C(0x0C)
 offset to DMAMUX2 request line multiplexer channel 3 configuration register
 
#define MCCI_STM32H7_DMAMUX2_C4CR   UINT32_C(0x10)
 offset to DMAMUX2 request line multiplexer channel 4 configuration register
 
#define MCCI_STM32H7_DMAMUX2_C5CR   UINT32_C(0x14)
 offset to DMAMUX2 request line multiplexer channel 5 configuration register
 
#define MCCI_STM32H7_DMAMUX2_C6CR   UINT32_C(0x18)
 offset to DMAMUX2 request line multiplexer channel 6 configuration register
 
#define MCCI_STM32H7_DMAMUX2_C7CR   UINT32_C(0x1C)
 offset to DMAMUX2 request line multiplexer channel 7 configuration register
 
#define MCCI_STM32H7_DMAMUX2_CCR(x)   ((x) * UINT32_C(0x04))
 offset to DMAMUX2 request line multiplexer channel x configuration register
 
#define MCCI_STM32H7_DMAMUX2_CFR   UINT32_C(0x84)
 offset to DMAMUX2 request line multiplexer interrupt clear flag register
 
#define MCCI_STM32H7_DMAMUX2_CSR   UINT32_C(0x80)
 offset to DMAMUX2 request line multiplexer interrupt channel status register
 
#define MCCI_STM32H7_DMAMUX2_RG0CR   UINT32_C(0x100)
 offset to DMAMUX2 request generator channel 0 configuration register
 
#define MCCI_STM32H7_DMAMUX2_RG1CR   UINT32_C(0x104)
 offset to DMAMUX2 request generator channel 1 configuration register
 
#define MCCI_STM32H7_DMAMUX2_RG2CR   UINT32_C(0x108)
 offset to DMAMUX2 request generator channel 2 configuration register
 
#define MCCI_STM32H7_DMAMUX2_RG3CR   UINT32_C(0x10C)
 offset to DMAMUX2 request generator channel 3 configuration register
 
#define MCCI_STM32H7_DMAMUX2_RG4CR   UINT32_C(0x110)
 offset to DMAMUX2 request generator channel 4 configuration register
 
#define MCCI_STM32H7_DMAMUX2_RG5CR   UINT32_C(0x114)
 offset to DMAMUX2 request generator channel 5 configuration register
 
#define MCCI_STM32H7_DMAMUX2_RG6CR   UINT32_C(0x118)
 offset to DMAMUX2 request generator channel 6 configuration register
 
#define MCCI_STM32H7_DMAMUX2_RG7CR   UINT32_C(0x11C)
 offset to DMAMUX2 request generator channel 7 configuration register
 
#define MCCI_STM32H7_DMAMUX2_RGCFR   UINT32_C(0x144)
 offset to DMAMUX2 request generator interrupt clear flag register
 
#define MCCI_STM32H7_DMAMUX2_RGCR(x)   (UINT32_C(0x100) + ((x) * UINT32_C(0x04)))
 offset to DMAMUX2 request generator channel x configuration register
 
#define MCCI_STM32H7_DMAMUX2_RGSR   UINT32_C(0x140)
 offset to DMAMUX2 request generator interrupt channel status register
 
DMAMUX1_CxCR bits
#define MCCI_STM32H7_DMAMUX1_CxCR_DMAREQ_ID   (UINT32_C(0x7F) << 0)
 DMA request identification.
 
#define MCCI_STM32H7_DMAMUX1_CxCR_DMAREQ_ID_N(n)   ((n) << 0)
 
#define MCCI_STM32H7_DMAMUX1_CxCR_EGE   (UINT32_C(1) << 9)
 Event generation enable.
 
#define MCCI_STM32H7_DMAMUX1_CxCR_NBREQ   (UINT32_C(0x1F) << 19)
 Number of DMA requests minus 1 to forward.
 
#define MCCI_STM32H7_DMAMUX1_CxCR_NBREQ_N(n)   ((n) << 19)
 
#define MCCI_STM32H7_DMAMUX1_CxCR_RSV10   (UINT32_C(0x3F) << 10)
 reserved, don't change
 
#define MCCI_STM32H7_DMAMUX1_CxCR_RSV27   UINT32_C(0xF8000000)
 reserved, don't change
 
#define MCCI_STM32H7_DMAMUX1_CxCR_RSV7   (UINT32_C(1) << 7)
 reserved, don't change
 
#define MCCI_STM32H7_DMAMUX1_CxCR_SE   (UINT32_C(1) << 16)
 Synchronization enable.
 
#define MCCI_STM32H7_DMAMUX1_CxCR_SOIE   (UINT32_C(1) << 8)
 Synchronization overrun interrupt enable.
 
#define MCCI_STM32H7_DMAMUX1_CxCR_SPOL   (UINT32_C(3) << 17)
 Synchronization polarity.
 
#define MCCI_STM32H7_DMAMUX1_CxCR_SPOL_BOTH   (UINT32_C(3) << 17)
 rising and falling edges
 
#define MCCI_STM32H7_DMAMUX1_CxCR_SPOL_FALLING   (UINT32_C(2) << 17)
 falling edge
 
#define MCCI_STM32H7_DMAMUX1_CxCR_SPOL_NO   (UINT32_C(0) << 17)
 no event, i.e. no synchronization nor detection
 
#define MCCI_STM32H7_DMAMUX1_CxCR_SPOL_RISING   (UINT32_C(1) << 17)
 rising edge
 
#define MCCI_STM32H7_DMAMUX1_CxCR_SYNC_ID   (UINT32_C(7) << 24)
 Synchronization identification.
 
#define MCCI_STM32H7_DMAMUX1_CxCR_SYNC_ID_N(n)   ((n) << 24)
 
DMAMUX2_CxCR bits
#define MCCI_STM32H7_DMAMUX2_CxCR_DMAREQ_ID   (UINT32_C(0x1F) << 0)
 DMA request identification.
 
#define MCCI_STM32H7_DMAMUX2_CxCR_DMAREQ_ID_N(n)   ((n) << 0)
 
#define MCCI_STM32H7_DMAMUX2_CxCR_EGE   (UINT32_C(1) << 9)
 Event generation enable.
 
#define MCCI_STM32H7_DMAMUX2_CxCR_NBREQ   (UINT32_C(0x1F) << 19)
 Number of DMA requests minus 1 to forward.
 
#define MCCI_STM32H7_DMAMUX2_CxCR_NBREQ_N(n)   ((n) << 19)
 
#define MCCI_STM32H7_DMAMUX2_CxCR_RSV10   (UINT32_C(0x3F) << 10)
 reserved, don't change
 
#define MCCI_STM32H7_DMAMUX2_CxCR_RSV28   UINT32_C(0xF0000000)
 reserved, don't change
 
#define MCCI_STM32H7_DMAMUX2_CxCR_RSV7   (UINT32_C(7) << 5)
 reserved, don't change
 
#define MCCI_STM32H7_DMAMUX2_CxCR_SE   (UINT32_C(1) << 16)
 Synchronization enable.
 
#define MCCI_STM32H7_DMAMUX2_CxCR_SOIE   (UINT32_C(1) << 8)
 Synchronization overrun interrupt enable.
 
#define MCCI_STM32H7_DMAMUX2_CxCR_SPOL   (UINT32_C(3) << 17)
 Synchronization polarity.
 
#define MCCI_STM32H7_DMAMUX2_CxCR_SPOL_BOTH   (UINT32_C(3) << 17)
 rising and falling edges
 
#define MCCI_STM32H7_DMAMUX2_CxCR_SPOL_FALLING   (UINT32_C(2) << 17)
 falling edge
 
#define MCCI_STM32H7_DMAMUX2_CxCR_SPOL_NO   (UINT32_C(0) << 17)
 no event, i.e. no synchronization nor detection
 
#define MCCI_STM32H7_DMAMUX2_CxCR_SPOL_RISING   (UINT32_C(1) << 17)
 rising edge
 
#define MCCI_STM32H7_DMAMUX2_CxCR_SYNC_ID   (UINT32_C(0xF) << 24)
 Synchronization identification.
 
#define MCCI_STM32H7_DMAMUX2_CxCR_SYNC_ID_N(n)   ((n) << 24)
 
DMAMUX1_RGxCR bits
#define MCCI_STM32H7_DMAMUX1_RGxCR_GE   (UINT32_C(1) << 16)
 DMA request generator channel x enable.
 
#define MCCI_STM32H7_DMAMUX1_RGxCR_GNBREQ   (UINT32_C(0x1F) << 19)
 Number of DMA requests to be generated (minus 1)
 
#define MCCI_STM32H7_DMAMUX1_RGxCR_GNBREQ_N(n)   ((n) << 19)
 
#define MCCI_STM32H7_DMAMUX1_RGxCR_GPOL   (UINT32_C(3) << 17)
 DMA request generator trigger polarity.
 
#define MCCI_STM32H7_DMAMUX1_RGxCR_GPOL_BOTH   (UINT32_C(3) << 17)
 rising and falling edges
 
#define MCCI_STM32H7_DMAMUX1_RGxCR_GPOL_FALLING   (UINT32_C(2) << 17)
 falling edge
 
#define MCCI_STM32H7_DMAMUX1_RGxCR_GPOL_NO   (UINT32_C(0) << 17)
 no event, i.e. no synchronization nor detection
 
#define MCCI_STM32H7_DMAMUX1_RGxCR_GPOL_RISING   (UINT32_C(1) << 17)
 rising edge
 
#define MCCI_STM32H7_DMAMUX1_RGxCR_OIE   (UINT32_C(1) << 8)
 Trigger overrun interrupt enable.
 
#define MCCI_STM32H7_DMAMUX1_RGxCR_RSV24   UINT32_C(0xFF000000)
 reserved, don't change
 
#define MCCI_STM32H7_DMAMUX1_RGxCR_RSV3   (UINT32_C(0x1F) << 3)
 reserved, don't change
 
#define MCCI_STM32H7_DMAMUX1_RGxCR_RSV9   (UINT32_C(0x7F) << 9)
 reserved, don't change
 
#define MCCI_STM32H7_DMAMUX1_RGxCR_SIG_ID   (UINT32_C(7) << 0)
 Signal identification.
 
#define MCCI_STM32H7_DMAMUX1_RGxCR_SIG_ID_N(n)   ((n) << 0)
 
DMAMUX2_RGxCR bits
#define MCCI_STM32H7_DMAMUX2_RGxCR_GE   (UINT32_C(1) << 16)
 DMA request generator channel x enable.
 
#define MCCI_STM32H7_DMAMUX2_RGxCR_GNBREQ   (UINT32_C(0x1F) << 19)
 Number of DMA requests to be generated (minus 1)
 
#define MCCI_STM32H7_DMAMUX2_RGxCR_GNBREQ_N(n)   ((n) << 19)
 
#define MCCI_STM32H7_DMAMUX2_RGxCR_GPOL   (UINT32_C(3) << 17)
 DMA request generator trigger polarity.
 
#define MCCI_STM32H7_DMAMUX2_RGxCR_GPOL_BOTH   (UINT32_C(3) << 17)
 rising and falling edges
 
#define MCCI_STM32H7_DMAMUX2_RGxCR_GPOL_FALLING   (UINT32_C(2) << 17)
 falling edge
 
#define MCCI_STM32H7_DMAMUX2_RGxCR_GPOL_NO   (UINT32_C(0) << 17)
 no event, i.e. no synchronization nor detection
 
#define MCCI_STM32H7_DMAMUX2_RGxCR_GPOL_RISING   (UINT32_C(1) << 17)
 rising edge
 
#define MCCI_STM32H7_DMAMUX2_RGxCR_OIE   (UINT32_C(1) << 8)
 Trigger overrun interrupt enable.
 
#define MCCI_STM32H7_DMAMUX2_RGxCR_RSV24   UINT32_C(0xFF000000)
 reserved, don't change
 
#define MCCI_STM32H7_DMAMUX2_RGxCR_RSV5   (UINT32_C(7) << 5)
 reserved, don't change
 
#define MCCI_STM32H7_DMAMUX2_RGxCR_RSV9   (UINT32_C(0x7F) << 9)
 reserved, don't change
 
#define MCCI_STM32H7_DMAMUX2_RGxCR_SIG_ID   (UINT32_C(0x1F) << 0)
 Signal identification.
 
#define MCCI_STM32H7_DMAMUX2_RGxCR_SIG_ID_N(n)   ((n) << 0)
 
DCMI offsets
#define MCCI_STM32H7_DCMI_CR   UINT32_C(0x00)
 offset to DCMI control register
 
#define MCCI_STM32H7_DCMI_CWSIZE   UINT32_C(0x24)
 offset to DCMI crop window size
 
#define MCCI_STM32H7_DCMI_CWSTRT   UINT32_C(0x20)
 offset to DCMI crop window start
 
#define MCCI_STM32H7_DCMI_DR   UINT32_C(0x28)
 offset to DCMI data register
 
#define MCCI_STM32H7_DCMI_ESCR   UINT32_C(0x18)
 offset to DCMI embedded synchronization code register
 
#define MCCI_STM32H7_DCMI_ESUR   UINT32_C(0x1C)
 offset to DCMI embedded synchronization unmask register
 
#define MCCI_STM32H7_DCMI_ICR   UINT32_C(0x14)
 offset to DCMI interrupt clear register
 
#define MCCI_STM32H7_DCMI_IER   UINT32_C(0x0C)
 offset to DCMI interrupt enable register
 
#define MCCI_STM32H7_DCMI_MIS   UINT32_C(0x10)
 offset to DCMI masked interrupt status register
 
#define MCCI_STM32H7_DCMI_RIS   UINT32_C(0x08)
 offset to DCMI raw interrupt status register
 
#define MCCI_STM32H7_DCMI_SR   UINT32_C(0x04)
 offset to DCMI status register
 
DCMI_CR bits
#define MCCI_STM32H7_DCMI_CR_BSM   (UINT32_C(3) << 16)
 Byte Select mode.
 
#define MCCI_STM32H7_DCMI_CR_BSM_N(n)   ((n) << 16)
 
#define MCCI_STM32H7_DCMI_CR_CAPTURE   (UINT32_C(1) << 0)
 Capture enable.
 
#define MCCI_STM32H7_DCMI_CR_CM   (UINT32_C(1) << 1)
 Capture mode.
 
#define MCCI_STM32H7_DCMI_CR_CROP   (UINT32_C(1) << 2)
 Crop feature.
 
#define MCCI_STM32H7_DCMI_CR_EDM   (UINT32_C(3) << 10)
 Extended data mode.
 
#define MCCI_STM32H7_DCMI_CR_EDM_N(n)   ((n) << 10)
 
#define MCCI_STM32H7_DCMI_CR_ENABLE   (UINT32_C(1) << 14)
 DCMI enable.
 
#define MCCI_STM32H7_DCMI_CR_ESS   (UINT32_C(1) << 4)
 Embedded synchronization select.
 
#define MCCI_STM32H7_DCMI_CR_FCRC   (UINT32_C(3) << 8)
 Frame capture rate control.
 
#define MCCI_STM32H7_DCMI_CR_FCRC_N(n)   ((n) << 8)
 
#define MCCI_STM32H7_DCMI_CR_HSPOL   (UINT32_C(1) << 6)
 Horizontal synchronization polarity.
 
#define MCCI_STM32H7_DCMI_CR_JPEG   (UINT32_C(1) << 3)
 JPEG format.
 
#define MCCI_STM32H7_DCMI_CR_LSM   (UINT32_C(1) << 19)
 Line Select mode.
 
#define MCCI_STM32H7_DCMI_CR_OEBS   (UINT32_C(1) << 18)
 Odd/Even Byte Select (Byte Select Start)
 
#define MCCI_STM32H7_DCMI_CR_OELS   (UINT32_C(1) << 20)
 Odd/Even Line Select (Line Select Start)
 
#define MCCI_STM32H7_DCMI_CR_PCKPOL   (UINT32_C(1) << 5)
 Pixel clock polarity.
 
#define MCCI_STM32H7_DCMI_CR_RSV12   (UINT32_C(3) << 12)
 reserved, don't change
 
#define MCCI_STM32H7_DCMI_CR_RSV15   (UINT32_C(1) << 15)
 reserved, don't change
 
#define MCCI_STM32H7_DCMI_CR_RSV21   UINT32_C(0xFFE00000)
 reserved, don't change
 
#define MCCI_STM32H7_DCMI_CR_VSPOL   (UINT32_C(1) << 7)
 Vertical synchronization polarity.
 
DCMI_SR bits
#define MCCI_STM32H7_DCMI_SR_FNE   (UINT32_C(1) << 2)
 FIFO not empty.
 
#define MCCI_STM32H7_DCMI_SR_HSYNC   (UINT32_C(1) << 0)
 Horizontal synchronization.
 
#define MCCI_STM32H7_DCMI_SR_RSV3   UINT32_C(0xFFFFFFF8)
 reserved, don't change
 
#define MCCI_STM32H7_DCMI_SR_VSYNC   (UINT32_C(1) << 1)
 Vertical synchronization.
 
DCMI_RIS bits
#define MCCI_STM32H7_DCMI_RIS_ERR   (UINT32_C(1) << 2)
 Synchronization error raw interrupt status.
 
#define MCCI_STM32H7_DCMI_RIS_FRAME   (UINT32_C(1) << 0)
 Capture complete raw interrupt status.
 
#define MCCI_STM32H7_DCMI_RIS_LINE   (UINT32_C(1) << 4)
 Line raw interrupt status.
 
#define MCCI_STM32H7_DCMI_RIS_OVR   (UINT32_C(1) << 1)
 Overrun raw interrupt status.
 
#define MCCI_STM32H7_DCMI_RIS_RSV5   UINT32_C(0xFFFFFFE0)
 reserved, don't change
 
#define MCCI_STM32H7_DCMI_RIS_VSYNC   (UINT32_C(1) << 3)
 DCMI_VSYNC raw interrupt status.
 
DCMI_IER bits
#define MCCI_STM32H7_DCMI_IER_ERR   (UINT32_C(1) << 2)
 Synchronization interrupt enable.
 
#define MCCI_STM32H7_DCMI_IER_FRAME   (UINT32_C(1) << 0)
 Capture complete interrupt enable.
 
#define MCCI_STM32H7_DCMI_IER_LINE   (UINT32_C(1) << 4)
 Line interrupt enable.
 
#define MCCI_STM32H7_DCMI_IER_OVR   (UINT32_C(1) << 1)
 Overrun interrupt enable.
 
#define MCCI_STM32H7_DCMI_IER_RSV5   UINT32_C(0xFFFFFFE0)
 reserved, don't change
 
#define MCCI_STM32H7_DCMI_IER_VSYNC   (UINT32_C(1) << 3)
 DCMI_VSYNC interrupt enable.
 
DCMI_MIS bits
#define MCCI_STM32H7_DCMI_MIS_ERR   (UINT32_C(1) << 2)
 Synchronization maskedinterrupt status.
 
#define MCCI_STM32H7_DCMI_MIS_FRAME   (UINT32_C(1) << 0)
 Capture complete maskedinterrupt status.
 
#define MCCI_STM32H7_DCMI_MIS_LINE   (UINT32_C(1) << 4)
 Line maskedinterrupt status.
 
#define MCCI_STM32H7_DCMI_MIS_OVR   (UINT32_C(1) << 1)
 Overrun maskedinterrupt status.
 
#define MCCI_STM32H7_DCMI_MIS_RSV5   UINT32_C(0xFFFFFFE0)
 reserved, don't change
 
#define MCCI_STM32H7_DCMI_MIS_VSYNC   (UINT32_C(1) << 3)
 DCMI_VSYNC maskedinterrupt status.
 
DCMI_ICR bits
#define MCCI_STM32H7_DCMI_ICR_ERR   (UINT32_C(1) << 2)
 Synchronization raw interrupt status clear.
 
#define MCCI_STM32H7_DCMI_ICR_FRAME   (UINT32_C(1) << 0)
 Capture complete interrupt status clear.
 
#define MCCI_STM32H7_DCMI_ICR_LINE   (UINT32_C(1) << 4)
 Line interrupt status clear.
 
#define MCCI_STM32H7_DCMI_ICR_OVR   (UINT32_C(1) << 1)
 Overrun interrupt status clear.
 
#define MCCI_STM32H7_DCMI_ICR_RSV5   UINT32_C(0xFFFFFFE0)
 reserved, don't change
 
#define MCCI_STM32H7_DCMI_ICR_VSYNC   (UINT32_C(1) << 3)
 DCMI_VSYNC interrupt status clear.
 
DCMI_ESCR bits
#define MCCI_STM32H7_DCMI_ESCR_FEC   (UINT32_C(0xFF) << 24)
 Frame end delimiter code.
 
#define MCCI_STM32H7_DCMI_ESCR_FEC_N(n)   ((n) << 24)
 
#define MCCI_STM32H7_DCMI_ESCR_FSC   (UINT32_C(0xFF) << 0)
 Frame start delimiter code.
 
#define MCCI_STM32H7_DCMI_ESCR_FSC_N(n)   ((n) << 0)
 
#define MCCI_STM32H7_DCMI_ESCR_LEC   (UINT32_C(0xFF) << 16)
 Line end delimiter code.
 
#define MCCI_STM32H7_DCMI_ESCR_LEC_N(n)   ((n) << 16)
 
#define MCCI_STM32H7_DCMI_ESCR_LSC   (UINT32_C(0xFF) << 8)
 Line start delimiter code.
 
#define MCCI_STM32H7_DCMI_ESCR_LSC_N(n)   ((n) << 8)
 
DCMI_ESUR bits
#define MCCI_STM32H7_DCMI_ESUR_FEU   (UINT32_C(0xFF) << 24)
 Frame end delimiter unmask.
 
#define MCCI_STM32H7_DCMI_ESUR_FEU_N(n)   ((n) << 24)
 
#define MCCI_STM32H7_DCMI_ESUR_FSU   (UINT32_C(0xFF) << 0)
 Frame start delimiter unmask.
 
#define MCCI_STM32H7_DCMI_ESUR_FSU_N(n)   ((n) << 0)
 
#define MCCI_STM32H7_DCMI_ESUR_LEU   (UINT32_C(0xFF) << 16)
 Line end delimiter unmask.
 
#define MCCI_STM32H7_DCMI_ESUR_LEU_N(n)   ((n) << 16)
 
#define MCCI_STM32H7_DCMI_ESUR_LSU   (UINT32_C(0xFF) << 8)
 Line start delimiter unmask.
 
#define MCCI_STM32H7_DCMI_ESUR_LSU_N(n)   ((n) << 8)
 
DCMI_CWSTRT bits
#define MCCI_STM32H7_DCMI_CWSTRT_HOFFCNT   (UINT32_C(0x3FFF) << 0)
 Horizontal offset count.
 
#define MCCI_STM32H7_DCMI_CWSTRT_HOFFCNT_N(n)   ((n) << 0)
 
#define MCCI_STM32H7_DCMI_CWSTRT_RSV14   (UINT32_C(3) << 14)
 reserved, don't change
 
#define MCCI_STM32H7_DCMI_CWSTRT_RSV29   (UINT32_C(7) << 29)
 reserved, don't change
 
#define MCCI_STM32H7_DCMI_CWSTRT_VST   (UINT32_C(0x1FFF) << 16)
 Vertical start line count.
 
#define MCCI_STM32H7_DCMI_CWSTRT_VST_N(n)   ((n) << 16)
 
DCMI_CWSIZE bits
#define MCCI_STM32H7_DCMI_CWSIZE_CAPCNT   (UINT32_C(0x3FFF) << 0)
 Capture count.
 
#define MCCI_STM32H7_DCMI_CWSIZE_CAPCNT_N(n)   ((n) << 0)
 
#define MCCI_STM32H7_DCMI_CWSIZE_RSV14   (UINT32_C(3) << 14)
 reserved, don't change
 
#define MCCI_STM32H7_DCMI_CWSIZE_RSV30   (UINT32_C(3) << 30)
 reserved, don't change
 
#define MCCI_STM32H7_DCMI_CWSIZE_VLINE   (UINT32_C(0x3FFF) << 16)
 Vertical line count.
 
#define MCCI_STM32H7_DCMI_CWSIZE_VLINE_N(n)   ((n) << 16)
 
I2C offsets
#define MCCI_STM32H7_I2C_CR1   UINT32_C(0x00)
 offset to I2C control register 1
 
#define MCCI_STM32H7_I2C_CR2   UINT32_C(0x04)
 offset to I2C control register 2
 
#define MCCI_STM32H7_I2C_ICR   UINT32_C(0x1C)
 offset to I2C interrupt clear register
 
#define MCCI_STM32H7_I2C_ISR   UINT32_C(0x18)
 offset to I2C interrupt and status register
 
#define MCCI_STM32H7_I2C_OAR1   UINT32_C(0x08)
 offset to I2C own address 1 register
 
#define MCCI_STM32H7_I2C_OAR2   UINT32_C(0x0C)
 offset to I2C own address 2 register
 
#define MCCI_STM32H7_I2C_PECR   UINT32_C(0x20)
 offset to I2C PEC register
 
#define MCCI_STM32H7_I2C_RXDR   UINT32_C(0x24)
 offset to I2C receive data register
 
#define MCCI_STM32H7_I2C_TIMINGR   UINT32_C(0x10)
 offset to I2C timing register
 
#define MCCI_STM32H7_I2C_TIMOUTR   UINT32_C(0x14)
 offset to I2C timeout register
 
#define MCCI_STM32H7_I2C_TXDR   UINT32_C(0x28)
 offset to I2C transmit data register
 
I2C_CR1 bits
#define MCCI_STM32H7_I2C_CR1_ADDRIE   (UINT32_C(1) << 3)
 Address match Interrupt enable (slave only)
 
#define MCCI_STM32H7_I2C_CR1_ALERTEN   (UINT32_C(1) << 22)
 SMBus alert enable.
 
#define MCCI_STM32H7_I2C_CR1_ANFOFF   (UINT32_C(1) << 12)
 Analog noise filter OFF.
 
#define MCCI_STM32H7_I2C_CR1_DNF   (UINT32_C(0xF) << 8)
 Digital noise filter.
 
#define MCCI_STM32H7_I2C_CR1_DNF_N(n)   ((n) << 8)
 
#define MCCI_STM32H7_I2C_CR1_ERRIE   (UINT32_C(1) << 7)
 Error interrupts enable.
 
#define MCCI_STM32H7_I2C_CR1_GCEN   (UINT32_C(1) << 19)
 General call enable.
 
#define MCCI_STM32H7_I2C_CR1_NACKIE   (UINT32_C(1) << 4)
 Not acknowledge received Interrupt enable.
 
#define MCCI_STM32H7_I2C_CR1_NOSTRETCH   (UINT32_C(1) << 17)
 Clock stretching disable.
 
#define MCCI_STM32H7_I2C_CR1_PE   (UINT32_C(1) << 0)
 Peripheral enable.
 
#define MCCI_STM32H7_I2C_CR1_PECEN   (UINT32_C(1) << 23)
 PEC enable.
 
#define MCCI_STM32H7_I2C_CR1_RSV13   (UINT32_C(1) << 13)
 reserved, don't change
 
#define MCCI_STM32H7_I2C_CR1_RSV24   UINT32_C(0xFF000000)
 reserved, don't change
 
#define MCCI_STM32H7_I2C_CR1_RXDMAEN   (UINT32_C(1) << 15)
 DMA reception requests enable.
 
#define MCCI_STM32H7_I2C_CR1_RXIE   (UINT32_C(1) << 2)
 RX Interrupt enable.
 
#define MCCI_STM32H7_I2C_CR1_SBC   (UINT32_C(1) << 16)
 Slave byte control.
 
#define MCCI_STM32H7_I2C_CR1_SMBDEN   (UINT32_C(1) << 21)
 SMBus Device Default Address enable.
 
#define MCCI_STM32H7_I2C_CR1_SMBHEN   (UINT32_C(1) << 20)
 SMBus Host Address enable.
 
#define MCCI_STM32H7_I2C_CR1_STOPIE   (UINT32_C(1) << 5)
 Stop detection Interrupt enable.
 
#define MCCI_STM32H7_I2C_CR1_TCIE   (UINT32_C(1) << 6)
 Transfer Complete interrupt enable.
 
#define MCCI_STM32H7_I2C_CR1_TXDMAEN   (UINT32_C(1) << 14)
 DMA transmission requests enable.
 
#define MCCI_STM32H7_I2C_CR1_TXIE   (UINT32_C(1) << 1)
 TX Interrupt enable.
 
#define MCCI_STM32H7_I2C_CR1_WUPEN   (UINT32_C(1) << 18)
 Wakeup from Stop mode enable.
 
I2C_CR2 bits
#define MCCI_STM32H7_I2C_CR2_ADD10   (UINT32_C(1) << 11)
 10-bit addressing mode (master mode)
 
#define MCCI_STM32H7_I2C_CR2_AUTOEND   (UINT32_C(1) << 25)
 Automatic end mode (master mode)
 
#define MCCI_STM32H7_I2C_CR2_HEAD10R   (UINT32_C(1) << 12)
 10-bit address header only read direction (master receiver mode)
 
#define MCCI_STM32H7_I2C_CR2_NACK   (UINT32_C(1) << 15)
 NACK generation (slave mode)
 
#define MCCI_STM32H7_I2C_CR2_NBYTES   (UINT32_C(0xFF) << 16)
 Number of bytes.
 
#define MCCI_STM32H7_I2C_CR2_NBYTES_N(n)   ((n) << 16)
 
#define MCCI_STM32H7_I2C_CR2_PECBYTE   (UINT32_C(1) << 26)
 Packet error checking byte.
 
#define MCCI_STM32H7_I2C_CR2_RD_WRN   (UINT32_C(1) << 10)
 Transfer direction (master mode)
 
#define MCCI_STM32H7_I2C_CR2_RELOAD   (UINT32_C(1) << 24)
 NBYTES reload mode.
 
#define MCCI_STM32H7_I2C_CR2_RSV27   UINT32_C(0xF8000000)
 reserved, don't change
 
#define MCCI_STM32H7_I2C_CR2_SADD   (UINT32_C(0x3FF) << 0)
 Slave address (master mode)
 
#define MCCI_STM32H7_I2C_CR2_SADD_N(n)   ((n) << 0)
 
#define MCCI_STM32H7_I2C_CR2_START   (UINT32_C(1) << 13)
 Start generation.
 
#define MCCI_STM32H7_I2C_CR2_STOP   (UINT32_C(1) << 14)
 Stop generation (master mode)
 
I2C_OAR1 bits
#define MCCI_STM32H7_I2C_OAR1_OA1   (UINT32_C(0x3FF) << 0)
 Interface own slave address.
 
#define MCCI_STM32H7_I2C_OAR1_OA1_N(n)   ((n) << 0)
 
#define MCCI_STM32H7_I2C_OAR1_OA1EN   (UINT32_C(1) << 15)
 Own Address 1 enable.
 
#define MCCI_STM32H7_I2C_OAR1_OA1MODE   (UINT32_C(1) << 10)
 Own Address 1 10-bit mode.
 
#define MCCI_STM32H7_I2C_OAR1_RSV11   (UINT32_C(0xF) << 11)
 reserved, don't change
 
#define MCCI_STM32H7_I2C_OAR1_RSV16   UINT32_C(0xFFFF0000)
 reserved, don't change
 
I2C_OAR2 bits
#define MCCI_STM32H7_I2C_OAR2_OA2   (UINT32_C(0xFF) << 0)
 Interface address.
 
#define MCCI_STM32H7_I2C_OAR2_OA2_N(n)   ((n) << 0)
 
#define MCCI_STM32H7_I2C_OAR2_OA2EN   (UINT32_C(1) << 15)
 Own Address 2 enable.
 
#define MCCI_STM32H7_I2C_OAR2_OA2MSK   (UINT32_C(7) << 8)
 Own Address 2 masks.
 
#define MCCI_STM32H7_I2C_OAR2_OA2MSK_N(n)   ((n) << 8)
 
#define MCCI_STM32H7_I2C_OAR2_RSV11   (UINT32_C(0xF) << 11)
 reserved, don't change
 
#define MCCI_STM32H7_I2C_OAR2_RSV16   UINT32_C(0xFFFF0000)
 reserved, don't change
 
I2C_TIMINGR bits
#define MCCI_STM32H7_I2C_TIMINGR_PRESC   (UINT32_C(0xF) << 28)
 Timing prescaler.
 
#define MCCI_STM32H7_I2C_TIMINGR_PRESC_N(n)   ((n) << 28)
 
#define MCCI_STM32H7_I2C_TIMINGR_RSV24   (UINT32_C(0xF) << 24)
 reserved, don't change
 
#define MCCI_STM32H7_I2C_TIMINGR_SCLDEL   (UINT32_C(0xF) << 20)
 Data setup time.
 
#define MCCI_STM32H7_I2C_TIMINGR_SCLDEL_N(n)   ((n) << 20)
 
#define MCCI_STM32H7_I2C_TIMINGR_SCLH   (UINT32_C(0xFF) << 8)
 SCL high period (master mode)
 
#define MCCI_STM32H7_I2C_TIMINGR_SCLH_N(n)   ((n) << 8)
 
#define MCCI_STM32H7_I2C_TIMINGR_SCLL   (UINT32_C(0xFF) << 0)
 SCL low period (master mode)
 
#define MCCI_STM32H7_I2C_TIMINGR_SCLL_N(n)   ((n) << 0)
 
#define MCCI_STM32H7_I2C_TIMINGR_SDADEL   (UINT32_C(0xF) << 16)
 Data hold time.
 
#define MCCI_STM32H7_I2C_TIMINGR_SDADEL_N(n)   ((n) << 16)
 
I2C_TIMEOUTR bits
#define MCCI_STM32H7_I2C_TIMEOUTR_RSV28   (UINT32_C(7) << 28)
 reserved, don't change
 
#define MCCI_STM32H7_I2C_TIMEOUTR_TEXTEN   (UINT32_C(1) << 31)
 Extended clock timeout enable.
 
#define MCCI_STM32H7_I2C_TIMEOUTR_TIDLE   (UINT32_C(1) << 12)
 Idle clock timeout detection.
 
#define MCCI_STM32H7_I2C_TIMEOUTR_TIMEOUTA   (UINT32_C(0xFFF) << 0)
 Bus Timeout A.
 
#define MCCI_STM32H7_I2C_TIMEOUTR_TIMEOUTA_N(n)   ((n) << 0)
 
#define MCCI_STM32H7_I2C_TIMEOUTR_TIMEOUTB   (UINT32_C(0xFFF) << 16)
 Bus timeout B.
 
#define MCCI_STM32H7_I2C_TIMEOUTR_TIMEOUTB_N(n)   ((n) << 16)
 
#define MCCI_STM32H7_I2C_TIMEOUTR_TIMOUTEN   (UINT32_C(1) << 15)
 Clock timeout enable.
 
#define MCCI_STM32H7_I2C_TIMINGR_RSV13   (UINT32_C(3) << 13)
 reserved, don't change
 
I2C_ISR bits
#define MCCI_STM32H7_I2C_ISR_ADDCODE   (UINT32_C(0x7F) << 17)
 Address match code (Slave mode)
 
#define MCCI_STM32H7_I2C_ISR_ADDR   (UINT32_C(1) << 3)
 Address matched (slave mode)
 
#define MCCI_STM32H7_I2C_ISR_ALERT   (UINT32_C(1) << 13)
 SMBus alert.
 
#define MCCI_STM32H7_I2C_ISR_ARLO   (UINT32_C(1) << 9)
 Arbitration lost.
 
#define MCCI_STM32H7_I2C_ISR_BERR   (UINT32_C(1) << 8)
 Bus error.
 
#define MCCI_STM32H7_I2C_ISR_BUSY   (UINT32_C(1) << 15)
 Bus busy.
 
#define MCCI_STM32H7_I2C_ISR_DIR   (UINT32_C(1) << 16)
 Transfer direction (Slave mode)
 
#define MCCI_STM32H7_I2C_ISR_NACKF   (UINT32_C(1) << 4)
 Not Acknowledge received flag.
 
#define MCCI_STM32H7_I2C_ISR_OVR   (UINT32_C(1) << 10)
 Overrun/Underrun (slave mode)
 
#define MCCI_STM32H7_I2C_ISR_PECERR   (UINT32_C(1) << 11)
 PEC Error in reception.
 
#define MCCI_STM32H7_I2C_ISR_RSV14   (UINT32_C(1) << 14)
 reserved, don't change
 
#define MCCI_STM32H7_I2C_ISR_RSV24   UINT32_C(0xFF000000)
 reserved, don't change
 
#define MCCI_STM32H7_I2C_ISR_RXNE   (UINT32_C(1) << 2)
 Receive data register not empty (receivers)
 
#define MCCI_STM32H7_I2C_ISR_STOPF   (UINT32_C(1) << 5)
 Stop detection flag.
 
#define MCCI_STM32H7_I2C_ISR_TC   (UINT32_C(1) << 6)
 Transfer Complete (master mode)
 
#define MCCI_STM32H7_I2C_ISR_TCR   (UINT32_C(1) << 7)
 Transfer Complete Reload.
 
#define MCCI_STM32H7_I2C_ISR_TIMEOUT   (UINT32_C(1) << 12)
 Timeout or tLOW detection flag.
 
#define MCCI_STM32H7_I2C_ISR_TXE   (UINT32_C(1) << 0)
 Transmit data register empty (transmitters)
 
#define MCCI_STM32H7_I2C_ISR_TXIS   (UINT32_C(1) << 1)
 Transmit interrupt status (transmitters)
 
I2C_ICR bits
#define MCCI_STM32H7_I2C_ICR_ADDRCF   (UINT32_C(1) << 3)
 Address matched flag clear.
 
#define MCCI_STM32H7_I2C_ICR_ALERTCF   (UINT32_C(1) << 13)
 Alert flag clear.
 
#define MCCI_STM32H7_I2C_ICR_ARLOCF   (UINT32_C(1) << 9)
 Arbitration lost flag clear.
 
#define MCCI_STM32H7_I2C_ICR_BERRCF   (UINT32_C(1) << 8)
 Bus error flag clear.
 
#define MCCI_STM32H7_I2C_ICR_NACKCF   (UINT32_C(1) << 4)
 Not Acknowledge flag clear.
 
#define MCCI_STM32H7_I2C_ICR_OVRCF   (UINT32_C(1) << 10)
 Overrun/Underrun flag clear.
 
#define MCCI_STM32H7_I2C_ICR_PECCF   (UINT32_C(1) << 11)
 PEC Error flag clear.
 
#define MCCI_STM32H7_I2C_ICR_RSV0   (UINT32_C(7) << 0)
 reserved, don't change
 
#define MCCI_STM32H7_I2C_ICR_RSV14   UINT32_C(0xFFFFC000)
 reserved, don't change
 
#define MCCI_STM32H7_I2C_ICR_RSV6   (UINT32_C(3) << 6)
 reserved, don't change
 
#define MCCI_STM32H7_I2C_ICR_STOPCF   (UINT32_C(1) << 5)
 STOP detection flag clear.
 
#define MCCI_STM32H7_I2C_ICR_TIMEOUTCF   (UINT32_C(1) << 12)
 Timeout detection flag clear.
 
I2C_PECR bits
#define MCCI_STM32H7_I2C_PECR_PEC   (UINT32_C(0xFF) << 0)
 Packet error checking register.
 
#define MCCI_STM32H7_I2C_PECR_RSV8   UINT32_C(0xFFFFFF00)
 reserved, don't change
 
I2C_RXDR bits
#define MCCI_STM32H7_I2C_RXDR_RSV8   UINT32_C(0xFFFFFF00)
 reserved, don't change
 
#define MCCI_STM32H7_I2C_RXDR_RXDATA   (UINT32_C(0xFF) << 0)
 8-bit receive data
 
I2C_TXDR bits
#define MCCI_STM32H7_I2C_TXDR_RSV8   UINT32_C(0xFFFFFF00)
 reserved, don't change
 
#define MCCI_STM32H7_I2C_TXDR_TXDATA   (UINT32_C(0xFF) << 0)
 8-bit transmit data
 
Timer offsets
#define MCCI_STM32H7_TIM_AF1   UINT32_C(0x60)
 offset to TIM Alternate function option register 1
 
#define MCCI_STM32H7_TIM_AF2   UINT32_C(0x64)
 offset to TIM Alternate function option register 2
 
#define MCCI_STM32H7_TIM_ARR   UINT32_C(0x2C)
 offset to TIM auto-reload register
 
#define MCCI_STM32H7_TIM_BDTR   UINT32_C(0x44)
 offset to TIM break and dead-time register
 
#define MCCI_STM32H7_TIM_CCER   UINT32_C(0x20)
 offset to TIM capture/compare enable register
 
#define MCCI_STM32H7_TIM_CCMR1   UINT32_C(0x18)
 offset to TIM capture/compare mode register 1
 
#define MCCI_STM32H7_TIM_CCMR2   UINT32_C(0x1C)
 offset to TIM capture/compare mode register 2
 
#define MCCI_STM32H7_TIM_CCMR3   UINT32_C(0x54)
 offset to TIM capture/compare mode register 3
 
#define MCCI_STM32H7_TIM_CCR1   UINT32_C(0x34)
 offset to TIM capture/compare register 1
 
#define MCCI_STM32H7_TIM_CCR2   UINT32_C(0x38)
 offset to TIM capture/compare register 2
 
#define MCCI_STM32H7_TIM_CCR3   UINT32_C(0x3C)
 offset to TIM capture/compare register 3
 
#define MCCI_STM32H7_TIM_CCR4   UINT32_C(0x40)
 offset to TIM capture/compare register 4
 
#define MCCI_STM32H7_TIM_CCR5   UINT32_C(0x58)
 offset to TIM capture/compare register 5
 
#define MCCI_STM32H7_TIM_CCR6   UINT32_C(0x5C)
 offset to TIM capture/compare register 6
 
#define MCCI_STM32H7_TIM_CNT   UINT32_C(0x24)
 offset to TIM counter register
 
#define MCCI_STM32H7_TIM_CR1   UINT32_C(0x00)
 offset to TIM control register 1
 
#define MCCI_STM32H7_TIM_CR2   UINT32_C(0x04)
 offset to TIM control register 2
 
#define MCCI_STM32H7_TIM_DCR   UINT32_C(0x48)
 offset to TIM DMA control register
 
#define MCCI_STM32H7_TIM_DIER   UINT32_C(0x0C)
 offset to TIM DMA/interrupt enable register
 
#define MCCI_STM32H7_TIM_DMAR   UINT32_C(0x4C)
 offset to TIM DMA address register
 
#define MCCI_STM32H7_TIM_EGR   UINT32_C(0x14)
 offset to TIM event generation register
 
#define MCCI_STM32H7_TIM_PSC   UINT32_C(0x28)
 offset to TIM prescaler register
 
#define MCCI_STM32H7_TIM_RCR   UINT32_C(0x30)
 offset to TIM repetition counter register
 
#define MCCI_STM32H7_TIM_SMCR   UINT32_C(0x08)
 offset to TIM slave mode control register
 
#define MCCI_STM32H7_TIM_SR   UINT32_C(0x10)
 offset to TIM status register
 
#define MCCI_STM32H7_TIM_TISEL   UINT32_C(0x68)
 offset to TIM timer input selection register
 
TIM_CR1 bits
#define MCCI_STM32H7_TIM_CR1_ARPE   (UINT32_C(1) << 7)
 Auto-reload preload enable.
 
#define MCCI_STM32H7_TIM_CR1_CEN   (UINT32_C(1) << 0)
 Counter enable.
 
#define MCCI_STM32H7_TIM_CR1_CKD   (UINT32_C(0x3) << 8)
 Clock division.
 
#define MCCI_STM32H7_TIM_CR1_CKD_N(n)   ((n) << 8)
 
#define MCCI_STM32H7_TIM_CR1_CMS   (UINT32_C(0x3) << 5)
 Center-aligned mode selection.
 
#define MCCI_STM32H7_TIM_CR1_CMS_N(n)   ((n) << 5)
 
#define MCCI_STM32H7_TIM_CR1_DIR   (UINT32_C(1) << 4)
 Direction.
 
#define MCCI_STM32H7_TIM_CR1_OPM   (UINT32_C(1) << 3)
 One pulse mode.
 
#define MCCI_STM32H7_TIM_CR1_RSV10   (UINT32_C(1) << 10)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_CR1_RSV12   UINT32_C(0xFFFFF000)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_CR1_UDIS   (UINT32_C(1) << 1)
 Update disable.
 
#define MCCI_STM32H7_TIM_CR1_UIFREMAP   (UINT32_C(1) << 11)
 UIF status bit remapping.
 
#define MCCI_STM32H7_TIM_CR1_URS   (UINT32_C(1) << 2)
 Update request source.
 
TIM_CR2 bits
#define MCCI_STM32H7_TIM_CR2_CCDS   (UINT32_C(1) << 3)
 Capture/compare DMA selection.
 
#define MCCI_STM32H7_TIM_CR2_CCPC   (UINT32_C(1) << 0)
 Capture/compare preloaded control.
 
#define MCCI_STM32H7_TIM_CR2_CCUS   (UINT32_C(1) << 2)
 Capture/compare control update selection.
 
#define MCCI_STM32H7_TIM_CR2_MMS   (UINT32_C(0x7) << 4)
 Master mode selection.
 
#define MCCI_STM32H7_TIM_CR2_MMS2   (UINT32_C(0xF) << 20)
 Master mode selection 2.
 
#define MCCI_STM32H7_TIM_CR2_MMS2_N(n)   ((n) << 20)
 
#define MCCI_STM32H7_TIM_CR2_MMS_N(n)   ((n) << 4)
 
#define MCCI_STM32H7_TIM_CR2_OIS1   (UINT32_C(1) << 8)
 Output Idle state 1 (OC1 output)
 
#define MCCI_STM32H7_TIM_CR2_OIS1N   (UINT32_C(1) << 9)
 Output Idle state 1 (OC1N output)
 
#define MCCI_STM32H7_TIM_CR2_OIS2   (UINT32_C(1) << 10)
 Output Idle state 2 (OC2 output)
 
#define MCCI_STM32H7_TIM_CR2_OIS2N   (UINT32_C(1) << 11)
 Output Idle state 2 (OC2N output)
 
#define MCCI_STM32H7_TIM_CR2_OIS3   (UINT32_C(1) << 12)
 Output Idle state 3 (OC3 output)
 
#define MCCI_STM32H7_TIM_CR2_OIS3N   (UINT32_C(1) << 13)
 Output Idle state 3 (OC3N output)
 
#define MCCI_STM32H7_TIM_CR2_OIS4   (UINT32_C(1) << 14)
 Output Idle state 4 (OC4 output)
 
#define MCCI_STM32H7_TIM_CR2_OIS5   (UINT32_C(1) << 16)
 Output Idle state 5 (OC5 output)
 
#define MCCI_STM32H7_TIM_CR2_OIS6   (UINT32_C(1) << 18)
 Output Idle state 6 (OC6 output)
 
#define MCCI_STM32H7_TIM_CR2_RSV1   (UINT32_C(1) << 1)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_CR2_RSV15   (UINT32_C(1) << 15)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_CR2_RSV17   (UINT32_C(1) << 17)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_CR2_RSV19   (UINT32_C(1) << 19)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_CR2_RSV24   UINT32_C(0xFF000000)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_CR2_TI1S   (UINT32_C(1) << 7)
 TI1 selection.
 
TIM_SMCR bits
#define MCCI_STM32H7_TIM_SMCR_ECE   (UINT32_C(1) << 14)
 External clock enable.
 
#define MCCI_STM32H7_TIM_SMCR_ETF   (UINT32_C(0xF) << 8)
 External trigger filter.
 
#define MCCI_STM32H7_TIM_SMCR_ETF_N(n)   ((n) << 8)
 
#define MCCI_STM32H7_TIM_SMCR_ETP   (UINT32_C(1) << 15)
 External trigger polarity.
 
#define MCCI_STM32H7_TIM_SMCR_ETPS   (UINT32_C(0x3) << 12)
 External trigger prescaler.
 
#define MCCI_STM32H7_TIM_SMCR_ETPS_N(n)   ((n) << 12)
 
#define MCCI_STM32H7_TIM_SMCR_MSM   (UINT32_C(1) << 7)
 Master/slave mode.
 
#define MCCI_STM32H7_TIM_SMCR_RSV17   (UINT32_C(7) << 17)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_SMCR_RSV22   UINT32_C(0xFFC00000)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_SMCR_RSV3   (UINT32_C(1) << 3)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_SMCR_SMS   (MCCI_STM32H7_TIM_SMCR_SMS3 | MCCI_STM32H7_TIM_SMCR_SMS0)
 Trigger selection.
 
#define MCCI_STM32H7_TIM_SMCR_SMS0   (UINT32_C(0x7) << 0)
 Slave mode selection.
 
#define MCCI_STM32H7_TIM_SMCR_SMS0_N(n)   ((n) << 0)
 
#define MCCI_STM32H7_TIM_SMCR_SMS3   (UINT32_C(1) << 16)
 Slave mode selection.
 
#define MCCI_STM32H7_TIM_SMCR_SMS_N(n)   ((((n) >> 3) << 16) | MCCI_STM32H7_TIM_SMCR_SMS0_N((n) & UINT32_C(0x7)))
 
#define MCCI_STM32H7_TIM_SMCR_TS   (MCCI_STM32H7_TIM_SMCR_TS3 | MCCI_STM32H7_TIM_SMCR_TS0)
 Trigger selection.
 
#define MCCI_STM32H7_TIM_SMCR_TS0   (UINT32_C(0x7) << 4)
 Trigger selection.
 
#define MCCI_STM32H7_TIM_SMCR_TS0_N(n)   ((n) << 4)
 
#define MCCI_STM32H7_TIM_SMCR_TS3   (UINT32_C(0x3) << 20)
 Trigger selection.
 
#define MCCI_STM32H7_TIM_SMCR_TS3_N(n)   ((n) << 20)
 
#define MCCI_STM32H7_TIM_SMCR_TS_N(n)   (MCCI_STM32H7_TIM_SMCR_TS3_N((n) >> 3) | MCCI_STM32H7_TIM_SMCR_TS0_N((n) & UINT32_C(0x7)))
 
TIM_DIER bits
#define MCCI_STM32H7_TIM_DIER_BIE   (UINT32_C(1) << 7)
 Break interrupt enable.
 
#define MCCI_STM32H7_TIM_DIER_CC1DE   (UINT32_C(1) << 9)
 Capture/Compare 1 DMA request enable.
 
#define MCCI_STM32H7_TIM_DIER_CC1IE   (UINT32_C(1) << 1)
 Capture/Compare 1 interrupt enable.
 
#define MCCI_STM32H7_TIM_DIER_CC2DE   (UINT32_C(1) << 10)
 Capture/Compare 2 DMA request enable.
 
#define MCCI_STM32H7_TIM_DIER_CC2IE   (UINT32_C(1) << 2)
 Capture/Compare 2 interrupt enable.
 
#define MCCI_STM32H7_TIM_DIER_CC3DE   (UINT32_C(1) << 11)
 Capture/Compare 3 DMA request enable.
 
#define MCCI_STM32H7_TIM_DIER_CC3IE   (UINT32_C(1) << 3)
 Capture/Compare 3 interrupt enable.
 
#define MCCI_STM32H7_TIM_DIER_CC4DE   (UINT32_C(1) << 12)
 Capture/Compare 4 DMA request enable.
 
#define MCCI_STM32H7_TIM_DIER_CC4IE   (UINT32_C(1) << 4)
 Capture/Compare 4 interrupt enable.
 
#define MCCI_STM32H7_TIM_DIER_COMDE   (UINT32_C(1) << 13)
 COM DMA request enable.
 
#define MCCI_STM32H7_TIM_DIER_COMIE   (UINT32_C(1) << 5)
 COM interrupt enable.
 
#define MCCI_STM32H7_TIM_DIER_RSV15   UINT32_C(0xFFFF8000)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_DIER_TDE   (UINT32_C(1) << 14)
 Trigger DMA request enable.
 
#define MCCI_STM32H7_TIM_DIER_TIE   (UINT32_C(1) << 6)
 Trigger interrupt enable.
 
#define MCCI_STM32H7_TIM_DIER_UDE   (UINT32_C(1) << 8)
 Update DMA request enable.
 
#define MCCI_STM32H7_TIM_DIER_UIE   (UINT32_C(1) << 0)
 Update interrupt enable.
 
TIM_SR bits
#define MCCI_STM32H7_TIM_SR_B2IF   (UINT32_C(1) << 8)
 Break 2 interrupt flag.
 
#define MCCI_STM32H7_TIM_SR_BIF   (UINT32_C(1) << 7)
 Break interrupt flag.
 
#define MCCI_STM32H7_TIM_SR_CC1IF   (UINT32_C(1) << 1)
 Capture/Compare 1 interrupt flag.
 
#define MCCI_STM32H7_TIM_SR_CC1OF   (UINT32_C(1) << 9)
 Capture/Compare 1 overcapture flag.
 
#define MCCI_STM32H7_TIM_SR_CC2IF   (UINT32_C(1) << 2)
 Capture/Compare 2 interrupt flag.
 
#define MCCI_STM32H7_TIM_SR_CC2OF   (UINT32_C(1) << 10)
 Capture/Compare 2 overcapture flag.
 
#define MCCI_STM32H7_TIM_SR_CC3IF   (UINT32_C(1) << 3)
 Capture/Compare 3 interrupt flag.
 
#define MCCI_STM32H7_TIM_SR_CC3OF   (UINT32_C(1) << 11)
 Capture/Compare 3 overcapture flag.
 
#define MCCI_STM32H7_TIM_SR_CC4IF   (UINT32_C(1) << 4)
 Capture/Compare 4 interrupt flag.
 
#define MCCI_STM32H7_TIM_SR_CC4OF   (UINT32_C(1) << 12)
 Capture/Compare 4 overcapture flag.
 
#define MCCI_STM32H7_TIM_SR_CC5IF   (UINT32_C(1) << 16)
 Compare 5 interrupt flag.
 
#define MCCI_STM32H7_TIM_SR_CC6IF   (UINT32_C(1) << 17)
 Compare 6 interrupt flag.
 
#define MCCI_STM32H7_TIM_SR_COMIF   (UINT32_C(1) << 5)
 COM interrupt flag.
 
#define MCCI_STM32H7_TIM_SR_RSV14   (UINT32_C(3) << 14)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_SR_RSV18   UINT32_C(0xFFFC0000)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_SR_SBIF   (UINT32_C(1) << 13)
 System Break interrupt flag.
 
#define MCCI_STM32H7_TIM_SR_TIF   (UINT32_C(1) << 6)
 Trigger interrupt flag.
 
#define MCCI_STM32H7_TIM_SR_UIF   (UINT32_C(1) << 0)
 Update interrupt flag.
 
TIM_EGR bits
#define MCCI_STM32H7_TIM_EGR_B2G   (UINT32_C(1) << 8)
 Break 2 generation.
 
#define MCCI_STM32H7_TIM_EGR_BG   (UINT32_C(1) << 7)
 Break generation.
 
#define MCCI_STM32H7_TIM_EGR_CC1G   (UINT32_C(1) << 1)
 Capture/Compare 1 generation.
 
#define MCCI_STM32H7_TIM_EGR_CC2G   (UINT32_C(1) << 2)
 Capture/Compare 2 generation.
 
#define MCCI_STM32H7_TIM_EGR_CC3G   (UINT32_C(1) << 3)
 Capture/Compare 3 generation.
 
#define MCCI_STM32H7_TIM_EGR_CC4G   (UINT32_C(1) << 4)
 Capture/Compare 4 generation.
 
#define MCCI_STM32H7_TIM_EGR_COMG   (UINT32_C(1) << 5)
 COM generation.
 
#define MCCI_STM32H7_TIM_EGR_RSV8   UINT32_C(0xFFFFFE00)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_EGR_TG   (UINT32_C(1) << 6)
 Trigger generation.
 
#define MCCI_STM32H7_TIM_EGR_UG   (UINT32_C(1) << 0)
 Update generation.
 
TIM_CNT bits
#define MCCI_STM32H7_TIM_CNT_CNT   (UINT32_C(0xFFFF) << 0)
 Counter value.
 
#define MCCI_STM32H7_TIM_CNT_RSV16   UINT32_C(0x7FFF0000)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_CNT_UIFCPY   (UINT32_C(1) << 8)
 UIF copy.
 
TIM_PSC bits
#define MCCI_STM32H7_TIM_PSC_PSC   (UINT32_C(0xFFFF) << 0)
 Prescaler value.
 
#define MCCI_STM32H7_TIM_PSC_RSV16   UINT32_C(0xFFFF0000)
 reserved, don't change
 
TIM_ARR bits
#define MCCI_STM32H7_TIM_ARR_ARR   (UINT32_C(0xFFFF) << 0)
 Auto-reload value.
 
#define MCCI_STM32H7_TIM_ARR_RSV16   UINT32_C(0xFFFF0000)
 reserved, don't change
 
TIM_RCR bits
#define MCCI_STM32H7_TIM_RCR_REP   (UINT32_C(0xFFFF) << 0)
 Repetition counter value.
 
#define MCCI_STM32H7_TIM_RCR_RSV16   UINT32_C(0xFFFF0000)
 reserved, don't change
 
TIM_CCRx bits
#define MCCI_STM32H7_TIM_CCR_CCR   (UINT32_C(0xFFFF) << 0)
 Capture/Compare value.
 
#define MCCI_STM32H7_TIM_CCR_RSV16   UINT32_C(0xFFFF0000)
 reserved, don't change
 
TIM_AF1 bits
#define MCCI_STM32H7_TIM_AF1_BKCMP1E   (UINT32_C(1) << 1)
 BRK COMP1 enable.
 
#define MCCI_STM32H7_TIM_AF1_BKCMP1P   (UINT32_C(1) << 10)
 BRK COMP1 input polarity.
 
#define MCCI_STM32H7_TIM_AF1_BKCMP2E   (UINT32_C(1) << 2)
 BRK COMP2 enable.
 
#define MCCI_STM32H7_TIM_AF1_BKCMP2P   (UINT32_C(1) << 11)
 BRK COMP2 input polarity.
 
#define MCCI_STM32H7_TIM_AF1_BKDF1BK2E   (UINT32_C(1) << 8)
 BRK dfsdm1_break[2] enable.
 
#define MCCI_STM32H7_TIM_AF1_BKINE   (UINT32_C(1) << 0)
 BRK BKIN input enable.
 
#define MCCI_STM32H7_TIM_AF1_BKINP   (UINT32_C(1) << 9)
 BRK BKIN input polarity.
 
#define MCCI_STM32H7_TIM_AF1_ETRSEL   (UINT32_C(0xF) << 14)
 ETR source selection.
 
#define MCCI_STM32H7_TIM_AF1_ETRSEL_N(n)   ((n) << 14)
 
#define MCCI_STM32H7_TIM_AF1_RSV12   (UINT32_C(3) << 12)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_AF1_RSV18   UINT32_C(0xFFFC0000)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_AF1_RSV3   (UINT32_C(0x1F) << 3)
 reserved, don't change
 
TIM_AF2 bits
#define MCCI_STM32H7_TIM_AF2_BKCMP1E   (UINT32_C(1) << 1)
 BRK COMP1 enable.
 
#define MCCI_STM32H7_TIM_AF2_BKCMP1P   (UINT32_C(1) << 10)
 BRK COMP1 input polarity.
 
#define MCCI_STM32H7_TIM_AF2_BKCMP2E   (UINT32_C(1) << 2)
 BRK COMP2 enable.
 
#define MCCI_STM32H7_TIM_AF2_BKCMP2P   (UINT32_C(1) << 11)
 BRK COMP2 input polarity.
 
#define MCCI_STM32H7_TIM_AF2_BKDF1BK2E   (UINT32_C(1) << 8)
 BRK dfsdm1_break[2] enable.
 
#define MCCI_STM32H7_TIM_AF2_BKINE   (UINT32_C(1) << 0)
 BRK BKIN input enable.
 
#define MCCI_STM32H7_TIM_AF2_BKINP   (UINT32_C(1) << 9)
 BRK BKIN input polarity.
 
#define MCCI_STM32H7_TIM_AF2_RSV12   UINT32_C(0xFFFFF000)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_AF2_RSV3   (UINT32_C(0x1F) << 3)
 reserved, don't change
 
TIM_TISEL bits
#define MCCI_STM32H7_TIM_TISEL_RSV12   (UINT32_C(0xF) << 12)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_TISEL_RSV20   (UINT32_C(0xF) << 20)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_TISEL_RSV28   (UINT32_C(0xF) << 28)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_TISEL_RSV4   (UINT32_C(0xF) << 4)
 reserved, don't change
 
#define MCCI_STM32H7_TIM_TISEL_TI1SEL   (UINT32_C(0xF) << 0)
 selects TI1[0] to TI1[15] input
 
#define MCCI_STM32H7_TIM_TISEL_TI1SEL_N(n)   ((n) << 0)
 
#define MCCI_STM32H7_TIM_TISEL_TI2SEL   (UINT32_C(0xF) << 8)
 selects TI2[0] to TI2[15] input
 
#define MCCI_STM32H7_TIM_TISEL_TI2SEL_N(n)   ((n) << 8)
 
#define MCCI_STM32H7_TIM_TISEL_TI3SEL   (UINT32_C(0xF) << 16)
 selects TI3[0] to TI3[15] input
 
#define MCCI_STM32H7_TIM_TISEL_TI3SEL_N(n)   ((n) << 16)
 
#define MCCI_STM32H7_TIM_TISEL_TI4SEL   (UINT32_C(0xF) << 24)
 selects TI4[0] to TI4[15] input
 
#define MCCI_STM32H7_TIM_TISEL_TI4SEL_N(n)   ((n) << 24)
 
STM32Hxx interrupt numbers
#define MCCI_STM32H7_IRQ_ADC   UINT32_C(18)
 ADC1 and ADC2 global Interrupts.
 
#define MCCI_STM32H7_IRQ_BDMA1   UINT32_C(154)
 BDMA1 for DFSM global interrupt.
 
#define MCCI_STM32H7_IRQ_BDMA2_Channel0   UINT32_C(129)
 BDMA2 Channel 0 global Interrupt.
 
#define MCCI_STM32H7_IRQ_BDMA2_Channel1   UINT32_C(130)
 BDMA2 Channel 1 global Interrupt.
 
#define MCCI_STM32H7_IRQ_BDMA2_Channel2   UINT32_C(131)
 BDMA2 Channel 2 global Interrupt.
 
#define MCCI_STM32H7_IRQ_BDMA2_Channel3   UINT32_C(132)
 BDMA2 Channel 3 global Interrupt.
 
#define MCCI_STM32H7_IRQ_BDMA2_Channel4   UINT32_C(133)
 BDMA2 Channel 4 global Interrupt.
 
#define MCCI_STM32H7_IRQ_BDMA2_Channel5   UINT32_C(134)
 BDMA2 Channel 5 global Interrupt.
 
#define MCCI_STM32H7_IRQ_BDMA2_Channel6   UINT32_C(135)
 BDMA2 Channel 6 global Interrupt.
 
#define MCCI_STM32H7_IRQ_BDMA2_Channel7   UINT32_C(136)
 BDMA2 Channel 7 global Interrupt.
 
#define MCCI_STM32H7_IRQ_CEC   UINT32_C(94)
 HDMI-CEC global Interrupt.
 
#define MCCI_STM32H7_IRQ_COMP   UINT32_C(137)
 COMP global Interrupt.
 
#define MCCI_STM32H7_IRQ_CRS   UINT32_C(144)
 Clock Recovery Global Interrupt.
 
#define MCCI_STM32H7_IRQ_CRYP   UINT32_C(79)
 CRYP crypto global interrupt.
 
#define MCCI_STM32H7_IRQ_DAC2   UINT32_C(127)
 DAC2 global Interrupt.
 
#define MCCI_STM32H7_IRQ_DCMI_PSSI   UINT32_C(78)
 DCMI and PSSI global interrupt.
 
#define MCCI_STM32H7_IRQ_DFSDM1_FLT0   UINT32_C(110)
 DFSDM Filter1 Interrupt.
 
#define MCCI_STM32H7_IRQ_DFSDM1_FLT1   UINT32_C(111)
 DFSDM Filter2 Interrupt.
 
#define MCCI_STM32H7_IRQ_DFSDM1_FLT2   UINT32_C(112)
 DFSDM Filter3 Interrupt.
 
#define MCCI_STM32H7_IRQ_DFSDM1_FLT3   UINT32_C(113)
 DFSDM Filter4 Interrupt.
 
#define MCCI_STM32H7_IRQ_DFSDM1_FLT4   UINT32_C(64)
 DFSDM Filter4 Interrupt.
 
#define MCCI_STM32H7_IRQ_DFSDM1_FLT5   UINT32_C(65)
 DFSDM Filter5 Interrupt.
 
#define MCCI_STM32H7_IRQ_DFSDM1_FLT6   UINT32_C(66)
 DFSDM Filter6 Interrupt.
 
#define MCCI_STM32H7_IRQ_DFSDM1_FLT7   UINT32_C(67)
 DFSDM Filter7 Interrupt.
 
#define MCCI_STM32H7_IRQ_DFSDM2   UINT32_C(42)
 DFSDM2 global Interrupt.
 
#define MCCI_STM32H7_IRQ_DMA1_Stream0   UINT32_C(11)
 DMA1 Stream 0 global Interrupt.
 
#define MCCI_STM32H7_IRQ_DMA1_Stream1   UINT32_C(12)
 DMA1 Stream 1 global Interrupt.
 
#define MCCI_STM32H7_IRQ_DMA1_Stream2   UINT32_C(13)
 DMA1 Stream 2 global Interrupt.
 
#define MCCI_STM32H7_IRQ_DMA1_Stream3   UINT32_C(14)
 DMA1 Stream 3 global Interrupt.
 
#define MCCI_STM32H7_IRQ_DMA1_Stream4   UINT32_C(15)
 DMA1 Stream 4 global Interrupt.
 
#define MCCI_STM32H7_IRQ_DMA1_Stream5   UINT32_C(16)
 DMA1 Stream 5 global Interrupt.
 
#define MCCI_STM32H7_IRQ_DMA1_Stream6   UINT32_C(17)
 DMA1 Stream 6 global Interrupt.
 
#define MCCI_STM32H7_IRQ_DMA1_Stream7   UINT32_C(47)
 DMA1 Stream7 Interrupt.
 
#define MCCI_STM32H7_IRQ_DMA2_Stream0   UINT32_C(56)
 DMA2 Stream 0 global Interrupt.
 
#define MCCI_STM32H7_IRQ_DMA2_Stream1   UINT32_C(57)
 DMA2 Stream 1 global Interrupt.
 
#define MCCI_STM32H7_IRQ_DMA2_Stream2   UINT32_C(58)
 DMA2 Stream 2 global Interrupt.
 
#define MCCI_STM32H7_IRQ_DMA2_Stream3   UINT32_C(59)
 DMA2 Stream 3 global Interrupt.
 
#define MCCI_STM32H7_IRQ_DMA2_Stream4   UINT32_C(60)
 DMA2 Stream 4 global Interrupt.
 
#define MCCI_STM32H7_IRQ_DMA2_Stream5   UINT32_C(68)
 DMA2 Stream 5 global interrupt.
 
#define MCCI_STM32H7_IRQ_DMA2_Stream6   UINT32_C(69)
 DMA2 Stream 6 global interrupt.
 
#define MCCI_STM32H7_IRQ_DMA2_Stream7   UINT32_C(70)
 DMA2 Stream 7 global interrupt.
 
#define MCCI_STM32H7_IRQ_DMA2D   UINT32_C(90)
 DMA2D global Interrupt.
 
#define MCCI_STM32H7_IRQ_DMAMUX1_OVR   UINT32_C(102)
 DMAMUX1 Overrun interrupt.
 
#define MCCI_STM32H7_IRQ_DMAMUX2_OVR   UINT32_C(128)
 DMAMUX2 Overrun interrupt.
 
#define MCCI_STM32H7_IRQ_DTS   UINT32_C(147)
 Digital Temperature Sensor Global Interrupt.
 
#define MCCI_STM32H7_IRQ_ECC   UINT32_C(145)
 ECC diagnostic Global Interrupt.
 
#define MCCI_STM32H7_IRQ_EXTI0   UINT32_C(6)
 EXTI Line0 Interrupt.
 
#define MCCI_STM32H7_IRQ_EXTI1   UINT32_C(7)
 EXTI Line1 Interrupt.
 
#define MCCI_STM32H7_IRQ_EXTI15_10   UINT32_C(40)
 External Line[15:10] Interrupts.
 
#define MCCI_STM32H7_IRQ_EXTI2   UINT32_C(8)
 EXTI Line2 Interrupt.
 
#define MCCI_STM32H7_IRQ_EXTI3   UINT32_C(9)
 EXTI Line3 Interrupt.
 
#define MCCI_STM32H7_IRQ_EXTI4   UINT32_C(10)
 EXTI Line4 Interrupt.
 
#define MCCI_STM32H7_IRQ_EXTI9_5   UINT32_C(23)
 External Line[9:5] Interrupts.
 
#define MCCI_STM32H7_IRQ_FDCAN1_IT0   UINT32_C(19)
 FDCAN1 Interrupt line 0.
 
#define MCCI_STM32H7_IRQ_FDCAN1_IT1   UINT32_C(21)
 FDCAN1 Interrupt line 1.
 
#define MCCI_STM32H7_IRQ_FDCAN2_IT0   UINT32_C(20)
 FDCAN2 Interrupt line 0.
 
#define MCCI_STM32H7_IRQ_FDCAN2_IT1   UINT32_C(22)
 FDCAN2 Interrupt line 1.
 
#define MCCI_STM32H7_IRQ_FDCAN_CAL   UINT32_C(63)
 FDCAN Calibration unit Interrupt.
 
#define MCCI_STM32H7_IRQ_FLASH   UINT32_C(4)
 FLASH global Interrupt.
 
#define MCCI_STM32H7_IRQ_FMC   UINT32_C(48)
 FMC global Interrupt.
 
#define MCCI_STM32H7_IRQ_FPU   UINT32_C(81)
 FPU global interrupt.
 
#define MCCI_STM32H7_IRQ_GFXMMU   UINT32_C(153)
 GFXMMU global interrupt.
 
#define MCCI_STM32H7_IRQ_HASH_RNG   UINT32_C(80)
 HASH and RNG global interrupt.
 
#define MCCI_STM32H7_IRQ_HSEM1   UINT32_C(125)
 HSEM1 global Interrupt.
 
#define MCCI_STM32H7_IRQ_I2C1_ER   UINT32_C(32)
 I2C1 Error Interrupt.
 
#define MCCI_STM32H7_IRQ_I2C1_EV   UINT32_C(31)
 I2C1 Event Interrupt.
 
#define MCCI_STM32H7_IRQ_I2C2_ER   UINT32_C(34)
 I2C2 Error Interrupt.
 
#define MCCI_STM32H7_IRQ_I2C2_EV   UINT32_C(33)
 I2C2 Event Interrupt.
 
#define MCCI_STM32H7_IRQ_I2C3_ER   UINT32_C(73)
 I2C3 error interrupt.
 
#define MCCI_STM32H7_IRQ_I2C3_EV   UINT32_C(72)
 I2C3 event interrupt.
 
#define MCCI_STM32H7_IRQ_I2C4_ER   UINT32_C(96)
 I2C4 Error Interrupt.
 
#define MCCI_STM32H7_IRQ_I2C4_EV   UINT32_C(95)
 I2C4 Event Interrupt.
 
#define MCCI_STM32H7_IRQ_JPEG   UINT32_C(121)
 JPEG global Interrupt.
 
#define MCCI_STM32H7_IRQ_LPTIM1   UINT32_C(93)
 LP TIM1 interrupt.
 
#define MCCI_STM32H7_IRQ_LPTIM2   UINT32_C(138)
 LP TIM2 global interrupt.
 
#define MCCI_STM32H7_IRQ_LPTIM3   UINT32_C(139)
 LP TIM3 global interrupt.
 
#define MCCI_STM32H7_IRQ_LPUART1   UINT32_C(142)
 LP UART1 interrupt.
 
#define MCCI_STM32H7_IRQ_LTDC   UINT32_C(88)
 LTDC global Interrupt.
 
#define MCCI_STM32H7_IRQ_LTDC_ER   UINT32_C(89)
 LTDC Error global Interrupt.
 
#define MCCI_STM32H7_IRQ_MDIOS   UINT32_C(120)
 MDIOS global Interrupt.
 
#define MCCI_STM32H7_IRQ_MDIOS_WKUP   UINT32_C(119)
 MDIOS Wakeup Interrupt.
 
#define MCCI_STM32H7_IRQ_MDMA   UINT32_C(122)
 MDMA global Interrupt.
 
#define MCCI_STM32H7_IRQ_OCTOSPI1   UINT32_C(92)
 OCTOSPI1 global interrupt.
 
#define MCCI_STM32H7_IRQ_OCTOSPI2   UINT32_C(150)
 OctoSPI2 global interrupt.
 
#define MCCI_STM32H7_IRQ_OTFDEC1   UINT32_C(151)
 OTFDEC1 global interrupt.
 
#define MCCI_STM32H7_IRQ_OTFDEC2   UINT32_C(152)
 OTFDEC2 global interrupt.
 
#define MCCI_STM32H7_IRQ_OTG_HS   UINT32_C(77)
 USB OTG HS global interrupt.
 
#define MCCI_STM32H7_IRQ_OTG_HS_EP1_IN   UINT32_C(75)
 USB OTG HS End Point 1 In global interrupt.
 
#define MCCI_STM32H7_IRQ_OTG_HS_EP1_OUT   UINT32_C(74)
 USB OTG HS End Point 1 Out global interrupt.
 
#define MCCI_STM32H7_IRQ_OTG_HS_WKUP   UINT32_C(76)
 USB OTG HS Wakeup through EXTI interrupt.
 
#define MCCI_STM32H7_IRQ_PVD_PVM   UINT32_C(1)
 PVD/PVM through EXTI Line detection Interrupt.
 
#define MCCI_STM32H7_IRQ_RCC   UINT32_C(5)
 RCC global Interrupt.
 
#define MCCI_STM32H7_IRQ_RTC_Alarm   UINT32_C(41)
 RTC Alarm (A and B) through EXTI Line Interrupt.
 
#define MCCI_STM32H7_IRQ_RTC_TAMP_STAMP_CSS_LSE   UINT32_C(2)
 Tamper, TimeStamp, CSS and LSE interrupts through the EXTI line.
 
#define MCCI_STM32H7_IRQ_RTC_WKUP   UINT32_C(3)
 RTC Wakeup interrupt through the EXTI line.
 
#define MCCI_STM32H7_IRQ_SAI1   UINT32_C(87)
 SAI1 global Interrupt.
 
#define MCCI_STM32H7_IRQ_SAI2   UINT32_C(91)
 SAI2 global Interrupt.
 
#define MCCI_STM32H7_IRQ_SDMMC1   UINT32_C(49)
 SDMMC1 global Interrupt.
 
#define MCCI_STM32H7_IRQ_SDMMC2   UINT32_C(124)
 SDMMC2 global Interrupt.
 
#define MCCI_STM32H7_IRQ_SPDIF_RX   UINT32_C(97)
 SPDIF-RX global Interrupt.
 
#define MCCI_STM32H7_IRQ_SPI1   UINT32_C(35)
 SPI1 global Interrupt.
 
#define MCCI_STM32H7_IRQ_SPI2   UINT32_C(36)
 SPI2 global Interrupt.
 
#define MCCI_STM32H7_IRQ_SPI3   UINT32_C(51)
 SPI3 global Interrupt.
 
#define MCCI_STM32H7_IRQ_SPI4   UINT32_C(84)
 SPI4 global Interrupt.
 
#define MCCI_STM32H7_IRQ_SPI5   UINT32_C(85)
 SPI5 global Interrupt.
 
#define MCCI_STM32H7_IRQ_SPI6   UINT32_C(86)
 SPI6 global Interrupt.
 
#define MCCI_STM32H7_IRQ_SWPMI1   UINT32_C(115)
 Serial Wire Interface 1 global interrupt.
 
#define MCCI_STM32H7_IRQ_TIM15   UINT32_C(116)
 TIM15 global Interrupt.
 
#define MCCI_STM32H7_IRQ_TIM16   UINT32_C(117)
 TIM16 global Interrupt.
 
#define MCCI_STM32H7_IRQ_TIM17   UINT32_C(118)
 TIM17 global Interrupt.
 
#define MCCI_STM32H7_IRQ_TIM1_BRK   UINT32_C(24)
 TIM1 Break Interrupt.
 
#define MCCI_STM32H7_IRQ_TIM1_CC   UINT32_C(27)
 TIM1 Capture Compare Interrupt.
 
#define MCCI_STM32H7_IRQ_TIM1_TRG_COM   UINT32_C(26)
 TIM1 Trigger and Commutation Interrupt.
 
#define MCCI_STM32H7_IRQ_TIM1_UP   UINT32_C(25)
 TIM1 Update Interrupt.
 
#define MCCI_STM32H7_IRQ_TIM2   UINT32_C(28)
 TIM2 global Interrupt.
 
#define MCCI_STM32H7_IRQ_TIM3   UINT32_C(29)
 TIM3 global Interrupt.
 
#define MCCI_STM32H7_IRQ_TIM4   UINT32_C(30)
 TIM4 global Interrupt.
 
#define MCCI_STM32H7_IRQ_TIM5   UINT32_C(50)
 TIM5 global Interrupt.
 
#define MCCI_STM32H7_IRQ_TIM6_DAC   UINT32_C(54)
 TIM6 global and DAC1&2 underrun error interrupts.
 
#define MCCI_STM32H7_IRQ_TIM7   UINT32_C(55)
 TIM7 global interrupt.
 
#define MCCI_STM32H7_IRQ_TIM8_BRK_TIM12   UINT32_C(43)
 TIM8 Break Interrupt and TIM12 global interrupt.
 
#define MCCI_STM32H7_IRQ_TIM8_CC   UINT32_C(46)
 TIM8 Capture Compare Interrupt.
 
#define MCCI_STM32H7_IRQ_TIM8_TRG_COM_TIM14   UINT32_C(45)
 TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt.
 
#define MCCI_STM32H7_IRQ_TIM8_UP_TIM13   UINT32_C(44)
 TIM8 Update Interrupt and TIM13 global interrupt.
 
#define MCCI_STM32H7_IRQ_UART4   UINT32_C(52)
 UART4 global Interrupt.
 
#define MCCI_STM32H7_IRQ_UART5   UINT32_C(53)
 UART5 global Interrupt.
 
#define MCCI_STM32H7_IRQ_UART7   UINT32_C(82)
 UART7 global interrupt.
 
#define MCCI_STM32H7_IRQ_UART8   UINT32_C(83)
 UART8 global interrupt.
 
#define MCCI_STM32H7_IRQ_UART9   UINT32_C(140)
 UART9 global interrupt.
 
#define MCCI_STM32H7_IRQ_USART1   UINT32_C(37)
 USART1 global Interrupt.
 
#define MCCI_STM32H7_IRQ_USART10   UINT32_C(141)
 USART10 global interrupt.
 
#define MCCI_STM32H7_IRQ_USART2   UINT32_C(38)
 USART2 global Interrupt.
 
#define MCCI_STM32H7_IRQ_USART3   UINT32_C(39)
 USART3 global Interrupt.
 
#define MCCI_STM32H7_IRQ_USART6   UINT32_C(71)
 USART6 global interrupt.
 
#define MCCI_STM32H7_IRQ_WAKEUP_PIN   UINT32_C(149)
 Interrupt for all 6 wake-up pins.
 
#define MCCI_STM32H7_IRQ_WWDG   UINT32_C(0)
 Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)
 
#define MCCI_STM32H7_IRQ_WWDG_RST   UINT32_C(143)
 Window Watchdog Event interrupt.
 

Macro Definition Documentation

◆ _mcci_stm32h7xx_h_

#define _mcci_stm32h7xx_h_   /* prevent multiple includes */

Definition at line 23 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR

#define MCCI_STM32H7_DCMI_CR   UINT32_C(0x00)

offset to DCMI control register

Definition at line 2499 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_BSM

#define MCCI_STM32H7_DCMI_CR_BSM   (UINT32_C(3) << 16)

Byte Select mode.

Definition at line 2518 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_BSM_N

#define MCCI_STM32H7_DCMI_CR_BSM_N (   n)    ((n) << 16)

Definition at line 2519 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_CAPTURE

#define MCCI_STM32H7_DCMI_CR_CAPTURE   (UINT32_C(1) << 0)

Capture enable.

Definition at line 2534 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_CM

#define MCCI_STM32H7_DCMI_CR_CM   (UINT32_C(1) << 1)

Capture mode.

Definition at line 2533 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_CROP

#define MCCI_STM32H7_DCMI_CR_CROP   (UINT32_C(1) << 2)

Crop feature.

Definition at line 2532 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_EDM

#define MCCI_STM32H7_DCMI_CR_EDM   (UINT32_C(3) << 10)

Extended data mode.

Definition at line 2523 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_EDM_N

#define MCCI_STM32H7_DCMI_CR_EDM_N (   n)    ((n) << 10)

Definition at line 2524 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_ENABLE

#define MCCI_STM32H7_DCMI_CR_ENABLE   (UINT32_C(1) << 14)

DCMI enable.

Definition at line 2521 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_ESS

#define MCCI_STM32H7_DCMI_CR_ESS   (UINT32_C(1) << 4)

Embedded synchronization select.

Definition at line 2530 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_FCRC

#define MCCI_STM32H7_DCMI_CR_FCRC   (UINT32_C(3) << 8)

Frame capture rate control.

Definition at line 2525 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_FCRC_N

#define MCCI_STM32H7_DCMI_CR_FCRC_N (   n)    ((n) << 8)

Definition at line 2526 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_HSPOL

#define MCCI_STM32H7_DCMI_CR_HSPOL   (UINT32_C(1) << 6)

Horizontal synchronization polarity.

Definition at line 2528 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_JPEG

#define MCCI_STM32H7_DCMI_CR_JPEG   (UINT32_C(1) << 3)

JPEG format.

Definition at line 2531 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_LSM

#define MCCI_STM32H7_DCMI_CR_LSM   (UINT32_C(1) << 19)

Line Select mode.

Definition at line 2516 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_OEBS

#define MCCI_STM32H7_DCMI_CR_OEBS   (UINT32_C(1) << 18)

Odd/Even Byte Select (Byte Select Start)

Definition at line 2517 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_OELS

#define MCCI_STM32H7_DCMI_CR_OELS   (UINT32_C(1) << 20)

Odd/Even Line Select (Line Select Start)

Definition at line 2515 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_PCKPOL

#define MCCI_STM32H7_DCMI_CR_PCKPOL   (UINT32_C(1) << 5)

Pixel clock polarity.

Definition at line 2529 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_RSV12

#define MCCI_STM32H7_DCMI_CR_RSV12   (UINT32_C(3) << 12)

reserved, don't change

Definition at line 2522 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_RSV15

#define MCCI_STM32H7_DCMI_CR_RSV15   (UINT32_C(1) << 15)

reserved, don't change

Definition at line 2520 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_RSV21

#define MCCI_STM32H7_DCMI_CR_RSV21   UINT32_C(0xFFE00000)

reserved, don't change

Definition at line 2514 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CR_VSPOL

#define MCCI_STM32H7_DCMI_CR_VSPOL   (UINT32_C(1) << 7)

Vertical synchronization polarity.

Definition at line 2527 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CWSIZE

#define MCCI_STM32H7_DCMI_CWSIZE   UINT32_C(0x24)

offset to DCMI crop window size

Definition at line 2508 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CWSIZE_CAPCNT

#define MCCI_STM32H7_DCMI_CWSIZE_CAPCNT   (UINT32_C(0x3FFF) << 0)

Capture count.

Definition at line 2625 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CWSIZE_CAPCNT_N

#define MCCI_STM32H7_DCMI_CWSIZE_CAPCNT_N (   n)    ((n) << 0)

Definition at line 2626 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CWSIZE_RSV14

#define MCCI_STM32H7_DCMI_CWSIZE_RSV14   (UINT32_C(3) << 14)

reserved, don't change

Definition at line 2624 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CWSIZE_RSV30

#define MCCI_STM32H7_DCMI_CWSIZE_RSV30   (UINT32_C(3) << 30)

reserved, don't change

Definition at line 2621 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CWSIZE_VLINE

#define MCCI_STM32H7_DCMI_CWSIZE_VLINE   (UINT32_C(0x3FFF) << 16)

Vertical line count.

Definition at line 2622 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CWSIZE_VLINE_N

#define MCCI_STM32H7_DCMI_CWSIZE_VLINE_N (   n)    ((n) << 16)

Definition at line 2623 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CWSTRT

#define MCCI_STM32H7_DCMI_CWSTRT   UINT32_C(0x20)

offset to DCMI crop window start

Definition at line 2507 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CWSTRT_HOFFCNT

#define MCCI_STM32H7_DCMI_CWSTRT_HOFFCNT   (UINT32_C(0x3FFF) << 0)

Horizontal offset count.

Definition at line 2615 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CWSTRT_HOFFCNT_N

#define MCCI_STM32H7_DCMI_CWSTRT_HOFFCNT_N (   n)    ((n) << 0)

Definition at line 2616 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CWSTRT_RSV14

#define MCCI_STM32H7_DCMI_CWSTRT_RSV14   (UINT32_C(3) << 14)

reserved, don't change

Definition at line 2614 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CWSTRT_RSV29

#define MCCI_STM32H7_DCMI_CWSTRT_RSV29   (UINT32_C(7) << 29)

reserved, don't change

Definition at line 2611 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CWSTRT_VST

#define MCCI_STM32H7_DCMI_CWSTRT_VST   (UINT32_C(0x1FFF) << 16)

Vertical start line count.

Definition at line 2612 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_CWSTRT_VST_N

#define MCCI_STM32H7_DCMI_CWSTRT_VST_N (   n)    ((n) << 16)

Definition at line 2613 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_DR

#define MCCI_STM32H7_DCMI_DR   UINT32_C(0x28)

offset to DCMI data register

Definition at line 2509 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ESCR

#define MCCI_STM32H7_DCMI_ESCR   UINT32_C(0x18)

offset to DCMI embedded synchronization code register

Definition at line 2505 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ESCR_FEC

#define MCCI_STM32H7_DCMI_ESCR_FEC   (UINT32_C(0xFF) << 24)

Frame end delimiter code.

Definition at line 2587 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ESCR_FEC_N

#define MCCI_STM32H7_DCMI_ESCR_FEC_N (   n)    ((n) << 24)

Definition at line 2588 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ESCR_FSC

#define MCCI_STM32H7_DCMI_ESCR_FSC   (UINT32_C(0xFF) << 0)

Frame start delimiter code.

Definition at line 2593 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ESCR_FSC_N

#define MCCI_STM32H7_DCMI_ESCR_FSC_N (   n)    ((n) << 0)

Definition at line 2594 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ESCR_LEC

#define MCCI_STM32H7_DCMI_ESCR_LEC   (UINT32_C(0xFF) << 16)

Line end delimiter code.

Definition at line 2589 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ESCR_LEC_N

#define MCCI_STM32H7_DCMI_ESCR_LEC_N (   n)    ((n) << 16)

Definition at line 2590 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ESCR_LSC

#define MCCI_STM32H7_DCMI_ESCR_LSC   (UINT32_C(0xFF) << 8)

Line start delimiter code.

Definition at line 2591 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ESCR_LSC_N

#define MCCI_STM32H7_DCMI_ESCR_LSC_N (   n)    ((n) << 8)

Definition at line 2592 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ESUR

#define MCCI_STM32H7_DCMI_ESUR   UINT32_C(0x1C)

offset to DCMI embedded synchronization unmask register

Definition at line 2506 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ESUR_FEU

#define MCCI_STM32H7_DCMI_ESUR_FEU   (UINT32_C(0xFF) << 24)

Frame end delimiter unmask.

Definition at line 2599 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ESUR_FEU_N

#define MCCI_STM32H7_DCMI_ESUR_FEU_N (   n)    ((n) << 24)

Definition at line 2600 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ESUR_FSU

#define MCCI_STM32H7_DCMI_ESUR_FSU   (UINT32_C(0xFF) << 0)

Frame start delimiter unmask.

Definition at line 2605 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ESUR_FSU_N

#define MCCI_STM32H7_DCMI_ESUR_FSU_N (   n)    ((n) << 0)

Definition at line 2606 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ESUR_LEU

#define MCCI_STM32H7_DCMI_ESUR_LEU   (UINT32_C(0xFF) << 16)

Line end delimiter unmask.

Definition at line 2601 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ESUR_LEU_N

#define MCCI_STM32H7_DCMI_ESUR_LEU_N (   n)    ((n) << 16)

Definition at line 2602 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ESUR_LSU

#define MCCI_STM32H7_DCMI_ESUR_LSU   (UINT32_C(0xFF) << 8)

Line start delimiter unmask.

Definition at line 2603 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ESUR_LSU_N

#define MCCI_STM32H7_DCMI_ESUR_LSU_N (   n)    ((n) << 8)

Definition at line 2604 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ICR

#define MCCI_STM32H7_DCMI_ICR   UINT32_C(0x14)

offset to DCMI interrupt clear register

Definition at line 2504 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ICR_ERR

#define MCCI_STM32H7_DCMI_ICR_ERR   (UINT32_C(1) << 2)

Synchronization raw interrupt status clear.

Definition at line 2580 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ICR_FRAME

#define MCCI_STM32H7_DCMI_ICR_FRAME   (UINT32_C(1) << 0)

Capture complete interrupt status clear.

Definition at line 2582 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ICR_LINE

#define MCCI_STM32H7_DCMI_ICR_LINE   (UINT32_C(1) << 4)

Line interrupt status clear.

Definition at line 2578 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ICR_OVR

#define MCCI_STM32H7_DCMI_ICR_OVR   (UINT32_C(1) << 1)

Overrun interrupt status clear.

Definition at line 2581 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ICR_RSV5

#define MCCI_STM32H7_DCMI_ICR_RSV5   UINT32_C(0xFFFFFFE0)

reserved, don't change

Definition at line 2577 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_ICR_VSYNC

#define MCCI_STM32H7_DCMI_ICR_VSYNC   (UINT32_C(1) << 3)

DCMI_VSYNC interrupt status clear.

Definition at line 2579 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_IER

#define MCCI_STM32H7_DCMI_IER   UINT32_C(0x0C)

offset to DCMI interrupt enable register

Definition at line 2502 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_IER_ERR

#define MCCI_STM32H7_DCMI_IER_ERR   (UINT32_C(1) << 2)

Synchronization interrupt enable.

Definition at line 2560 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_IER_FRAME

#define MCCI_STM32H7_DCMI_IER_FRAME   (UINT32_C(1) << 0)

Capture complete interrupt enable.

Definition at line 2562 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_IER_LINE

#define MCCI_STM32H7_DCMI_IER_LINE   (UINT32_C(1) << 4)

Line interrupt enable.

Definition at line 2558 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_IER_OVR

#define MCCI_STM32H7_DCMI_IER_OVR   (UINT32_C(1) << 1)

Overrun interrupt enable.

Definition at line 2561 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_IER_RSV5

#define MCCI_STM32H7_DCMI_IER_RSV5   UINT32_C(0xFFFFFFE0)

reserved, don't change

Definition at line 2557 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_IER_VSYNC

#define MCCI_STM32H7_DCMI_IER_VSYNC   (UINT32_C(1) << 3)

DCMI_VSYNC interrupt enable.

Definition at line 2559 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_MIS

#define MCCI_STM32H7_DCMI_MIS   UINT32_C(0x10)

offset to DCMI masked interrupt status register

Definition at line 2503 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_MIS_ERR

#define MCCI_STM32H7_DCMI_MIS_ERR   (UINT32_C(1) << 2)

Synchronization maskedinterrupt status.

Definition at line 2570 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_MIS_FRAME

#define MCCI_STM32H7_DCMI_MIS_FRAME   (UINT32_C(1) << 0)

Capture complete maskedinterrupt status.

Definition at line 2572 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_MIS_LINE

#define MCCI_STM32H7_DCMI_MIS_LINE   (UINT32_C(1) << 4)

Line maskedinterrupt status.

Definition at line 2568 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_MIS_OVR

#define MCCI_STM32H7_DCMI_MIS_OVR   (UINT32_C(1) << 1)

Overrun maskedinterrupt status.

Definition at line 2571 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_MIS_RSV5

#define MCCI_STM32H7_DCMI_MIS_RSV5   UINT32_C(0xFFFFFFE0)

reserved, don't change

Definition at line 2567 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_MIS_VSYNC

#define MCCI_STM32H7_DCMI_MIS_VSYNC   (UINT32_C(1) << 3)

DCMI_VSYNC maskedinterrupt status.

Definition at line 2569 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_RIS

#define MCCI_STM32H7_DCMI_RIS   UINT32_C(0x08)

offset to DCMI raw interrupt status register

Definition at line 2501 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_RIS_ERR

#define MCCI_STM32H7_DCMI_RIS_ERR   (UINT32_C(1) << 2)

Synchronization error raw interrupt status.

Definition at line 2550 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_RIS_FRAME

#define MCCI_STM32H7_DCMI_RIS_FRAME   (UINT32_C(1) << 0)

Capture complete raw interrupt status.

Definition at line 2552 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_RIS_LINE

#define MCCI_STM32H7_DCMI_RIS_LINE   (UINT32_C(1) << 4)

Line raw interrupt status.

Definition at line 2548 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_RIS_OVR

#define MCCI_STM32H7_DCMI_RIS_OVR   (UINT32_C(1) << 1)

Overrun raw interrupt status.

Definition at line 2551 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_RIS_RSV5

#define MCCI_STM32H7_DCMI_RIS_RSV5   UINT32_C(0xFFFFFFE0)

reserved, don't change

Definition at line 2547 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_RIS_VSYNC

#define MCCI_STM32H7_DCMI_RIS_VSYNC   (UINT32_C(1) << 3)

DCMI_VSYNC raw interrupt status.

Definition at line 2549 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_SR

#define MCCI_STM32H7_DCMI_SR   UINT32_C(0x04)

offset to DCMI status register

Definition at line 2500 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_SR_FNE

#define MCCI_STM32H7_DCMI_SR_FNE   (UINT32_C(1) << 2)

FIFO not empty.

Definition at line 2540 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_SR_HSYNC

#define MCCI_STM32H7_DCMI_SR_HSYNC   (UINT32_C(1) << 0)

Horizontal synchronization.

Definition at line 2542 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_SR_RSV3

#define MCCI_STM32H7_DCMI_SR_RSV3   UINT32_C(0xFFFFFFF8)

reserved, don't change

Definition at line 2539 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DCMI_SR_VSYNC

#define MCCI_STM32H7_DCMI_SR_VSYNC   (UINT32_C(1) << 1)

Vertical synchronization.

Definition at line 2541 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA1_STREAM_BASE

#define MCCI_STM32H7_DMA1_STREAM_BASE (   x)     (MCCI_STM32H7_REG_DMA1 + MCCI_STM32H7_DMA_STREAM_BASE(x))

Definition at line 2234 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA2_STREAM_BASE

#define MCCI_STM32H7_DMA2_STREAM_BASE (   x)     (MCCI_STM32H7_REG_DMA2 + MCCI_STM32H7_DMA_STREAM_BASE(x))

Definition at line 2236 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_GET_STREAM

#define MCCI_STM32H7_DMA_GET_STREAM (   b)    ((((b) & UINT32_C(0xFF)) - UINT32_C(0x10)) / UINT32_C(0x18))

Definition at line 2239 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_HIFCR

#define MCCI_STM32H7_DMA_HIFCR   UINT32_C(0x0C)

offset to DMA high interrupt flag clear register

Definition at line 2214 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_HISR

#define MCCI_STM32H7_DMA_HISR   UINT32_C(0x04)

offset to DMA high interrupt status register

Definition at line 2212 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_DMEIF

#define MCCI_STM32H7_DMA_ISR_DMEIF   (UINT32_C(1) << 2)

direct mode error interrupt flag

Definition at line 2274 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_DMEIF0

#define MCCI_STM32H7_DMA_ISR_DMEIF0   (UINT32_C(1) << 2)

direct mode error interrupt flag

Definition at line 2267 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_DMEIF1

#define MCCI_STM32H7_DMA_ISR_DMEIF1   (UINT32_C(1) << 8)

direct mode error interrupt flag

Definition at line 2261 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_DMEIF2

#define MCCI_STM32H7_DMA_ISR_DMEIF2   (UINT32_C(1) << 18)

direct mode error interrupt flag

Definition at line 2254 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_DMEIF3

#define MCCI_STM32H7_DMA_ISR_DMEIF3   (UINT32_C(1) << 24)

direct mode error interrupt flag

Definition at line 2248 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_FEIF

#define MCCI_STM32H7_DMA_ISR_FEIF   (UINT32_C(1) << 0)

FIFO error interrupt flag.

Definition at line 2275 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_FEIF0

#define MCCI_STM32H7_DMA_ISR_FEIF0   (UINT32_C(1) << 0)

FIFO error interrupt flag.

Definition at line 2269 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_FEIF1

#define MCCI_STM32H7_DMA_ISR_FEIF1   (UINT32_C(1) << 6)

FIFO error interrupt flag.

Definition at line 2263 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_FEIF2

#define MCCI_STM32H7_DMA_ISR_FEIF2   (UINT32_C(1) << 16)

FIFO error interrupt flag.

Definition at line 2256 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_FEIF3

#define MCCI_STM32H7_DMA_ISR_FEIF3   (UINT32_C(1) << 22)

FIFO error interrupt flag.

Definition at line 2250 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_HTIF

#define MCCI_STM32H7_DMA_ISR_HTIF   (UINT32_C(1) << 4)

half transfer interrupt flag

Definition at line 2272 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_HTIF0

#define MCCI_STM32H7_DMA_ISR_HTIF0   (UINT32_C(1) << 4)

half transfer interrupt flag

Definition at line 2265 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_HTIF1

#define MCCI_STM32H7_DMA_ISR_HTIF1   (UINT32_C(1) << 10)

half transfer interrupt flag

Definition at line 2259 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_HTIF2

#define MCCI_STM32H7_DMA_ISR_HTIF2   (UINT32_C(1) << 20)

half transfer interrupt flag

Definition at line 2252 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_HTIF3

#define MCCI_STM32H7_DMA_ISR_HTIF3   (UINT32_C(1) << 26)

half transfer interrupt flag

Definition at line 2246 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_MASK

#define MCCI_STM32H7_DMA_ISR_MASK   UINT32_C(0x3D)

ISR stream mask.

Definition at line 2276 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_RSV1

#define MCCI_STM32H7_DMA_ISR_RSV1   (UINT32_C(1) << 1)

reserved, don't change

Definition at line 2268 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_RSV12

#define MCCI_STM32H7_DMA_ISR_RSV12   UINT32_C(0x0000F000)

reserved, don't change

Definition at line 2257 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_RSV17

#define MCCI_STM32H7_DMA_ISR_RSV17   (UINT32_C(1) << 17)

reserved, don't change

Definition at line 2255 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_RSV23

#define MCCI_STM32H7_DMA_ISR_RSV23   (UINT32_C(1) << 23)

reserved, don't change

Definition at line 2249 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_RSV28

#define MCCI_STM32H7_DMA_ISR_RSV28   UINT32_C(0xF0000000)

reserved, don't change

Definition at line 2244 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_RSV7

#define MCCI_STM32H7_DMA_ISR_RSV7   (UINT32_C(1) << 7)

reserved, don't change

Definition at line 2262 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_TCIF

#define MCCI_STM32H7_DMA_ISR_TCIF   (UINT32_C(1) << 5)

transfer complete interrupt flag

Definition at line 2271 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_TCIF0

#define MCCI_STM32H7_DMA_ISR_TCIF0   (UINT32_C(1) << 5)

transfer complete interrupt flag

Definition at line 2264 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_TCIF1

#define MCCI_STM32H7_DMA_ISR_TCIF1   (UINT32_C(1) << 11)

transfer complete interrupt flag

Definition at line 2258 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_TCIF2

#define MCCI_STM32H7_DMA_ISR_TCIF2   (UINT32_C(1) << 21)

transfer complete interrupt flag

Definition at line 2251 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_TCIF3

#define MCCI_STM32H7_DMA_ISR_TCIF3   (UINT32_C(1) << 27)

transfer complete interrupt flag

Definition at line 2245 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_TEIF

#define MCCI_STM32H7_DMA_ISR_TEIF   (UINT32_C(1) << 3)

transfer error interrupt flag

Definition at line 2273 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_TEIF0

#define MCCI_STM32H7_DMA_ISR_TEIF0   (UINT32_C(1) << 3)

transfer error interrupt flag

Definition at line 2266 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_TEIF1

#define MCCI_STM32H7_DMA_ISR_TEIF1   (UINT32_C(1) << 9)

transfer error interrupt flag

Definition at line 2260 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_TEIF2

#define MCCI_STM32H7_DMA_ISR_TEIF2   (UINT32_C(1) << 19)

transfer error interrupt flag

Definition at line 2253 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_ISR_TEIF3

#define MCCI_STM32H7_DMA_ISR_TEIF3   (UINT32_C(1) << 25)

transfer error interrupt flag

Definition at line 2247 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_LIFCR

#define MCCI_STM32H7_DMA_LIFCR   UINT32_C(0x08)

offset to DMA low interrupt flag clear register

Definition at line 2213 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_LISR

#define MCCI_STM32H7_DMA_LISR   UINT32_C(0x00)

offset to DMA low interrupt status register

Definition at line 2211 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR

#define MCCI_STM32H7_DMA_SCR   UINT32_C(0x00)

offset to DMA stream configuration register

Definition at line 2216 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_CIRC

#define MCCI_STM32H7_DMA_SCR_CIRC   (UINT32_C(1) << 8)

circular mode

Definition at line 2311 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_CT

#define MCCI_STM32H7_DMA_SCR_CT   (UINT32_C(1) << 19)

current target (only in double-buffer mode)

Definition at line 2293 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_DBM

#define MCCI_STM32H7_DMA_SCR_DBM   (UINT32_C(1) << 18)

double-buffer mode

Definition at line 2294 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_DIR

#define MCCI_STM32H7_DMA_SCR_DIR   (UINT32_C(3) << 6)

data transfer direction

Definition at line 2312 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_DIR_MEM_TO_MEM

#define MCCI_STM32H7_DMA_SCR_DIR_MEM_TO_MEM   (UINT32_C(2) << 6)

memory-to-memory

Definition at line 2315 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_DIR_MEM_TO_PERI

#define MCCI_STM32H7_DMA_SCR_DIR_MEM_TO_PERI   (UINT32_C(1) << 6)

memory-to-peripheral

Definition at line 2314 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_DIR_PERI_TO_MEM

#define MCCI_STM32H7_DMA_SCR_DIR_PERI_TO_MEM   (UINT32_C(0) << 6)

peripheral-to-memory

Definition at line 2313 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_DMEIE

#define MCCI_STM32H7_DMA_SCR_DMEIE   (UINT32_C(1) << 1)

direct mode error interrupt enable

Definition at line 2320 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_EN

#define MCCI_STM32H7_DMA_SCR_EN   (UINT32_C(1) << 0)

stream enable / flag stream ready when read low

Definition at line 2321 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_HTIE

#define MCCI_STM32H7_DMA_SCR_HTIE   (UINT32_C(1) << 3)

half transfer interrupt enable

Definition at line 2318 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_MBURST

#define MCCI_STM32H7_DMA_SCR_MBURST   (UINT32_C(3) << 23)

memory burst transfer configuration

Definition at line 2282 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_MBURST_INCR16

#define MCCI_STM32H7_DMA_SCR_MBURST_INCR16   (UINT32_C(3) << 23)

INCR16 (incremental burst of 16 beats)

Definition at line 2286 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_MBURST_INCR4

#define MCCI_STM32H7_DMA_SCR_MBURST_INCR4   (UINT32_C(1) << 23)

INCR4 (incremental burst of 4 beats)

Definition at line 2284 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_MBURST_INCR8

#define MCCI_STM32H7_DMA_SCR_MBURST_INCR8   (UINT32_C(2) << 23)

INCR8 (incremental burst of 8 beats)

Definition at line 2285 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_MBURST_SINGLE

#define MCCI_STM32H7_DMA_SCR_MBURST_SINGLE   (UINT32_C(0) << 23)

single transfer

Definition at line 2283 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_MINC

#define MCCI_STM32H7_DMA_SCR_MINC   (UINT32_C(1) << 10)

memory increment mode

Definition at line 2309 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_MSIZE

#define MCCI_STM32H7_DMA_SCR_MSIZE   (UINT32_C(3) << 13)

memory data size

Definition at line 2301 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_MSIZE_BYTE

#define MCCI_STM32H7_DMA_SCR_MSIZE_BYTE   (UINT32_C(0) << 13)

byte (8-bit)

Definition at line 2302 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_MSIZE_HALF

#define MCCI_STM32H7_DMA_SCR_MSIZE_HALF   (UINT32_C(1) << 13)

hlaf-word (16-bit)

Definition at line 2303 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_MSIZE_WORD

#define MCCI_STM32H7_DMA_SCR_MSIZE_WORD   (UINT32_C(2) << 13)

word (32-bit)

Definition at line 2304 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_PBURST

#define MCCI_STM32H7_DMA_SCR_PBURST   (UINT32_C(3) << 21)

peripheral burst transfer configuration

Definition at line 2287 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_PBURST_INCR16

#define MCCI_STM32H7_DMA_SCR_PBURST_INCR16   (UINT32_C(3) << 21)

INCR16 (incremental burst of 16 beats)

Definition at line 2291 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_PBURST_INCR4

#define MCCI_STM32H7_DMA_SCR_PBURST_INCR4   (UINT32_C(1) << 21)

INCR4 (incremental burst of 4 beats)

Definition at line 2289 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_PBURST_INCR8

#define MCCI_STM32H7_DMA_SCR_PBURST_INCR8   (UINT32_C(2) << 21)

INCR8 (incremental burst of 8 beats)

Definition at line 2290 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_PBURST_SINGLE

#define MCCI_STM32H7_DMA_SCR_PBURST_SINGLE   (UINT32_C(0) << 21)

single transfer

Definition at line 2288 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_PFCTRL

#define MCCI_STM32H7_DMA_SCR_PFCTRL   (UINT32_C(1) << 5)

peripheral flow controller

Definition at line 2316 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_PINC

#define MCCI_STM32H7_DMA_SCR_PINC   (UINT32_C(1) << 9)

peripheral increment mode

Definition at line 2310 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_PINCOS

#define MCCI_STM32H7_DMA_SCR_PINCOS   (UINT32_C(1) << 15)

peripheral increment offset size

Definition at line 2300 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_PL

#define MCCI_STM32H7_DMA_SCR_PL   (UINT32_C(3) << 16)

priority level

Definition at line 2295 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_PL_HIGH

#define MCCI_STM32H7_DMA_SCR_PL_HIGH   (UINT32_C(0) << 16)

high

Definition at line 2298 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_PL_LOW

#define MCCI_STM32H7_DMA_SCR_PL_LOW   (UINT32_C(0) << 16)

low

Definition at line 2296 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_PL_MEDIUM

#define MCCI_STM32H7_DMA_SCR_PL_MEDIUM   (UINT32_C(0) << 16)

medium

Definition at line 2297 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_PL_VERY_HIGH

#define MCCI_STM32H7_DMA_SCR_PL_VERY_HIGH   (UINT32_C(0) << 16)

very high

Definition at line 2299 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_PSIZE

#define MCCI_STM32H7_DMA_SCR_PSIZE   (UINT32_C(3) << 11)

peripheral data size

Definition at line 2305 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_PSIZE_BYTE

#define MCCI_STM32H7_DMA_SCR_PSIZE_BYTE   (UINT32_C(0) << 11)

byte (8-bit)

Definition at line 2306 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_PSIZE_HALF

#define MCCI_STM32H7_DMA_SCR_PSIZE_HALF   (UINT32_C(1) << 11)

hlaf-word (16-bit)

Definition at line 2307 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_PSIZE_WORD

#define MCCI_STM32H7_DMA_SCR_PSIZE_WORD   (UINT32_C(2) << 11)

word (32-bit)

Definition at line 2308 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_RSV25

#define MCCI_STM32H7_DMA_SCR_RSV25   UINT32_C(0xFE000000)

reserved, don't change

Definition at line 2281 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_TCIE

#define MCCI_STM32H7_DMA_SCR_TCIE   (UINT32_C(1) << 4)

transfer complete interrupt enable

Definition at line 2317 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_TEIE

#define MCCI_STM32H7_DMA_SCR_TEIE   (UINT32_C(1) << 2)

transfer error interrupt enable

Definition at line 2319 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SCR_TRBUFF

#define MCCI_STM32H7_DMA_SCR_TRBUFF   (UINT32_C(1) << 20)

Enable the DMA to handle bufferable transfers.

Definition at line 2292 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SFCR

#define MCCI_STM32H7_DMA_SFCR   UINT32_C(0x14)

offset to DMA stream FIFO control register

Definition at line 2221 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SFCR_DMDIS

#define MCCI_STM32H7_DMA_SFCR_DMDIS   (UINT32_C(1) << 2)

direct mode disable

Definition at line 2336 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SFCR_FEIE

#define MCCI_STM32H7_DMA_SFCR_FEIE   (UINT32_C(1) << 7)

FIFO error interrupt enable.

Definition at line 2327 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SFCR_FS

#define MCCI_STM32H7_DMA_SFCR_FS   (UINT32_C(7) << 3)

FIFO status.

Definition at line 2329 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SFCR_FS_EMPTY

#define MCCI_STM32H7_DMA_SFCR_FS_EMPTY   (UINT32_C(4) << 3)

FIFO is empty.

Definition at line 2334 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SFCR_FS_FULL

#define MCCI_STM32H7_DMA_SFCR_FS_FULL   (UINT32_C(5) << 3)

FIFO is full.

Definition at line 2335 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SFCR_FS_LESS_1P2

#define MCCI_STM32H7_DMA_SFCR_FS_LESS_1P2   (UINT32_C(1) << 3)

1/4 <= fifo_level < 1/2

Definition at line 2331 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SFCR_FS_LESS_1P4

#define MCCI_STM32H7_DMA_SFCR_FS_LESS_1P4   (UINT32_C(0) << 3)

0 < fifo_level < 1/4

Definition at line 2330 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SFCR_FS_LESS_3P4

#define MCCI_STM32H7_DMA_SFCR_FS_LESS_3P4   (UINT32_C(2) << 3)

1/2 <= fifo_level < 3/4

Definition at line 2332 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SFCR_FS_LESS_FULL

#define MCCI_STM32H7_DMA_SFCR_FS_LESS_FULL   (UINT32_C(3) << 3)

3/4 <= fifo_level < full

Definition at line 2333 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SFCR_FTH

#define MCCI_STM32H7_DMA_SFCR_FTH   (UINT32_C(3) << 0)

FIFO threshold selection.

Definition at line 2337 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SFCR_FTH_1P2_FULL

#define MCCI_STM32H7_DMA_SFCR_FTH_1P2_FULL   (UINT32_C(1) << 0)

1/4 full FIFO

Definition at line 2339 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SFCR_FTH_1P4_FULL

#define MCCI_STM32H7_DMA_SFCR_FTH_1P4_FULL   (UINT32_C(0) << 0)

1/4 full FIFO

Definition at line 2338 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SFCR_FTH_3P4_FULL

#define MCCI_STM32H7_DMA_SFCR_FTH_3P4_FULL   (UINT32_C(2) << 0)

1/4 full FIFO

Definition at line 2340 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SFCR_FTH_FULL

#define MCCI_STM32H7_DMA_SFCR_FTH_FULL   (UINT32_C(3) << 0)

1/4 full FIFO

Definition at line 2341 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SFCR_RSV6

#define MCCI_STM32H7_DMA_SFCR_RSV6   (UINT32_C(1) << 6)

reserved, don't change

Definition at line 2328 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SFCR_RSV8

#define MCCI_STM32H7_DMA_SFCR_RSV8   UINT32_C(0xFFFFFF00)

reserved, don't change

Definition at line 2326 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SM0AR

#define MCCI_STM32H7_DMA_SM0AR   UINT32_C(0x0C)

offset to DMA stream memory 0 address register

Definition at line 2219 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SM1AR

#define MCCI_STM32H7_DMA_SM1AR   UINT32_C(0x10)

offset to DMA stream memory 1 address register

Definition at line 2220 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SNDTR

#define MCCI_STM32H7_DMA_SNDTR   UINT32_C(0x04)

offset to DMA stream number of data register

Definition at line 2217 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SPAR

#define MCCI_STM32H7_DMA_SPAR   UINT32_C(0x08)

offset to DMA stream peripheral address register

Definition at line 2218 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_STREAM_BASE

#define MCCI_STM32H7_DMA_STREAM_BASE (   x)    (((x) * UINT32_C(0x18)) + UINT32_C(0x10))

offset to DMA stream x base

Definition at line 2223 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SxCR

#define MCCI_STM32H7_DMA_SxCR (   x)    (((x) * UINT32_C(0x18)) + UINT32_C(0x10))

offset to DMA stream x configuration register

Definition at line 2224 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SxFCR

#define MCCI_STM32H7_DMA_SxFCR (   x)    (((x) * UINT32_C(0x18)) + UINT32_C(0x24))

offset to DMA stream x FIFO control register

Definition at line 2229 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SxM0AR

#define MCCI_STM32H7_DMA_SxM0AR (   x)    (((x) * UINT32_C(0x18)) + UINT32_C(0x1C))

offset to DMA stream x memory 0 address register

Definition at line 2227 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SxM1AR

#define MCCI_STM32H7_DMA_SxM1AR (   x)    (((x) * UINT32_C(0x18)) + UINT32_C(0x20))

offset to DMA stream x memory 1 address register

Definition at line 2228 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SxNDTR

#define MCCI_STM32H7_DMA_SxNDTR (   x)    (((x) * UINT32_C(0x18)) + UINT32_C(0x14))

offset to DMA stream x number of data register

Definition at line 2225 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMA_SxPAR

#define MCCI_STM32H7_DMA_SxPAR (   x)    (((x) * UINT32_C(0x18)) + UINT32_C(0x18))

offset to DMA stream x peripheral address register

Definition at line 2226 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_C0CR

#define MCCI_STM32H7_DMAMUX1_C0CR   UINT32_C(0x00)

offset to DMAMUX1 request line multiplexer channel 0 configuration register

Definition at line 2353 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_C10CR

#define MCCI_STM32H7_DMAMUX1_C10CR   UINT32_C(0x28)

offset to DMAMUX1 request line multiplexer channel 10 configuration register

Definition at line 2363 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_C11CR

#define MCCI_STM32H7_DMAMUX1_C11CR   UINT32_C(0x2C)

offset to DMAMUX1 request line multiplexer channel 11 configuration register

Definition at line 2364 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_C12CR

#define MCCI_STM32H7_DMAMUX1_C12CR   UINT32_C(0x30)

offset to DMAMUX1 request line multiplexer channel 12 configuration register

Definition at line 2365 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_C13CR

#define MCCI_STM32H7_DMAMUX1_C13CR   UINT32_C(0x34)

offset to DMAMUX1 request line multiplexer channel 13 configuration register

Definition at line 2366 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_C14CR

#define MCCI_STM32H7_DMAMUX1_C14CR   UINT32_C(0x38)

offset to DMAMUX1 request line multiplexer channel 14 configuration register

Definition at line 2367 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_C15CR

#define MCCI_STM32H7_DMAMUX1_C15CR   UINT32_C(0x3C)

offset to DMAMUX1 request line multiplexer channel 15 configuration register

Definition at line 2368 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_C1CR

#define MCCI_STM32H7_DMAMUX1_C1CR   UINT32_C(0x04)

offset to DMAMUX1 request line multiplexer channel 1 configuration register

Definition at line 2354 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_C2CR

#define MCCI_STM32H7_DMAMUX1_C2CR   UINT32_C(0x08)

offset to DMAMUX1 request line multiplexer channel 2 configuration register

Definition at line 2355 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_C3CR

#define MCCI_STM32H7_DMAMUX1_C3CR   UINT32_C(0x0C)

offset to DMAMUX1 request line multiplexer channel 3 configuration register

Definition at line 2356 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_C4CR

#define MCCI_STM32H7_DMAMUX1_C4CR   UINT32_C(0x10)

offset to DMAMUX1 request line multiplexer channel 4 configuration register

Definition at line 2357 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_C5CR

#define MCCI_STM32H7_DMAMUX1_C5CR   UINT32_C(0x14)

offset to DMAMUX1 request line multiplexer channel 5 configuration register

Definition at line 2358 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_C6CR

#define MCCI_STM32H7_DMAMUX1_C6CR   UINT32_C(0x18)

offset to DMAMUX1 request line multiplexer channel 6 configuration register

Definition at line 2359 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_C7CR

#define MCCI_STM32H7_DMAMUX1_C7CR   UINT32_C(0x1C)

offset to DMAMUX1 request line multiplexer channel 7 configuration register

Definition at line 2360 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_C8CR

#define MCCI_STM32H7_DMAMUX1_C8CR   UINT32_C(0x20)

offset to DMAMUX1 request line multiplexer channel 8 configuration register

Definition at line 2361 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_C9CR

#define MCCI_STM32H7_DMAMUX1_C9CR   UINT32_C(0x24)

offset to DMAMUX1 request line multiplexer channel 9 configuration register

Definition at line 2362 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_CCR

#define MCCI_STM32H7_DMAMUX1_CCR (   x)    ((x) * UINT32_C(0x04))

offset to DMAMUX1 request line multiplexer channel x configuration register

Definition at line 2369 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_CFR

#define MCCI_STM32H7_DMAMUX1_CFR   UINT32_C(0x84)

offset to DMAMUX1 request line multiplexer interrupt clear flag register

Definition at line 2383 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_CSR

#define MCCI_STM32H7_DMAMUX1_CSR   UINT32_C(0x80)

offset to DMAMUX1 request line multiplexer interrupt channel status register

Definition at line 2381 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_CxCR_DMAREQ_ID

#define MCCI_STM32H7_DMAMUX1_CxCR_DMAREQ_ID   (UINT32_C(0x7F) << 0)

DMA request identification.

Definition at line 2429 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_CxCR_DMAREQ_ID_N

#define MCCI_STM32H7_DMAMUX1_CxCR_DMAREQ_ID_N (   n)    ((n) << 0)

Definition at line 2430 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_CxCR_EGE

#define MCCI_STM32H7_DMAMUX1_CxCR_EGE   (UINT32_C(1) << 9)

Event generation enable.

Definition at line 2426 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_CxCR_NBREQ

#define MCCI_STM32H7_DMAMUX1_CxCR_NBREQ   (UINT32_C(0x1F) << 19)

Number of DMA requests minus 1 to forward.

Definition at line 2417 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_CxCR_NBREQ_N

#define MCCI_STM32H7_DMAMUX1_CxCR_NBREQ_N (   n)    ((n) << 19)

Definition at line 2418 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_CxCR_RSV10

#define MCCI_STM32H7_DMAMUX1_CxCR_RSV10   (UINT32_C(0x3F) << 10)

reserved, don't change

Definition at line 2425 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_CxCR_RSV27

#define MCCI_STM32H7_DMAMUX1_CxCR_RSV27   UINT32_C(0xF8000000)

reserved, don't change

Definition at line 2414 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_CxCR_RSV7

#define MCCI_STM32H7_DMAMUX1_CxCR_RSV7   (UINT32_C(1) << 7)

reserved, don't change

Definition at line 2428 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_CxCR_SE

#define MCCI_STM32H7_DMAMUX1_CxCR_SE   (UINT32_C(1) << 16)

Synchronization enable.

Definition at line 2424 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_CxCR_SOIE

#define MCCI_STM32H7_DMAMUX1_CxCR_SOIE   (UINT32_C(1) << 8)

Synchronization overrun interrupt enable.

Definition at line 2427 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_CxCR_SPOL

#define MCCI_STM32H7_DMAMUX1_CxCR_SPOL   (UINT32_C(3) << 17)

Synchronization polarity.

Definition at line 2419 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_CxCR_SPOL_BOTH

#define MCCI_STM32H7_DMAMUX1_CxCR_SPOL_BOTH   (UINT32_C(3) << 17)

rising and falling edges

Definition at line 2423 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_CxCR_SPOL_FALLING

#define MCCI_STM32H7_DMAMUX1_CxCR_SPOL_FALLING   (UINT32_C(2) << 17)

falling edge

Definition at line 2422 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_CxCR_SPOL_NO

#define MCCI_STM32H7_DMAMUX1_CxCR_SPOL_NO   (UINT32_C(0) << 17)

no event, i.e. no synchronization nor detection

Definition at line 2420 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_CxCR_SPOL_RISING

#define MCCI_STM32H7_DMAMUX1_CxCR_SPOL_RISING   (UINT32_C(1) << 17)

rising edge

Definition at line 2421 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_CxCR_SYNC_ID

#define MCCI_STM32H7_DMAMUX1_CxCR_SYNC_ID   (UINT32_C(7) << 24)

Synchronization identification.

Definition at line 2415 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_CxCR_SYNC_ID_N

#define MCCI_STM32H7_DMAMUX1_CxCR_SYNC_ID_N (   n)    ((n) << 24)

Definition at line 2416 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RG0CR

#define MCCI_STM32H7_DMAMUX1_RG0CR   UINT32_C(0x100)

offset to DMAMUX1 request generator channel 0 configuration register

Definition at line 2386 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RG1CR

#define MCCI_STM32H7_DMAMUX1_RG1CR   UINT32_C(0x104)

offset to DMAMUX1 request generator channel 1 configuration register

Definition at line 2387 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RG2CR

#define MCCI_STM32H7_DMAMUX1_RG2CR   UINT32_C(0x108)

offset to DMAMUX1 request generator channel 2 configuration register

Definition at line 2388 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RG3CR

#define MCCI_STM32H7_DMAMUX1_RG3CR   UINT32_C(0x10C)

offset to DMAMUX1 request generator channel 3 configuration register

Definition at line 2389 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RG4CR

#define MCCI_STM32H7_DMAMUX1_RG4CR   UINT32_C(0x110)

offset to DMAMUX1 request generator channel 4 configuration register

Definition at line 2390 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RG5CR

#define MCCI_STM32H7_DMAMUX1_RG5CR   UINT32_C(0x114)

offset to DMAMUX1 request generator channel 5 configuration register

Definition at line 2391 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RG6CR

#define MCCI_STM32H7_DMAMUX1_RG6CR   UINT32_C(0x118)

offset to DMAMUX1 request generator channel 6 configuration register

Definition at line 2392 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RG7CR

#define MCCI_STM32H7_DMAMUX1_RG7CR   UINT32_C(0x11C)

offset to DMAMUX1 request generator channel 7 configuration register

Definition at line 2393 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RGCFR

#define MCCI_STM32H7_DMAMUX1_RGCFR   UINT32_C(0x144)

offset to DMAMUX1 request generator interrupt clear flag register

Definition at line 2408 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RGCR

#define MCCI_STM32H7_DMAMUX1_RGCR (   x)    (UINT32_C(0x100) + ((x) * UINT32_C(0x04)))

offset to DMAMUX1 request generator channel x configuration register

Definition at line 2394 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RGSR

#define MCCI_STM32H7_DMAMUX1_RGSR   UINT32_C(0x140)

offset to DMAMUX1 request generator interrupt channel status register

Definition at line 2406 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RGxCR_GE

#define MCCI_STM32H7_DMAMUX1_RGxCR_GE   (UINT32_C(1) << 16)

DMA request generator channel x enable.

Definition at line 2464 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RGxCR_GNBREQ

#define MCCI_STM32H7_DMAMUX1_RGxCR_GNBREQ   (UINT32_C(0x1F) << 19)

Number of DMA requests to be generated (minus 1)

Definition at line 2457 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RGxCR_GNBREQ_N

#define MCCI_STM32H7_DMAMUX1_RGxCR_GNBREQ_N (   n)    ((n) << 19)

Definition at line 2458 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RGxCR_GPOL

#define MCCI_STM32H7_DMAMUX1_RGxCR_GPOL   (UINT32_C(3) << 17)

DMA request generator trigger polarity.

Definition at line 2459 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RGxCR_GPOL_BOTH

#define MCCI_STM32H7_DMAMUX1_RGxCR_GPOL_BOTH   (UINT32_C(3) << 17)

rising and falling edges

Definition at line 2463 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RGxCR_GPOL_FALLING

#define MCCI_STM32H7_DMAMUX1_RGxCR_GPOL_FALLING   (UINT32_C(2) << 17)

falling edge

Definition at line 2462 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RGxCR_GPOL_NO

#define MCCI_STM32H7_DMAMUX1_RGxCR_GPOL_NO   (UINT32_C(0) << 17)

no event, i.e. no synchronization nor detection

Definition at line 2460 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RGxCR_GPOL_RISING

#define MCCI_STM32H7_DMAMUX1_RGxCR_GPOL_RISING   (UINT32_C(1) << 17)

rising edge

Definition at line 2461 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RGxCR_OIE

#define MCCI_STM32H7_DMAMUX1_RGxCR_OIE   (UINT32_C(1) << 8)

Trigger overrun interrupt enable.

Definition at line 2466 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RGxCR_RSV24

#define MCCI_STM32H7_DMAMUX1_RGxCR_RSV24   UINT32_C(0xFF000000)

reserved, don't change

Definition at line 2456 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RGxCR_RSV3

#define MCCI_STM32H7_DMAMUX1_RGxCR_RSV3   (UINT32_C(0x1F) << 3)

reserved, don't change

Definition at line 2467 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RGxCR_RSV9

#define MCCI_STM32H7_DMAMUX1_RGxCR_RSV9   (UINT32_C(0x7F) << 9)

reserved, don't change

Definition at line 2465 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RGxCR_SIG_ID

#define MCCI_STM32H7_DMAMUX1_RGxCR_SIG_ID   (UINT32_C(7) << 0)

Signal identification.

Definition at line 2468 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX1_RGxCR_SIG_ID_N

#define MCCI_STM32H7_DMAMUX1_RGxCR_SIG_ID_N (   n)    ((n) << 0)

Definition at line 2469 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_C0CR

#define MCCI_STM32H7_DMAMUX2_C0CR   UINT32_C(0x00)

offset to DMAMUX2 request line multiplexer channel 0 configuration register

Definition at line 2371 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_C1CR

#define MCCI_STM32H7_DMAMUX2_C1CR   UINT32_C(0x04)

offset to DMAMUX2 request line multiplexer channel 1 configuration register

Definition at line 2372 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_C2CR

#define MCCI_STM32H7_DMAMUX2_C2CR   UINT32_C(0x08)

offset to DMAMUX2 request line multiplexer channel 2 configuration register

Definition at line 2373 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_C3CR

#define MCCI_STM32H7_DMAMUX2_C3CR   UINT32_C(0x0C)

offset to DMAMUX2 request line multiplexer channel 3 configuration register

Definition at line 2374 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_C4CR

#define MCCI_STM32H7_DMAMUX2_C4CR   UINT32_C(0x10)

offset to DMAMUX2 request line multiplexer channel 4 configuration register

Definition at line 2375 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_C5CR

#define MCCI_STM32H7_DMAMUX2_C5CR   UINT32_C(0x14)

offset to DMAMUX2 request line multiplexer channel 5 configuration register

Definition at line 2376 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_C6CR

#define MCCI_STM32H7_DMAMUX2_C6CR   UINT32_C(0x18)

offset to DMAMUX2 request line multiplexer channel 6 configuration register

Definition at line 2377 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_C7CR

#define MCCI_STM32H7_DMAMUX2_C7CR   UINT32_C(0x1C)

offset to DMAMUX2 request line multiplexer channel 7 configuration register

Definition at line 2378 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_CCR

#define MCCI_STM32H7_DMAMUX2_CCR (   x)    ((x) * UINT32_C(0x04))

offset to DMAMUX2 request line multiplexer channel x configuration register

Definition at line 2379 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_CFR

#define MCCI_STM32H7_DMAMUX2_CFR   UINT32_C(0x84)

offset to DMAMUX2 request line multiplexer interrupt clear flag register

Definition at line 2384 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_CSR

#define MCCI_STM32H7_DMAMUX2_CSR   UINT32_C(0x80)

offset to DMAMUX2 request line multiplexer interrupt channel status register

Definition at line 2382 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_CxCR_DMAREQ_ID

#define MCCI_STM32H7_DMAMUX2_CxCR_DMAREQ_ID   (UINT32_C(0x1F) << 0)

DMA request identification.

Definition at line 2450 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_CxCR_DMAREQ_ID_N

#define MCCI_STM32H7_DMAMUX2_CxCR_DMAREQ_ID_N (   n)    ((n) << 0)

Definition at line 2451 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_CxCR_EGE

#define MCCI_STM32H7_DMAMUX2_CxCR_EGE   (UINT32_C(1) << 9)

Event generation enable.

Definition at line 2447 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_CxCR_NBREQ

#define MCCI_STM32H7_DMAMUX2_CxCR_NBREQ   (UINT32_C(0x1F) << 19)

Number of DMA requests minus 1 to forward.

Definition at line 2438 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_CxCR_NBREQ_N

#define MCCI_STM32H7_DMAMUX2_CxCR_NBREQ_N (   n)    ((n) << 19)

Definition at line 2439 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_CxCR_RSV10

#define MCCI_STM32H7_DMAMUX2_CxCR_RSV10   (UINT32_C(0x3F) << 10)

reserved, don't change

Definition at line 2446 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_CxCR_RSV28

#define MCCI_STM32H7_DMAMUX2_CxCR_RSV28   UINT32_C(0xF0000000)

reserved, don't change

Definition at line 2435 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_CxCR_RSV7

#define MCCI_STM32H7_DMAMUX2_CxCR_RSV7   (UINT32_C(7) << 5)

reserved, don't change

Definition at line 2449 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_CxCR_SE

#define MCCI_STM32H7_DMAMUX2_CxCR_SE   (UINT32_C(1) << 16)

Synchronization enable.

Definition at line 2445 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_CxCR_SOIE

#define MCCI_STM32H7_DMAMUX2_CxCR_SOIE   (UINT32_C(1) << 8)

Synchronization overrun interrupt enable.

Definition at line 2448 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_CxCR_SPOL

#define MCCI_STM32H7_DMAMUX2_CxCR_SPOL   (UINT32_C(3) << 17)

Synchronization polarity.

Definition at line 2440 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_CxCR_SPOL_BOTH

#define MCCI_STM32H7_DMAMUX2_CxCR_SPOL_BOTH   (UINT32_C(3) << 17)

rising and falling edges

Definition at line 2444 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_CxCR_SPOL_FALLING

#define MCCI_STM32H7_DMAMUX2_CxCR_SPOL_FALLING   (UINT32_C(2) << 17)

falling edge

Definition at line 2443 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_CxCR_SPOL_NO

#define MCCI_STM32H7_DMAMUX2_CxCR_SPOL_NO   (UINT32_C(0) << 17)

no event, i.e. no synchronization nor detection

Definition at line 2441 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_CxCR_SPOL_RISING

#define MCCI_STM32H7_DMAMUX2_CxCR_SPOL_RISING   (UINT32_C(1) << 17)

rising edge

Definition at line 2442 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_CxCR_SYNC_ID

#define MCCI_STM32H7_DMAMUX2_CxCR_SYNC_ID   (UINT32_C(0xF) << 24)

Synchronization identification.

Definition at line 2436 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_CxCR_SYNC_ID_N

#define MCCI_STM32H7_DMAMUX2_CxCR_SYNC_ID_N (   n)    ((n) << 24)

Definition at line 2437 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RG0CR

#define MCCI_STM32H7_DMAMUX2_RG0CR   UINT32_C(0x100)

offset to DMAMUX2 request generator channel 0 configuration register

Definition at line 2396 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RG1CR

#define MCCI_STM32H7_DMAMUX2_RG1CR   UINT32_C(0x104)

offset to DMAMUX2 request generator channel 1 configuration register

Definition at line 2397 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RG2CR

#define MCCI_STM32H7_DMAMUX2_RG2CR   UINT32_C(0x108)

offset to DMAMUX2 request generator channel 2 configuration register

Definition at line 2398 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RG3CR

#define MCCI_STM32H7_DMAMUX2_RG3CR   UINT32_C(0x10C)

offset to DMAMUX2 request generator channel 3 configuration register

Definition at line 2399 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RG4CR

#define MCCI_STM32H7_DMAMUX2_RG4CR   UINT32_C(0x110)

offset to DMAMUX2 request generator channel 4 configuration register

Definition at line 2400 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RG5CR

#define MCCI_STM32H7_DMAMUX2_RG5CR   UINT32_C(0x114)

offset to DMAMUX2 request generator channel 5 configuration register

Definition at line 2401 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RG6CR

#define MCCI_STM32H7_DMAMUX2_RG6CR   UINT32_C(0x118)

offset to DMAMUX2 request generator channel 6 configuration register

Definition at line 2402 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RG7CR

#define MCCI_STM32H7_DMAMUX2_RG7CR   UINT32_C(0x11C)

offset to DMAMUX2 request generator channel 7 configuration register

Definition at line 2403 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RGCFR

#define MCCI_STM32H7_DMAMUX2_RGCFR   UINT32_C(0x144)

offset to DMAMUX2 request generator interrupt clear flag register

Definition at line 2409 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RGCR

#define MCCI_STM32H7_DMAMUX2_RGCR (   x)    (UINT32_C(0x100) + ((x) * UINT32_C(0x04)))

offset to DMAMUX2 request generator channel x configuration register

Definition at line 2404 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RGSR

#define MCCI_STM32H7_DMAMUX2_RGSR   UINT32_C(0x140)

offset to DMAMUX2 request generator interrupt channel status register

Definition at line 2407 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RGxCR_GE

#define MCCI_STM32H7_DMAMUX2_RGxCR_GE   (UINT32_C(1) << 16)

DMA request generator channel x enable.

Definition at line 2482 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RGxCR_GNBREQ

#define MCCI_STM32H7_DMAMUX2_RGxCR_GNBREQ   (UINT32_C(0x1F) << 19)

Number of DMA requests to be generated (minus 1)

Definition at line 2475 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RGxCR_GNBREQ_N

#define MCCI_STM32H7_DMAMUX2_RGxCR_GNBREQ_N (   n)    ((n) << 19)

Definition at line 2476 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RGxCR_GPOL

#define MCCI_STM32H7_DMAMUX2_RGxCR_GPOL   (UINT32_C(3) << 17)

DMA request generator trigger polarity.

Definition at line 2477 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RGxCR_GPOL_BOTH

#define MCCI_STM32H7_DMAMUX2_RGxCR_GPOL_BOTH   (UINT32_C(3) << 17)

rising and falling edges

Definition at line 2481 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RGxCR_GPOL_FALLING

#define MCCI_STM32H7_DMAMUX2_RGxCR_GPOL_FALLING   (UINT32_C(2) << 17)

falling edge

Definition at line 2480 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RGxCR_GPOL_NO

#define MCCI_STM32H7_DMAMUX2_RGxCR_GPOL_NO   (UINT32_C(0) << 17)

no event, i.e. no synchronization nor detection

Definition at line 2478 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RGxCR_GPOL_RISING

#define MCCI_STM32H7_DMAMUX2_RGxCR_GPOL_RISING   (UINT32_C(1) << 17)

rising edge

Definition at line 2479 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RGxCR_OIE

#define MCCI_STM32H7_DMAMUX2_RGxCR_OIE   (UINT32_C(1) << 8)

Trigger overrun interrupt enable.

Definition at line 2484 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RGxCR_RSV24

#define MCCI_STM32H7_DMAMUX2_RGxCR_RSV24   UINT32_C(0xFF000000)

reserved, don't change

Definition at line 2474 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RGxCR_RSV5

#define MCCI_STM32H7_DMAMUX2_RGxCR_RSV5   (UINT32_C(7) << 5)

reserved, don't change

Definition at line 2485 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RGxCR_RSV9

#define MCCI_STM32H7_DMAMUX2_RGxCR_RSV9   (UINT32_C(0x7F) << 9)

reserved, don't change

Definition at line 2483 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RGxCR_SIG_ID

#define MCCI_STM32H7_DMAMUX2_RGxCR_SIG_ID   (UINT32_C(0x1F) << 0)

Signal identification.

Definition at line 2486 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_DMAMUX2_RGxCR_SIG_ID_N

#define MCCI_STM32H7_DMAMUX2_RGxCR_SIG_ID_N (   n)    ((n) << 0)

Definition at line 2487 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_FLASH_GET_BANK

#define MCCI_STM32H7_FLASH_GET_BANK (   f)    (((f) >> 20) & 1)

Definition at line 478 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_FLASH_GET_SECTOR

#define MCCI_STM32H7_FLASH_GET_SECTOR (   f)    (((f) >> 13) & 0x7F)

Definition at line 479 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_FLASH_IS_BANK2

#define MCCI_STM32H7_FLASH_IS_BANK2 (   f)    ((f) & UINT32_C(0x100000))

Definition at line 477 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_FLASH_IS_VALID

#define MCCI_STM32H7_FLASH_IS_VALID (   f)    ((f) >= MCCI_STM32H7_MEMORY_FLASH && (f) <= MCCI_STM32H7_MEMORY_FLASH_END)

Definition at line 476 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_FLASH_PROGRAM_FLASH_SIZE

#define MCCI_STM32H7_FLASH_PROGRAM_FLASH_SIZE   UINT32_C(16)

size in bytes of a FLASH program

Definition at line 473 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_FLASH_PROGRAM_OTP_SIZE

#define MCCI_STM32H7_FLASH_PROGRAM_OTP_SIZE   UINT32_C(2)

size in bytes of a FLASH program

Definition at line 474 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_FLASH_SECTOR_SIZE

#define MCCI_STM32H7_FLASH_SECTOR_SIZE   UINT32_C(8192)

size in bytes of a sector

Definition at line 472 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_AFRH

#define MCCI_STM32H7_GPIO_AFRH   UINT32_C(0x24)

Definition at line 1887 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_AFRL

#define MCCI_STM32H7_GPIO_AFRL   UINT32_C(0x20)

Definition at line 1886 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_AFRx_P

#define MCCI_STM32H7_GPIO_AFRx_P (   p)    (MCCI_STM32H7_GPIO_AFRL + (((p) / UINT32_C(8)) * UINT32_C(4)))

Definition at line 1995 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_AFSEL_P

#define MCCI_STM32H7_GPIO_AFSEL_P (   p)    (UINT32_C(0xF) << (((p) & UINT32_C(0x7)) * UINT32_C(4)))

get AFRx mask for port bit p.

Normal use: MCCI_BOOTLOADER_FIELD_SET_VALUE( MCCI_STM32H7_GPIO_AFSEL_P(bitnum), 0..15 )

Definition at line 2006 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_AFSEL_PV

#define MCCI_STM32H7_GPIO_AFSEL_PV (   p,
  v 
)    ((v) << (((p) & UINT32_C(0x7)) * UINT32_C(4)))

Definition at line 2007 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_BSRR

#define MCCI_STM32H7_GPIO_BSRR   UINT32_C(0x18)

Definition at line 1884 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_BSRR_BR

#define MCCI_STM32H7_GPIO_BSRR_BR   (UINT32_C(0xFFFF) << 16)

Definition at line 1974 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_BSRR_BR0

#define MCCI_STM32H7_GPIO_BSRR_BR0   (UINT32_C(1) << 16)

Definition at line 1973 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_BSRR_BR_P

#define MCCI_STM32H7_GPIO_BSRR_BR_P (   p)    (MCCI_STM32H7_GPIO_BSRR_BR0 << (p))

compute port-bit reset mask for bit p.

Definition at line 1978 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_BSRR_BS

#define MCCI_STM32H7_GPIO_BSRR_BS   (UINT32_C(0xFFFF) << 0)

Definition at line 1976 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_BSRR_BS0

#define MCCI_STM32H7_GPIO_BSRR_BS0   (UINT32_C(1) << 0)

Definition at line 1975 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_BSRR_BS_P

#define MCCI_STM32H7_GPIO_BSRR_BS_P (   p)    (MCCI_STM32H7_GPIO_BSRR_BS0 << (p))

compute port-bit set mask for bit p.

Definition at line 1980 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_IDR

#define MCCI_STM32H7_GPIO_IDR   UINT32_C(0x10)

Definition at line 1882 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_LCKR

#define MCCI_STM32H7_GPIO_LCKR   UINT32_C(0x1C)

Definition at line 1885 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_LCKR_LCK

#define MCCI_STM32H7_GPIO_LCKR_LCK   (UINT32_C(0xFFFF) << 0)

Definition at line 1989 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_LCKR_LCK_P

#define MCCI_STM32H7_GPIO_LCKR_LCK_P (   p)    (UINT32_C(1) << (p))

compute GPIO lock bit fmask for bit p.

Definition at line 1988 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_LCKR_LCKK

#define MCCI_STM32H7_GPIO_LCKR_LCKK   (UINT32_C(1) << 16)

Definition at line 1986 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_LCKR_RSV17

#define MCCI_STM32H7_GPIO_LCKR_RSV17   UINT32_C(0xFFFE0000)

Definition at line 1985 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_MODE_AF

#define MCCI_STM32H7_GPIO_MODE_AF   UINT32_C(2)

Definition at line 1895 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_MODE_ANALOG

#define MCCI_STM32H7_GPIO_MODE_ANALOG   UINT32_C(3)

Definition at line 1896 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_MODE_IN

#define MCCI_STM32H7_GPIO_MODE_IN   UINT32_C(0)

Definition at line 1893 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_MODE_MASK

#define MCCI_STM32H7_GPIO_MODE_MASK   UINT32_C(3)

Definition at line 1892 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_MODE_OUT

#define MCCI_STM32H7_GPIO_MODE_OUT   UINT32_C(1)

Definition at line 1894 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_MODE_P

#define MCCI_STM32H7_GPIO_MODE_P (   p)    (UINT32_C(3) << (2 * (p)))

compute the mask for the mode bits for port bits 0..31

Normally we compute a mask using an expression like: 

`MCCI_BOOTLOADER_FIELD_SET_VALUE(
    MCCI_STM32H7_GPIO_MODE_P(3),
    MCCI_STM32H7_GPIO_MODE_IN
    )`

Definition at line 1908 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_MODE_PV

#define MCCI_STM32H7_GPIO_MODE_PV (   p,
  v 
)    ((v) << (2 * (p)))

Definition at line 1909 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_MODER

#define MCCI_STM32H7_GPIO_MODER   UINT32_C(0x00)

Definition at line 1878 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_ODR

#define MCCI_STM32H7_GPIO_ODR   UINT32_C(0x14)

Definition at line 1883 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_OSPEED_HIGH

#define MCCI_STM32H7_GPIO_OSPEED_HIGH   UINT32_C(2)

Definition at line 1935 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_OSPEED_LOW

#define MCCI_STM32H7_GPIO_OSPEED_LOW   UINT32_C(0)

Definition at line 1933 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_OSPEED_MASK

#define MCCI_STM32H7_GPIO_OSPEED_MASK   UINT32_C(3)

Definition at line 1932 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_OSPEED_MEDIUM

#define MCCI_STM32H7_GPIO_OSPEED_MEDIUM   UINT32_C(1)

Definition at line 1934 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_OSPEED_P

#define MCCI_STM32H7_GPIO_OSPEED_P (   p)    (UINT32_C(3) << (2 * (p)))

compute the mask for the mode bits for port bits 0..31

Normally we compute a mask using an expression like: 

`MCCI_BOOTLOADER_FIELD_SET_VALUE(
    MCCI_STM32H7_GPIO_OSPEED_P(3),
    MCCI_STM32H7_GPIO_OSPEED_IN
    )`

Definition at line 1948 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_OSPEED_PV

#define MCCI_STM32H7_GPIO_OSPEED_PV (   p,
  v 
)    ((v) << (2 * (p)))

Definition at line 1949 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_OSPEED_VHIGH

#define MCCI_STM32H7_GPIO_OSPEED_VHIGH   UINT32_C(3)

Definition at line 1936 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_OSPEEDR

#define MCCI_STM32H7_GPIO_OSPEEDR   UINT32_C(0x08)

Definition at line 1880 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_OTYPE_OD

#define MCCI_STM32H7_GPIO_OTYPE_OD   UINT32_C(1)

Definition at line 1914 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_OTYPE_P

#define MCCI_STM32H7_GPIO_OTYPE_P (   p)    (UINT32_C(1) << (p))

compute the mask for the mode bits for port bits 0..15

Normally we compute a mask using an expression like: 

`MCCI_BOOTLOADER_FIELD_SET_VALUE(
    MCCI_STM32H7_GPIO_OTYPE_P(3),
    MCCI_STM32H7_GPIO_OTYPE_PP
    )`

Definition at line 1927 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_OTYPE_PP

#define MCCI_STM32H7_GPIO_OTYPE_PP   UINT32_C(0)

Definition at line 1913 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_OTYPE_PV

#define MCCI_STM32H7_GPIO_OTYPE_PV (   p,
  v 
)    ((v) << (p))

Definition at line 1928 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_OTYPER

#define MCCI_STM32H7_GPIO_OTYPER   UINT32_C(0x04)

Definition at line 1879 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_PUPD_MASK

#define MCCI_STM32H7_GPIO_PUPD_MASK   UINT32_C(3)

Definition at line 1953 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_PUPD_NONE

#define MCCI_STM32H7_GPIO_PUPD_NONE   UINT32_C(0)

Definition at line 1954 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_PUPD_P

#define MCCI_STM32H7_GPIO_PUPD_P (   p)    (UINT32_C(3) << (2 * (p)))

compute the mask for the mode bits for port bits 0..31

Normally we compute a mask using an expression like: 

`MCCI_BOOTLOADER_FIELD_SET_VALUE(
    MCCI_STM32H7_GPIO_PUPD_P(3),
    MCCI_STM32H7_GPIO_PUPD_PULLDOWN
    )`

Definition at line 1968 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_PUPD_PULLDOWN

#define MCCI_STM32H7_GPIO_PUPD_PULLDOWN   UINT32_C(2)

Definition at line 1956 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_PUPD_PULLUP

#define MCCI_STM32H7_GPIO_PUPD_PULLUP   UINT32_C(1)

Definition at line 1955 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_PUPD_PV

#define MCCI_STM32H7_GPIO_PUPD_PV (   p,
  v 
)    ((v) << (2 * (p)))

Definition at line 1969 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_GPIO_PUPDR

#define MCCI_STM32H7_GPIO_PUPDR   UINT32_C(0x0C)

Definition at line 1881 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1

#define MCCI_STM32H7_I2C_CR1   UINT32_C(0x00)

offset to I2C control register 1

Definition at line 2638 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_ADDRIE

#define MCCI_STM32H7_I2C_CR1_ADDRIE   (UINT32_C(1) << 3)

Address match Interrupt enable (slave only)

Definition at line 2672 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_ALERTEN

#define MCCI_STM32H7_I2C_CR1_ALERTEN   (UINT32_C(1) << 22)

SMBus alert enable.

Definition at line 2655 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_ANFOFF

#define MCCI_STM32H7_I2C_CR1_ANFOFF   (UINT32_C(1) << 12)

Analog noise filter OFF.

Definition at line 2665 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_DNF

#define MCCI_STM32H7_I2C_CR1_DNF   (UINT32_C(0xF) << 8)

Digital noise filter.

Definition at line 2666 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_DNF_N

#define MCCI_STM32H7_I2C_CR1_DNF_N (   n)    ((n) << 8)

Definition at line 2667 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_ERRIE

#define MCCI_STM32H7_I2C_CR1_ERRIE   (UINT32_C(1) << 7)

Error interrupts enable.

Definition at line 2668 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_GCEN

#define MCCI_STM32H7_I2C_CR1_GCEN   (UINT32_C(1) << 19)

General call enable.

Definition at line 2658 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_NACKIE

#define MCCI_STM32H7_I2C_CR1_NACKIE   (UINT32_C(1) << 4)

Not acknowledge received Interrupt enable.

Definition at line 2671 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_NOSTRETCH

#define MCCI_STM32H7_I2C_CR1_NOSTRETCH   (UINT32_C(1) << 17)

Clock stretching disable.

Definition at line 2660 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_PE

#define MCCI_STM32H7_I2C_CR1_PE   (UINT32_C(1) << 0)

Peripheral enable.

Definition at line 2675 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_PECEN

#define MCCI_STM32H7_I2C_CR1_PECEN   (UINT32_C(1) << 23)

PEC enable.

Definition at line 2654 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_RSV13

#define MCCI_STM32H7_I2C_CR1_RSV13   (UINT32_C(1) << 13)

reserved, don't change

Definition at line 2664 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_RSV24

#define MCCI_STM32H7_I2C_CR1_RSV24   UINT32_C(0xFF000000)

reserved, don't change

Definition at line 2653 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_RXDMAEN

#define MCCI_STM32H7_I2C_CR1_RXDMAEN   (UINT32_C(1) << 15)

DMA reception requests enable.

Definition at line 2662 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_RXIE

#define MCCI_STM32H7_I2C_CR1_RXIE   (UINT32_C(1) << 2)

RX Interrupt enable.

Definition at line 2673 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_SBC

#define MCCI_STM32H7_I2C_CR1_SBC   (UINT32_C(1) << 16)

Slave byte control.

Definition at line 2661 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_SMBDEN

#define MCCI_STM32H7_I2C_CR1_SMBDEN   (UINT32_C(1) << 21)

SMBus Device Default Address enable.

Definition at line 2656 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_SMBHEN

#define MCCI_STM32H7_I2C_CR1_SMBHEN   (UINT32_C(1) << 20)

SMBus Host Address enable.

Definition at line 2657 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_STOPIE

#define MCCI_STM32H7_I2C_CR1_STOPIE   (UINT32_C(1) << 5)

Stop detection Interrupt enable.

Definition at line 2670 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_TCIE

#define MCCI_STM32H7_I2C_CR1_TCIE   (UINT32_C(1) << 6)

Transfer Complete interrupt enable.

Definition at line 2669 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_TXDMAEN

#define MCCI_STM32H7_I2C_CR1_TXDMAEN   (UINT32_C(1) << 14)

DMA transmission requests enable.

Definition at line 2663 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_TXIE

#define MCCI_STM32H7_I2C_CR1_TXIE   (UINT32_C(1) << 1)

TX Interrupt enable.

Definition at line 2674 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR1_WUPEN

#define MCCI_STM32H7_I2C_CR1_WUPEN   (UINT32_C(1) << 18)

Wakeup from Stop mode enable.

Definition at line 2659 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR2

#define MCCI_STM32H7_I2C_CR2   UINT32_C(0x04)

offset to I2C control register 2

Definition at line 2639 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR2_ADD10

#define MCCI_STM32H7_I2C_CR2_ADD10   (UINT32_C(1) << 11)

10-bit addressing mode (master mode)

Definition at line 2690 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR2_AUTOEND

#define MCCI_STM32H7_I2C_CR2_AUTOEND   (UINT32_C(1) << 25)

Automatic end mode (master mode)

Definition at line 2682 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR2_HEAD10R

#define MCCI_STM32H7_I2C_CR2_HEAD10R   (UINT32_C(1) << 12)

10-bit address header only read direction (master receiver mode)

Definition at line 2689 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR2_NACK

#define MCCI_STM32H7_I2C_CR2_NACK   (UINT32_C(1) << 15)

NACK generation (slave mode)

Definition at line 2686 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR2_NBYTES

#define MCCI_STM32H7_I2C_CR2_NBYTES   (UINT32_C(0xFF) << 16)

Number of bytes.

Definition at line 2684 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR2_NBYTES_N

#define MCCI_STM32H7_I2C_CR2_NBYTES_N (   n)    ((n) << 16)

Definition at line 2685 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR2_PECBYTE

#define MCCI_STM32H7_I2C_CR2_PECBYTE   (UINT32_C(1) << 26)

Packet error checking byte.

Definition at line 2681 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR2_RD_WRN

#define MCCI_STM32H7_I2C_CR2_RD_WRN   (UINT32_C(1) << 10)

Transfer direction (master mode)

Definition at line 2691 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR2_RELOAD

#define MCCI_STM32H7_I2C_CR2_RELOAD   (UINT32_C(1) << 24)

NBYTES reload mode.

Definition at line 2683 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR2_RSV27

#define MCCI_STM32H7_I2C_CR2_RSV27   UINT32_C(0xF8000000)

reserved, don't change

Definition at line 2680 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR2_SADD

#define MCCI_STM32H7_I2C_CR2_SADD   (UINT32_C(0x3FF) << 0)

Slave address (master mode)

Definition at line 2692 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR2_SADD_N

#define MCCI_STM32H7_I2C_CR2_SADD_N (   n)    ((n) << 0)

Definition at line 2693 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR2_START

#define MCCI_STM32H7_I2C_CR2_START   (UINT32_C(1) << 13)

Start generation.

Definition at line 2688 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_CR2_STOP

#define MCCI_STM32H7_I2C_CR2_STOP   (UINT32_C(1) << 14)

Stop generation (master mode)

Definition at line 2687 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ICR

#define MCCI_STM32H7_I2C_ICR   UINT32_C(0x1C)

offset to I2C interrupt clear register

Definition at line 2645 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ICR_ADDRCF

#define MCCI_STM32H7_I2C_ICR_ADDRCF   (UINT32_C(1) << 3)

Address matched flag clear.

Definition at line 2780 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ICR_ALERTCF

#define MCCI_STM32H7_I2C_ICR_ALERTCF   (UINT32_C(1) << 13)

Alert flag clear.

Definition at line 2771 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ICR_ARLOCF

#define MCCI_STM32H7_I2C_ICR_ARLOCF   (UINT32_C(1) << 9)

Arbitration lost flag clear.

Definition at line 2775 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ICR_BERRCF

#define MCCI_STM32H7_I2C_ICR_BERRCF   (UINT32_C(1) << 8)

Bus error flag clear.

Definition at line 2776 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ICR_NACKCF

#define MCCI_STM32H7_I2C_ICR_NACKCF   (UINT32_C(1) << 4)

Not Acknowledge flag clear.

Definition at line 2779 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ICR_OVRCF

#define MCCI_STM32H7_I2C_ICR_OVRCF   (UINT32_C(1) << 10)

Overrun/Underrun flag clear.

Definition at line 2774 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ICR_PECCF

#define MCCI_STM32H7_I2C_ICR_PECCF   (UINT32_C(1) << 11)

PEC Error flag clear.

Definition at line 2773 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ICR_RSV0

#define MCCI_STM32H7_I2C_ICR_RSV0   (UINT32_C(7) << 0)

reserved, don't change

Definition at line 2781 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ICR_RSV14

#define MCCI_STM32H7_I2C_ICR_RSV14   UINT32_C(0xFFFFC000)

reserved, don't change

Definition at line 2770 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ICR_RSV6

#define MCCI_STM32H7_I2C_ICR_RSV6   (UINT32_C(3) << 6)

reserved, don't change

Definition at line 2777 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ICR_STOPCF

#define MCCI_STM32H7_I2C_ICR_STOPCF   (UINT32_C(1) << 5)

STOP detection flag clear.

Definition at line 2778 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ICR_TIMEOUTCF

#define MCCI_STM32H7_I2C_ICR_TIMEOUTCF   (UINT32_C(1) << 12)

Timeout detection flag clear.

Definition at line 2772 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ISR

#define MCCI_STM32H7_I2C_ISR   UINT32_C(0x18)

offset to I2C interrupt and status register

Definition at line 2644 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ISR_ADDCODE

#define MCCI_STM32H7_I2C_ISR_ADDCODE   (UINT32_C(0x7F) << 17)

Address match code (Slave mode)

Definition at line 2748 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ISR_ADDR

#define MCCI_STM32H7_I2C_ISR_ADDR   (UINT32_C(1) << 3)

Address matched (slave mode)

Definition at line 2762 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ISR_ALERT

#define MCCI_STM32H7_I2C_ISR_ALERT   (UINT32_C(1) << 13)

SMBus alert.

Definition at line 2752 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ISR_ARLO

#define MCCI_STM32H7_I2C_ISR_ARLO   (UINT32_C(1) << 9)

Arbitration lost.

Definition at line 2756 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ISR_BERR

#define MCCI_STM32H7_I2C_ISR_BERR   (UINT32_C(1) << 8)

Bus error.

Definition at line 2757 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ISR_BUSY

#define MCCI_STM32H7_I2C_ISR_BUSY   (UINT32_C(1) << 15)

Bus busy.

Definition at line 2750 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ISR_DIR

#define MCCI_STM32H7_I2C_ISR_DIR   (UINT32_C(1) << 16)

Transfer direction (Slave mode)

Definition at line 2749 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ISR_NACKF

#define MCCI_STM32H7_I2C_ISR_NACKF   (UINT32_C(1) << 4)

Not Acknowledge received flag.

Definition at line 2761 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ISR_OVR

#define MCCI_STM32H7_I2C_ISR_OVR   (UINT32_C(1) << 10)

Overrun/Underrun (slave mode)

Definition at line 2755 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ISR_PECERR

#define MCCI_STM32H7_I2C_ISR_PECERR   (UINT32_C(1) << 11)

PEC Error in reception.

Definition at line 2754 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ISR_RSV14

#define MCCI_STM32H7_I2C_ISR_RSV14   (UINT32_C(1) << 14)

reserved, don't change

Definition at line 2751 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ISR_RSV24

#define MCCI_STM32H7_I2C_ISR_RSV24   UINT32_C(0xFF000000)

reserved, don't change

Definition at line 2747 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ISR_RXNE

#define MCCI_STM32H7_I2C_ISR_RXNE   (UINT32_C(1) << 2)

Receive data register not empty (receivers)

Definition at line 2763 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ISR_STOPF

#define MCCI_STM32H7_I2C_ISR_STOPF   (UINT32_C(1) << 5)

Stop detection flag.

Definition at line 2760 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ISR_TC

#define MCCI_STM32H7_I2C_ISR_TC   (UINT32_C(1) << 6)

Transfer Complete (master mode)

Definition at line 2759 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ISR_TCR

#define MCCI_STM32H7_I2C_ISR_TCR   (UINT32_C(1) << 7)

Transfer Complete Reload.

Definition at line 2758 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ISR_TIMEOUT

#define MCCI_STM32H7_I2C_ISR_TIMEOUT   (UINT32_C(1) << 12)

Timeout or tLOW detection flag.

Definition at line 2753 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ISR_TXE

#define MCCI_STM32H7_I2C_ISR_TXE   (UINT32_C(1) << 0)

Transmit data register empty (transmitters)

Definition at line 2765 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_ISR_TXIS

#define MCCI_STM32H7_I2C_ISR_TXIS   (UINT32_C(1) << 1)

Transmit interrupt status (transmitters)

Definition at line 2764 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_OAR1

#define MCCI_STM32H7_I2C_OAR1   UINT32_C(0x08)

offset to I2C own address 1 register

Definition at line 2640 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_OAR1_OA1

#define MCCI_STM32H7_I2C_OAR1_OA1   (UINT32_C(0x3FF) << 0)

Interface own slave address.

Definition at line 2702 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_OAR1_OA1_N

#define MCCI_STM32H7_I2C_OAR1_OA1_N (   n)    ((n) << 0)

Definition at line 2703 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_OAR1_OA1EN

#define MCCI_STM32H7_I2C_OAR1_OA1EN   (UINT32_C(1) << 15)

Own Address 1 enable.

Definition at line 2699 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_OAR1_OA1MODE

#define MCCI_STM32H7_I2C_OAR1_OA1MODE   (UINT32_C(1) << 10)

Own Address 1 10-bit mode.

Definition at line 2701 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_OAR1_RSV11

#define MCCI_STM32H7_I2C_OAR1_RSV11   (UINT32_C(0xF) << 11)

reserved, don't change

Definition at line 2700 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_OAR1_RSV16

#define MCCI_STM32H7_I2C_OAR1_RSV16   UINT32_C(0xFFFF0000)

reserved, don't change

Definition at line 2698 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_OAR2

#define MCCI_STM32H7_I2C_OAR2   UINT32_C(0x0C)

offset to I2C own address 2 register

Definition at line 2641 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_OAR2_OA2

#define MCCI_STM32H7_I2C_OAR2_OA2   (UINT32_C(0xFF) << 0)

Interface address.

Definition at line 2713 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_OAR2_OA2_N

#define MCCI_STM32H7_I2C_OAR2_OA2_N (   n)    ((n) << 0)

Definition at line 2714 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_OAR2_OA2EN

#define MCCI_STM32H7_I2C_OAR2_OA2EN   (UINT32_C(1) << 15)

Own Address 2 enable.

Definition at line 2709 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_OAR2_OA2MSK

#define MCCI_STM32H7_I2C_OAR2_OA2MSK   (UINT32_C(7) << 8)

Own Address 2 masks.

Definition at line 2711 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_OAR2_OA2MSK_N

#define MCCI_STM32H7_I2C_OAR2_OA2MSK_N (   n)    ((n) << 8)

Definition at line 2712 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_OAR2_RSV11

#define MCCI_STM32H7_I2C_OAR2_RSV11   (UINT32_C(0xF) << 11)

reserved, don't change

Definition at line 2710 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_OAR2_RSV16

#define MCCI_STM32H7_I2C_OAR2_RSV16   UINT32_C(0xFFFF0000)

reserved, don't change

Definition at line 2708 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_PECR

#define MCCI_STM32H7_I2C_PECR   UINT32_C(0x20)

offset to I2C PEC register

Definition at line 2646 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_PECR_PEC

#define MCCI_STM32H7_I2C_PECR_PEC   (UINT32_C(0xFF) << 0)

Packet error checking register.

Definition at line 2787 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_PECR_RSV8

#define MCCI_STM32H7_I2C_PECR_RSV8   UINT32_C(0xFFFFFF00)

reserved, don't change

Definition at line 2786 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_RXDR

#define MCCI_STM32H7_I2C_RXDR   UINT32_C(0x24)

offset to I2C receive data register

Definition at line 2647 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_RXDR_RSV8

#define MCCI_STM32H7_I2C_RXDR_RSV8   UINT32_C(0xFFFFFF00)

reserved, don't change

Definition at line 2792 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_RXDR_RXDATA

#define MCCI_STM32H7_I2C_RXDR_RXDATA   (UINT32_C(0xFF) << 0)

8-bit receive data

Definition at line 2793 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMEOUTR_RSV28

#define MCCI_STM32H7_I2C_TIMEOUTR_RSV28   (UINT32_C(7) << 28)

reserved, don't change

Definition at line 2735 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMEOUTR_TEXTEN

#define MCCI_STM32H7_I2C_TIMEOUTR_TEXTEN   (UINT32_C(1) << 31)

Extended clock timeout enable.

Definition at line 2734 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMEOUTR_TIDLE

#define MCCI_STM32H7_I2C_TIMEOUTR_TIDLE   (UINT32_C(1) << 12)

Idle clock timeout detection.

Definition at line 2740 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMEOUTR_TIMEOUTA

#define MCCI_STM32H7_I2C_TIMEOUTR_TIMEOUTA   (UINT32_C(0xFFF) << 0)

Bus Timeout A.

Definition at line 2741 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMEOUTR_TIMEOUTA_N

#define MCCI_STM32H7_I2C_TIMEOUTR_TIMEOUTA_N (   n)    ((n) << 0)

Definition at line 2742 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMEOUTR_TIMEOUTB

#define MCCI_STM32H7_I2C_TIMEOUTR_TIMEOUTB   (UINT32_C(0xFFF) << 16)

Bus timeout B.

Definition at line 2736 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMEOUTR_TIMEOUTB_N

#define MCCI_STM32H7_I2C_TIMEOUTR_TIMEOUTB_N (   n)    ((n) << 16)

Definition at line 2737 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMEOUTR_TIMOUTEN

#define MCCI_STM32H7_I2C_TIMEOUTR_TIMOUTEN   (UINT32_C(1) << 15)

Clock timeout enable.

Definition at line 2738 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMINGR

#define MCCI_STM32H7_I2C_TIMINGR   UINT32_C(0x10)

offset to I2C timing register

Definition at line 2642 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMINGR_PRESC

#define MCCI_STM32H7_I2C_TIMINGR_PRESC   (UINT32_C(0xF) << 28)

Timing prescaler.

Definition at line 2719 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMINGR_PRESC_N

#define MCCI_STM32H7_I2C_TIMINGR_PRESC_N (   n)    ((n) << 28)

Definition at line 2720 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMINGR_RSV13

#define MCCI_STM32H7_I2C_TIMINGR_RSV13   (UINT32_C(3) << 13)

reserved, don't change

Definition at line 2739 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMINGR_RSV24

#define MCCI_STM32H7_I2C_TIMINGR_RSV24   (UINT32_C(0xF) << 24)

reserved, don't change

Definition at line 2721 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMINGR_SCLDEL

#define MCCI_STM32H7_I2C_TIMINGR_SCLDEL   (UINT32_C(0xF) << 20)

Data setup time.

Definition at line 2722 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMINGR_SCLDEL_N

#define MCCI_STM32H7_I2C_TIMINGR_SCLDEL_N (   n)    ((n) << 20)

Definition at line 2723 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMINGR_SCLH

#define MCCI_STM32H7_I2C_TIMINGR_SCLH   (UINT32_C(0xFF) << 8)

SCL high period (master mode)

Definition at line 2726 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMINGR_SCLH_N

#define MCCI_STM32H7_I2C_TIMINGR_SCLH_N (   n)    ((n) << 8)

Definition at line 2727 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMINGR_SCLL

#define MCCI_STM32H7_I2C_TIMINGR_SCLL   (UINT32_C(0xFF) << 0)

SCL low period (master mode)

Definition at line 2728 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMINGR_SCLL_N

#define MCCI_STM32H7_I2C_TIMINGR_SCLL_N (   n)    ((n) << 0)

Definition at line 2729 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMINGR_SDADEL

#define MCCI_STM32H7_I2C_TIMINGR_SDADEL   (UINT32_C(0xF) << 16)

Data hold time.

Definition at line 2724 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMINGR_SDADEL_N

#define MCCI_STM32H7_I2C_TIMINGR_SDADEL_N (   n)    ((n) << 16)

Definition at line 2725 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TIMOUTR

#define MCCI_STM32H7_I2C_TIMOUTR   UINT32_C(0x14)

offset to I2C timeout register

Definition at line 2643 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TXDR

#define MCCI_STM32H7_I2C_TXDR   UINT32_C(0x28)

offset to I2C transmit data register

Definition at line 2648 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TXDR_RSV8

#define MCCI_STM32H7_I2C_TXDR_RSV8   UINT32_C(0xFFFFFF00)

reserved, don't change

Definition at line 2798 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_I2C_TXDR_TXDATA

#define MCCI_STM32H7_I2C_TXDR_TXDATA   (UINT32_C(0xFF) << 0)

8-bit transmit data

Definition at line 2799 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_ADC

#define MCCI_STM32H7_IRQ_ADC   UINT32_C(18)

ADC1 and ADC2 global Interrupts.

Definition at line 3066 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_BDMA1

#define MCCI_STM32H7_IRQ_BDMA1   UINT32_C(154)

BDMA1 for DFSM global interrupt.

Definition at line 3184 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_BDMA2_Channel0

#define MCCI_STM32H7_IRQ_BDMA2_Channel0   UINT32_C(129)

BDMA2 Channel 0 global Interrupt.

Definition at line 3161 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_BDMA2_Channel1

#define MCCI_STM32H7_IRQ_BDMA2_Channel1   UINT32_C(130)

BDMA2 Channel 1 global Interrupt.

Definition at line 3162 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_BDMA2_Channel2

#define MCCI_STM32H7_IRQ_BDMA2_Channel2   UINT32_C(131)

BDMA2 Channel 2 global Interrupt.

Definition at line 3163 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_BDMA2_Channel3

#define MCCI_STM32H7_IRQ_BDMA2_Channel3   UINT32_C(132)

BDMA2 Channel 3 global Interrupt.

Definition at line 3164 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_BDMA2_Channel4

#define MCCI_STM32H7_IRQ_BDMA2_Channel4   UINT32_C(133)

BDMA2 Channel 4 global Interrupt.

Definition at line 3165 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_BDMA2_Channel5

#define MCCI_STM32H7_IRQ_BDMA2_Channel5   UINT32_C(134)

BDMA2 Channel 5 global Interrupt.

Definition at line 3166 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_BDMA2_Channel6

#define MCCI_STM32H7_IRQ_BDMA2_Channel6   UINT32_C(135)

BDMA2 Channel 6 global Interrupt.

Definition at line 3167 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_BDMA2_Channel7

#define MCCI_STM32H7_IRQ_BDMA2_Channel7   UINT32_C(136)

BDMA2 Channel 7 global Interrupt.

Definition at line 3168 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_CEC

#define MCCI_STM32H7_IRQ_CEC   UINT32_C(94)

HDMI-CEC global Interrupt.

Definition at line 3140 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_COMP

#define MCCI_STM32H7_IRQ_COMP   UINT32_C(137)

COMP global Interrupt.

Definition at line 3169 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_CRS

#define MCCI_STM32H7_IRQ_CRS   UINT32_C(144)

Clock Recovery Global Interrupt.

Definition at line 3176 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_CRYP

#define MCCI_STM32H7_IRQ_CRYP   UINT32_C(79)

CRYP crypto global interrupt.

Definition at line 3125 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DAC2

#define MCCI_STM32H7_IRQ_DAC2   UINT32_C(127)

DAC2 global Interrupt.

Definition at line 3159 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DCMI_PSSI

#define MCCI_STM32H7_IRQ_DCMI_PSSI   UINT32_C(78)

DCMI and PSSI global interrupt.

Definition at line 3124 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DFSDM1_FLT0

#define MCCI_STM32H7_IRQ_DFSDM1_FLT0   UINT32_C(110)

DFSDM Filter1 Interrupt.

Definition at line 3145 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DFSDM1_FLT1

#define MCCI_STM32H7_IRQ_DFSDM1_FLT1   UINT32_C(111)

DFSDM Filter2 Interrupt.

Definition at line 3146 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DFSDM1_FLT2

#define MCCI_STM32H7_IRQ_DFSDM1_FLT2   UINT32_C(112)

DFSDM Filter3 Interrupt.

Definition at line 3147 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DFSDM1_FLT3

#define MCCI_STM32H7_IRQ_DFSDM1_FLT3   UINT32_C(113)

DFSDM Filter4 Interrupt.

Definition at line 3148 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DFSDM1_FLT4

#define MCCI_STM32H7_IRQ_DFSDM1_FLT4   UINT32_C(64)

DFSDM Filter4 Interrupt.

Definition at line 3110 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DFSDM1_FLT5

#define MCCI_STM32H7_IRQ_DFSDM1_FLT5   UINT32_C(65)

DFSDM Filter5 Interrupt.

Definition at line 3111 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DFSDM1_FLT6

#define MCCI_STM32H7_IRQ_DFSDM1_FLT6   UINT32_C(66)

DFSDM Filter6 Interrupt.

Definition at line 3112 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DFSDM1_FLT7

#define MCCI_STM32H7_IRQ_DFSDM1_FLT7   UINT32_C(67)

DFSDM Filter7 Interrupt.

Definition at line 3113 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DFSDM2

#define MCCI_STM32H7_IRQ_DFSDM2   UINT32_C(42)

DFSDM2 global Interrupt.

Definition at line 3090 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DMA1_Stream0

#define MCCI_STM32H7_IRQ_DMA1_Stream0   UINT32_C(11)

DMA1 Stream 0 global Interrupt.

Definition at line 3059 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DMA1_Stream1

#define MCCI_STM32H7_IRQ_DMA1_Stream1   UINT32_C(12)

DMA1 Stream 1 global Interrupt.

Definition at line 3060 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DMA1_Stream2

#define MCCI_STM32H7_IRQ_DMA1_Stream2   UINT32_C(13)

DMA1 Stream 2 global Interrupt.

Definition at line 3061 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DMA1_Stream3

#define MCCI_STM32H7_IRQ_DMA1_Stream3   UINT32_C(14)

DMA1 Stream 3 global Interrupt.

Definition at line 3062 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DMA1_Stream4

#define MCCI_STM32H7_IRQ_DMA1_Stream4   UINT32_C(15)

DMA1 Stream 4 global Interrupt.

Definition at line 3063 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DMA1_Stream5

#define MCCI_STM32H7_IRQ_DMA1_Stream5   UINT32_C(16)

DMA1 Stream 5 global Interrupt.

Definition at line 3064 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DMA1_Stream6

#define MCCI_STM32H7_IRQ_DMA1_Stream6   UINT32_C(17)

DMA1 Stream 6 global Interrupt.

Definition at line 3065 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DMA1_Stream7

#define MCCI_STM32H7_IRQ_DMA1_Stream7   UINT32_C(47)

DMA1 Stream7 Interrupt.

Definition at line 3095 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DMA2_Stream0

#define MCCI_STM32H7_IRQ_DMA2_Stream0   UINT32_C(56)

DMA2 Stream 0 global Interrupt.

Definition at line 3104 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DMA2_Stream1

#define MCCI_STM32H7_IRQ_DMA2_Stream1   UINT32_C(57)

DMA2 Stream 1 global Interrupt.

Definition at line 3105 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DMA2_Stream2

#define MCCI_STM32H7_IRQ_DMA2_Stream2   UINT32_C(58)

DMA2 Stream 2 global Interrupt.

Definition at line 3106 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DMA2_Stream3

#define MCCI_STM32H7_IRQ_DMA2_Stream3   UINT32_C(59)

DMA2 Stream 3 global Interrupt.

Definition at line 3107 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DMA2_Stream4

#define MCCI_STM32H7_IRQ_DMA2_Stream4   UINT32_C(60)

DMA2 Stream 4 global Interrupt.

Definition at line 3108 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DMA2_Stream5

#define MCCI_STM32H7_IRQ_DMA2_Stream5   UINT32_C(68)

DMA2 Stream 5 global interrupt.

Definition at line 3114 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DMA2_Stream6

#define MCCI_STM32H7_IRQ_DMA2_Stream6   UINT32_C(69)

DMA2 Stream 6 global interrupt.

Definition at line 3115 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DMA2_Stream7

#define MCCI_STM32H7_IRQ_DMA2_Stream7   UINT32_C(70)

DMA2 Stream 7 global interrupt.

Definition at line 3116 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DMA2D

#define MCCI_STM32H7_IRQ_DMA2D   UINT32_C(90)

DMA2D global Interrupt.

Definition at line 3136 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DMAMUX1_OVR

#define MCCI_STM32H7_IRQ_DMAMUX1_OVR   UINT32_C(102)

DMAMUX1 Overrun interrupt.

Definition at line 3144 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DMAMUX2_OVR

#define MCCI_STM32H7_IRQ_DMAMUX2_OVR   UINT32_C(128)

DMAMUX2 Overrun interrupt.

Definition at line 3160 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_DTS

#define MCCI_STM32H7_IRQ_DTS   UINT32_C(147)

Digital Temperature Sensor Global Interrupt.

Definition at line 3178 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_ECC

#define MCCI_STM32H7_IRQ_ECC   UINT32_C(145)

ECC diagnostic Global Interrupt.

Definition at line 3177 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_EXTI0

#define MCCI_STM32H7_IRQ_EXTI0   UINT32_C(6)

EXTI Line0 Interrupt.

Definition at line 3054 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_EXTI1

#define MCCI_STM32H7_IRQ_EXTI1   UINT32_C(7)

EXTI Line1 Interrupt.

Definition at line 3055 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_EXTI15_10

#define MCCI_STM32H7_IRQ_EXTI15_10   UINT32_C(40)

External Line[15:10] Interrupts.

Definition at line 3088 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_EXTI2

#define MCCI_STM32H7_IRQ_EXTI2   UINT32_C(8)

EXTI Line2 Interrupt.

Definition at line 3056 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_EXTI3

#define MCCI_STM32H7_IRQ_EXTI3   UINT32_C(9)

EXTI Line3 Interrupt.

Definition at line 3057 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_EXTI4

#define MCCI_STM32H7_IRQ_EXTI4   UINT32_C(10)

EXTI Line4 Interrupt.

Definition at line 3058 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_EXTI9_5

#define MCCI_STM32H7_IRQ_EXTI9_5   UINT32_C(23)

External Line[9:5] Interrupts.

Definition at line 3071 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_FDCAN1_IT0

#define MCCI_STM32H7_IRQ_FDCAN1_IT0   UINT32_C(19)

FDCAN1 Interrupt line 0.

Definition at line 3067 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_FDCAN1_IT1

#define MCCI_STM32H7_IRQ_FDCAN1_IT1   UINT32_C(21)

FDCAN1 Interrupt line 1.

Definition at line 3069 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_FDCAN2_IT0

#define MCCI_STM32H7_IRQ_FDCAN2_IT0   UINT32_C(20)

FDCAN2 Interrupt line 0.

Definition at line 3068 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_FDCAN2_IT1

#define MCCI_STM32H7_IRQ_FDCAN2_IT1   UINT32_C(22)

FDCAN2 Interrupt line 1.

Definition at line 3070 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_FDCAN_CAL

#define MCCI_STM32H7_IRQ_FDCAN_CAL   UINT32_C(63)

FDCAN Calibration unit Interrupt.

Definition at line 3109 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_FLASH

#define MCCI_STM32H7_IRQ_FLASH   UINT32_C(4)

FLASH global Interrupt.

Definition at line 3052 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_FMC

#define MCCI_STM32H7_IRQ_FMC   UINT32_C(48)

FMC global Interrupt.

Definition at line 3096 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_FPU

#define MCCI_STM32H7_IRQ_FPU   UINT32_C(81)

FPU global interrupt.

Definition at line 3127 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_GFXMMU

#define MCCI_STM32H7_IRQ_GFXMMU   UINT32_C(153)

GFXMMU global interrupt.

Definition at line 3183 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_HASH_RNG

#define MCCI_STM32H7_IRQ_HASH_RNG   UINT32_C(80)

HASH and RNG global interrupt.

Definition at line 3126 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_HSEM1

#define MCCI_STM32H7_IRQ_HSEM1   UINT32_C(125)

HSEM1 global Interrupt.

Definition at line 3158 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_I2C1_ER

#define MCCI_STM32H7_IRQ_I2C1_ER   UINT32_C(32)

I2C1 Error Interrupt.

Definition at line 3080 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_I2C1_EV

#define MCCI_STM32H7_IRQ_I2C1_EV   UINT32_C(31)

I2C1 Event Interrupt.

Definition at line 3079 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_I2C2_ER

#define MCCI_STM32H7_IRQ_I2C2_ER   UINT32_C(34)

I2C2 Error Interrupt.

Definition at line 3082 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_I2C2_EV

#define MCCI_STM32H7_IRQ_I2C2_EV   UINT32_C(33)

I2C2 Event Interrupt.

Definition at line 3081 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_I2C3_ER

#define MCCI_STM32H7_IRQ_I2C3_ER   UINT32_C(73)

I2C3 error interrupt.

Definition at line 3119 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_I2C3_EV

#define MCCI_STM32H7_IRQ_I2C3_EV   UINT32_C(72)

I2C3 event interrupt.

Definition at line 3118 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_I2C4_ER

#define MCCI_STM32H7_IRQ_I2C4_ER   UINT32_C(96)

I2C4 Error Interrupt.

Definition at line 3142 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_I2C4_EV

#define MCCI_STM32H7_IRQ_I2C4_EV   UINT32_C(95)

I2C4 Event Interrupt.

Definition at line 3141 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_JPEG

#define MCCI_STM32H7_IRQ_JPEG   UINT32_C(121)

JPEG global Interrupt.

Definition at line 3155 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_LPTIM1

#define MCCI_STM32H7_IRQ_LPTIM1   UINT32_C(93)

LP TIM1 interrupt.

Definition at line 3139 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_LPTIM2

#define MCCI_STM32H7_IRQ_LPTIM2   UINT32_C(138)

LP TIM2 global interrupt.

Definition at line 3170 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_LPTIM3

#define MCCI_STM32H7_IRQ_LPTIM3   UINT32_C(139)

LP TIM3 global interrupt.

Definition at line 3171 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_LPUART1

#define MCCI_STM32H7_IRQ_LPUART1   UINT32_C(142)

LP UART1 interrupt.

Definition at line 3174 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_LTDC

#define MCCI_STM32H7_IRQ_LTDC   UINT32_C(88)

LTDC global Interrupt.

Definition at line 3134 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_LTDC_ER

#define MCCI_STM32H7_IRQ_LTDC_ER   UINT32_C(89)

LTDC Error global Interrupt.

Definition at line 3135 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_MDIOS

#define MCCI_STM32H7_IRQ_MDIOS   UINT32_C(120)

MDIOS global Interrupt.

Definition at line 3154 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_MDIOS_WKUP

#define MCCI_STM32H7_IRQ_MDIOS_WKUP   UINT32_C(119)

MDIOS Wakeup Interrupt.

Definition at line 3153 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_MDMA

#define MCCI_STM32H7_IRQ_MDMA   UINT32_C(122)

MDMA global Interrupt.

Definition at line 3156 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_OCTOSPI1

#define MCCI_STM32H7_IRQ_OCTOSPI1   UINT32_C(92)

OCTOSPI1 global interrupt.

Definition at line 3138 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_OCTOSPI2

#define MCCI_STM32H7_IRQ_OCTOSPI2   UINT32_C(150)

OctoSPI2 global interrupt.

Definition at line 3180 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_OTFDEC1

#define MCCI_STM32H7_IRQ_OTFDEC1   UINT32_C(151)

OTFDEC1 global interrupt.

Definition at line 3181 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_OTFDEC2

#define MCCI_STM32H7_IRQ_OTFDEC2   UINT32_C(152)

OTFDEC2 global interrupt.

Definition at line 3182 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_OTG_HS

#define MCCI_STM32H7_IRQ_OTG_HS   UINT32_C(77)

USB OTG HS global interrupt.

Definition at line 3123 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_OTG_HS_EP1_IN

#define MCCI_STM32H7_IRQ_OTG_HS_EP1_IN   UINT32_C(75)

USB OTG HS End Point 1 In global interrupt.

Definition at line 3121 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_OTG_HS_EP1_OUT

#define MCCI_STM32H7_IRQ_OTG_HS_EP1_OUT   UINT32_C(74)

USB OTG HS End Point 1 Out global interrupt.

Definition at line 3120 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_OTG_HS_WKUP

#define MCCI_STM32H7_IRQ_OTG_HS_WKUP   UINT32_C(76)

USB OTG HS Wakeup through EXTI interrupt.

Definition at line 3122 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_PVD_PVM

#define MCCI_STM32H7_IRQ_PVD_PVM   UINT32_C(1)

PVD/PVM through EXTI Line detection Interrupt.

Definition at line 3049 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_RCC

#define MCCI_STM32H7_IRQ_RCC   UINT32_C(5)

RCC global Interrupt.

Definition at line 3053 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_RTC_Alarm

#define MCCI_STM32H7_IRQ_RTC_Alarm   UINT32_C(41)

RTC Alarm (A and B) through EXTI Line Interrupt.

Definition at line 3089 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_RTC_TAMP_STAMP_CSS_LSE

#define MCCI_STM32H7_IRQ_RTC_TAMP_STAMP_CSS_LSE   UINT32_C(2)

Tamper, TimeStamp, CSS and LSE interrupts through the EXTI line.

Definition at line 3050 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_RTC_WKUP

#define MCCI_STM32H7_IRQ_RTC_WKUP   UINT32_C(3)

RTC Wakeup interrupt through the EXTI line.

Definition at line 3051 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_SAI1

#define MCCI_STM32H7_IRQ_SAI1   UINT32_C(87)

SAI1 global Interrupt.

Definition at line 3133 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_SAI2

#define MCCI_STM32H7_IRQ_SAI2   UINT32_C(91)

SAI2 global Interrupt.

Definition at line 3137 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_SDMMC1

#define MCCI_STM32H7_IRQ_SDMMC1   UINT32_C(49)

SDMMC1 global Interrupt.

Definition at line 3097 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_SDMMC2

#define MCCI_STM32H7_IRQ_SDMMC2   UINT32_C(124)

SDMMC2 global Interrupt.

Definition at line 3157 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_SPDIF_RX

#define MCCI_STM32H7_IRQ_SPDIF_RX   UINT32_C(97)

SPDIF-RX global Interrupt.

Definition at line 3143 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_SPI1

#define MCCI_STM32H7_IRQ_SPI1   UINT32_C(35)

SPI1 global Interrupt.

Definition at line 3083 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_SPI2

#define MCCI_STM32H7_IRQ_SPI2   UINT32_C(36)

SPI2 global Interrupt.

Definition at line 3084 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_SPI3

#define MCCI_STM32H7_IRQ_SPI3   UINT32_C(51)

SPI3 global Interrupt.

Definition at line 3099 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_SPI4

#define MCCI_STM32H7_IRQ_SPI4   UINT32_C(84)

SPI4 global Interrupt.

Definition at line 3130 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_SPI5

#define MCCI_STM32H7_IRQ_SPI5   UINT32_C(85)

SPI5 global Interrupt.

Definition at line 3131 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_SPI6

#define MCCI_STM32H7_IRQ_SPI6   UINT32_C(86)

SPI6 global Interrupt.

Definition at line 3132 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_SWPMI1

#define MCCI_STM32H7_IRQ_SWPMI1   UINT32_C(115)

Serial Wire Interface 1 global interrupt.

Definition at line 3149 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_TIM15

#define MCCI_STM32H7_IRQ_TIM15   UINT32_C(116)

TIM15 global Interrupt.

Definition at line 3150 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_TIM16

#define MCCI_STM32H7_IRQ_TIM16   UINT32_C(117)

TIM16 global Interrupt.

Definition at line 3151 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_TIM17

#define MCCI_STM32H7_IRQ_TIM17   UINT32_C(118)

TIM17 global Interrupt.

Definition at line 3152 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_TIM1_BRK

#define MCCI_STM32H7_IRQ_TIM1_BRK   UINT32_C(24)

TIM1 Break Interrupt.

Definition at line 3072 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_TIM1_CC

#define MCCI_STM32H7_IRQ_TIM1_CC   UINT32_C(27)

TIM1 Capture Compare Interrupt.

Definition at line 3075 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_TIM1_TRG_COM

#define MCCI_STM32H7_IRQ_TIM1_TRG_COM   UINT32_C(26)

TIM1 Trigger and Commutation Interrupt.

Definition at line 3074 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_TIM1_UP

#define MCCI_STM32H7_IRQ_TIM1_UP   UINT32_C(25)

TIM1 Update Interrupt.

Definition at line 3073 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_TIM2

#define MCCI_STM32H7_IRQ_TIM2   UINT32_C(28)

TIM2 global Interrupt.

Definition at line 3076 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_TIM3

#define MCCI_STM32H7_IRQ_TIM3   UINT32_C(29)

TIM3 global Interrupt.

Definition at line 3077 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_TIM4

#define MCCI_STM32H7_IRQ_TIM4   UINT32_C(30)

TIM4 global Interrupt.

Definition at line 3078 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_TIM5

#define MCCI_STM32H7_IRQ_TIM5   UINT32_C(50)

TIM5 global Interrupt.

Definition at line 3098 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_TIM6_DAC

#define MCCI_STM32H7_IRQ_TIM6_DAC   UINT32_C(54)

TIM6 global and DAC1&2 underrun error interrupts.

Definition at line 3102 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_TIM7

#define MCCI_STM32H7_IRQ_TIM7   UINT32_C(55)

TIM7 global interrupt.

Definition at line 3103 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_TIM8_BRK_TIM12

#define MCCI_STM32H7_IRQ_TIM8_BRK_TIM12   UINT32_C(43)

TIM8 Break Interrupt and TIM12 global interrupt.

Definition at line 3091 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_TIM8_CC

#define MCCI_STM32H7_IRQ_TIM8_CC   UINT32_C(46)

TIM8 Capture Compare Interrupt.

Definition at line 3094 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_TIM8_TRG_COM_TIM14

#define MCCI_STM32H7_IRQ_TIM8_TRG_COM_TIM14   UINT32_C(45)

TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt.

Definition at line 3093 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_TIM8_UP_TIM13

#define MCCI_STM32H7_IRQ_TIM8_UP_TIM13   UINT32_C(44)

TIM8 Update Interrupt and TIM13 global interrupt.

Definition at line 3092 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_UART4

#define MCCI_STM32H7_IRQ_UART4   UINT32_C(52)

UART4 global Interrupt.

Definition at line 3100 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_UART5

#define MCCI_STM32H7_IRQ_UART5   UINT32_C(53)

UART5 global Interrupt.

Definition at line 3101 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_UART7

#define MCCI_STM32H7_IRQ_UART7   UINT32_C(82)

UART7 global interrupt.

Definition at line 3128 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_UART8

#define MCCI_STM32H7_IRQ_UART8   UINT32_C(83)

UART8 global interrupt.

Definition at line 3129 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_UART9

#define MCCI_STM32H7_IRQ_UART9   UINT32_C(140)

UART9 global interrupt.

Definition at line 3172 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_USART1

#define MCCI_STM32H7_IRQ_USART1   UINT32_C(37)

USART1 global Interrupt.

Definition at line 3085 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_USART10

#define MCCI_STM32H7_IRQ_USART10   UINT32_C(141)

USART10 global interrupt.

Definition at line 3173 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_USART2

#define MCCI_STM32H7_IRQ_USART2   UINT32_C(38)

USART2 global Interrupt.

Definition at line 3086 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_USART3

#define MCCI_STM32H7_IRQ_USART3   UINT32_C(39)

USART3 global Interrupt.

Definition at line 3087 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_USART6

#define MCCI_STM32H7_IRQ_USART6   UINT32_C(71)

USART6 global interrupt.

Definition at line 3117 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_WAKEUP_PIN

#define MCCI_STM32H7_IRQ_WAKEUP_PIN   UINT32_C(149)

Interrupt for all 6 wake-up pins.

Definition at line 3179 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_WWDG

#define MCCI_STM32H7_IRQ_WWDG   UINT32_C(0)

Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)

Definition at line 3048 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_IRQ_WWDG_RST

#define MCCI_STM32H7_IRQ_WWDG_RST   UINT32_C(143)

Window Watchdog Event interrupt.

Definition at line 3175 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_MEMORY_AHB_SRAM1

#define MCCI_STM32H7_MEMORY_AHB_SRAM1   UINT32_C(0x30000000)

AHB SRAM1 (up to 64K)

Definition at line 63 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_MEMORY_AHB_SRAM2

#define MCCI_STM32H7_MEMORY_AHB_SRAM2   UINT32_C(0x30010000)

AHB SRAM2 (up to 64K)

Definition at line 64 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_MEMORY_AXI_SRAM1

#define MCCI_STM32H7_MEMORY_AXI_SRAM1   UINT32_C(0x24000000)

AXI SRAM1 (up to 256K)

Definition at line 60 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_MEMORY_AXI_SRAM2

#define MCCI_STM32H7_MEMORY_AXI_SRAM2   UINT32_C(0x24040000)

AXI SRAM2 (up to 384K)

Definition at line 61 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_MEMORY_AXI_SRAM3

#define MCCI_STM32H7_MEMORY_AXI_SRAM3   UINT32_C(0x240A0000)

AXI SRAM3 (up to 384K)

Definition at line 62 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_MEMORY_DTCM_RAM

#define MCCI_STM32H7_MEMORY_DTCM_RAM   UINT32_C(0x20000000)

DTCM RAM (128K)

Definition at line 59 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_MEMORY_FLASH

#define MCCI_STM32H7_MEMORY_FLASH   UINT32_C(0x08000000)

Flash program memory (up to 2M)

Definition at line 49 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_MEMORY_FLASH1

#define MCCI_STM32H7_MEMORY_FLASH1   UINT32_C(0x08000000)

Flash program memory (up to 1M)

Definition at line 50 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_MEMORY_FLASH2

#define MCCI_STM32H7_MEMORY_FLASH2   UINT32_C(0x08100000)

Flash program memory (up to 1M)

Definition at line 51 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_MEMORY_FLASH_END

#define MCCI_STM32H7_MEMORY_FLASH_END   UINT32_C(0x081FFFFF)

End of Flash program memory.

Definition at line 52 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_MEMORY_ITCM_RAM

#define MCCI_STM32H7_MEMORY_ITCM_RAM   UINT32_C(0x00000000)

ITCM RAM (64K)

Definition at line 58 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_MEMORY_OTP

#define MCCI_STM32H7_MEMORY_OTP   UINT32_C(0x08FFF000)

OTP Area (1K)

Definition at line 55 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_MEMORY_OTP_END

#define MCCI_STM32H7_MEMORY_OTP_END   UINT32_C(0x08FFF3FF)

End of OTP Area.

Definition at line 56 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_MEMORY_READ_ONLY

#define MCCI_STM32H7_MEMORY_READ_ONLY   UINT32_C(0x08FFF800)

read-only area (512)

Definition at line 57 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_MEMORY_SRD_BKPSRAM

#define MCCI_STM32H7_MEMORY_SRD_BKPSRAM   UINT32_C(0x38800000)

SRD Backup SRAM (up to 4K)

Definition at line 66 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_MEMORY_SRD_SRAM

#define MCCI_STM32H7_MEMORY_SRD_SRAM   UINT32_C(0x38000000)

SRD SRAM (up to 32K)

Definition at line 65 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_MEMORY_SYSTEM

#define MCCI_STM32H7_MEMORY_SYSTEM   UINT32_C(0x1FF00000)

System memory (128K)

Definition at line 53 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_MEMORY_SYSTEM_END

#define MCCI_STM32H7_MEMORY_SYSTEM_END   UINT32_C(0x1FF1FFFF)

End of System memory.

Definition at line 54 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_OPTIONS_PACKAGE_DATA

#define MCCI_STM32H7_OPTIONS_PACKAGE_DATA   UINT32_C(0x08FFF80E)

package data (16 bits)

Definition at line 204 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_OPTIONS_SYSTEM_FLASH_SIZE

#define MCCI_STM32H7_OPTIONS_SYSTEM_FLASH_SIZE   UINT32_C(0x08FFF80C)

memory size in k bytes (16 bits)

Definition at line 194 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_OPTIONS_SYSTEM_FLASH_SIZE_TO_BYTES

#define MCCI_STM32H7_OPTIONS_SYSTEM_FLASH_SIZE_TO_BYTES (   h)
Value:
((h) & UINT32_C(0xFFFF)) == UINT32_C(0xFFFF) \
? UINT32_C(0x200000) \
: ((h) & UINT32_C(0xFFFF)) == UINT32_C(0) \
? UINT32_C(0x200000) \
: (((h) & UINT32_C(0xFFFF)) * 1024)

convert flash_size_16 value to bytes

Definition at line 197 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_OPTIONS_U_ID_0

#define MCCI_STM32H7_OPTIONS_U_ID_0   UINT32_C(0x08FFF800)

register address: unique ID bits 31:0

Definition at line 190 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_OPTIONS_U_ID_4

#define MCCI_STM32H7_OPTIONS_U_ID_4   (MCCI_STM32H7_OPTIONS_U_ID_0 + 0x04)

register address: unique ID bits 63:32

Definition at line 191 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_OPTIONS_U_ID_8

#define MCCI_STM32H7_OPTIONS_U_ID_8   (MCCI_STM32H7_OPTIONS_U_ID_0 + 0x08)

register address: unique ID bits 95:64

Definition at line 192 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_ADC1

#define MCCI_STM32H7_REG_ADC1   UINT32_C(0x40022000)

Section 27.7: ADC register map (1K)

Definition at line 118 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_BDMA1

#define MCCI_STM32H7_REG_BDMA1   UINT32_C(0x48022C00)

Section 16.6: BDMA register map (1K)

Definition at line 129 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_BDMA2

#define MCCI_STM32H7_REG_BDMA2   UINT32_C(0x58025400)

Section 16.6: BDMA register map (1K)

Definition at line 178 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_CAN_CCU

#define MCCI_STM32H7_REG_CAN_CCU   UINT32_C(0x4000A800)

Section 61.5: FDCAN register map (1K)

Definition at line 97 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_CAN_MSG_RAM

#define MCCI_STM32H7_REG_CAN_MSG_RAM   UINT32_C(0x4000AC00)

Section 61.5: FDCAN register map (1K)

Definition at line 98 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_COMP

#define MCCI_STM32H7_REG_COMP   UINT32_C(0x58003800)

Section 31.6: COMP register map (1K)

Definition at line 158 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_CRC

#define MCCI_STM32H7_REG_CRC   UINT32_C(0x40023000)

Section 22.4: CRC register map (1K)

Definition at line 119 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_CRS

#define MCCI_STM32H7_REG_CRS   UINT32_C(0x40008400)

Section 9.8: CRS register map (1K)

Definition at line 91 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_CRYPTO

#define MCCI_STM32H7_REG_CRYPTO   UINT32_C(0x48021000)

Section 39.7: CRYPTO register map (1K)

Definition at line 124 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_DAC1

#define MCCI_STM32H7_REG_DAC1   UINT32_C(0x40007400)

Section 29.7: DAC register map (1K)

Definition at line 88 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_DAC2

#define MCCI_STM32H7_REG_DAC2   UINT32_C(0x58003400)

Section 29.7: DAC register map (1K)

Definition at line 157 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_DCMI

#define MCCI_STM32H7_REG_DCMI   UINT32_C(0x48020000)

Section 34.5: DCMI register map (1K)

Definition at line 121 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_DFSDM1

#define MCCI_STM32H7_REG_DFSDM1   UINT32_C(0x40017800)

Section 33.7: 33.8: DFSDM register map (1K)

Definition at line 114 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_DFSDM2

#define MCCI_STM32H7_REG_DFSDM2   UINT32_C(0x58006C00)

Section 33.7: DFSDM register map (1K)

Definition at line 164 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_DLYB_OCTOSPI1

#define MCCI_STM32H7_REG_DLYB_OCTOSPI1   UINT32_C(0x52006000)

Section 26.4: DLYB register map (4K)

Definition at line 139 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_DLYB_OCTOSPI2

#define MCCI_STM32H7_REG_DLYB_OCTOSPI2   UINT32_C(0x5200B000)

Section 26.4: DLYB register map (1K)

Definition at line 144 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_DLYB_SDMMC1

#define MCCI_STM32H7_REG_DLYB_SDMMC1   UINT32_C(0x52008000)

Section 26.4: DLYB register map (1K)

Definition at line 141 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_DLYB_SDMMC2

#define MCCI_STM32H7_REG_DLYB_SDMMC2   UINT32_C(0x48022800)

Section 26.4: DLYB register map (1K)

Definition at line 128 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_DMA1

#define MCCI_STM32H7_REG_DMA1   UINT32_C(0x40020000)

Section 15.5: DMA register map (1K)

Definition at line 115 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_DMA2

#define MCCI_STM32H7_REG_DMA2   UINT32_C(0x40020400)

Section 15.5: DMA register map (1K)

Definition at line 116 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_DMA2D

#define MCCI_STM32H7_REG_DMA2D   UINT32_C(0x52001000)

Section 18.5: DMA2D register map (4K)

Definition at line 134 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_DMAMUX1

#define MCCI_STM32H7_REG_DMAMUX1   UINT32_C(0x40020800)

Section 17.6: DMAMUX register map (1K)

Definition at line 117 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_DMAMUX2

#define MCCI_STM32H7_REG_DMAMUX2   UINT32_C(0x58025800)

Section 17.6: DMAMUX register map (1K)

Definition at line 179 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_DTS

#define MCCI_STM32H7_REG_DTS   UINT32_C(0x58006800)

Section 28.6: DTS register map (1K)

Definition at line 163 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_EXTI

#define MCCI_STM32H7_REG_EXTI   UINT32_C(0x58000000)

Section 20.6: EXTI register map (1K)

Definition at line 149 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FDCAN

#define MCCI_STM32H7_REG_FDCAN   UINT32_C(0x4000A400)

Section 61.5: FDCAN register map (1K)

Definition at line 96 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH

#define MCCI_STM32H7_REG_FLASH   UINT32_C(0x52002000)

Section 4.9: FLASH register map (4K)

Definition at line 135 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_ACR

#define MCCI_STM32H7_REG_FLASH_ACR   (MCCI_STM32H7_REG_FLASH + 0x000)

Flash access control register.

Definition at line 215 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_ACR_LATENCY

#define MCCI_STM32H7_REG_FLASH_ACR_LATENCY   (UINT32_C(0xF) << 0)

Read latency:

Definition at line 261 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_ACR_LATENCY_V

#define MCCI_STM32H7_REG_FLASH_ACR_LATENCY_V (   n)    (UINT32_C(n) << 0)

Read latency: n wait state.

Definition at line 262 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_ACR_RSV6

#define MCCI_STM32H7_REG_FLASH_ACR_RSV6   UINT32_C(0xFFFFFFC0)

Reserved, don't change.

Definition at line 258 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_ACR_WRHIGHFREQ

#define MCCI_STM32H7_REG_FLASH_ACR_WRHIGHFREQ   (UINT32_C(3) << 4)

Flash signal delay.

Definition at line 259 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_ACR_WRHIGHFREQ_V

#define MCCI_STM32H7_REG_FLASH_ACR_WRHIGHFREQ_V (   n)    (UINT32_C(n) << 4)

Flash signal delay.

Definition at line 260 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_BOOT_ADD0

#define MCCI_STM32H7_REG_FLASH_BOOT_ADD0   (UINT32_C(0xFFFF) << 0)

boot address 0

Definition at line 424 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_BOOT_ADD1

#define MCCI_STM32H7_REG_FLASH_BOOT_ADD1   (UINT32_C(0xFFFF) << 16)

boot address 1

Definition at line 423 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_BOOT_CUR

#define MCCI_STM32H7_REG_FLASH_BOOT_CUR   (MCCI_STM32H7_REG_FLASH + 0x040)

Flash boot address.

Definition at line 231 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_BOOT_PRG

#define MCCI_STM32H7_REG_FLASH_BOOT_PRG   (MCCI_STM32H7_REG_FLASH + 0x044)

Flash boot address.

Definition at line 232 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CCR1

#define MCCI_STM32H7_REG_FLASH_CCR1   (MCCI_STM32H7_REG_FLASH + 0x014)

Flash clear control register for bank 1.

Definition at line 220 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CCR2

#define MCCI_STM32H7_REG_FLASH_CCR2   (MCCI_STM32H7_REG_FLASH + 0x114)

Flash clear control register for bank 2.

Definition at line 243 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CCR_CRCEND

#define MCCI_STM32H7_REG_FLASH_CCR_CRCEND   (UINT32_C(1) << 27)

CRCEND flag clear.

Definition at line 332 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CCR_CRCRDERR

#define MCCI_STM32H7_REG_FLASH_CCR_CRCRDERR   (UINT32_C(1) << 28)

CRCRDERR flag clear.

Definition at line 331 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CCR_DBECCERR

#define MCCI_STM32H7_REG_FLASH_CCR_DBECCERR   (UINT32_C(1) << 26)

DBECCERR flag clear.

Definition at line 333 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CCR_EOP

#define MCCI_STM32H7_REG_FLASH_CCR_EOP   (UINT32_C(1) << 16)

EOP flag clear.

Definition at line 342 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CCR_INCERR

#define MCCI_STM32H7_REG_FLASH_CCR_INCERR   (UINT32_C(1) << 21)

INCERR flag clear.

Definition at line 338 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CCR_PGSERR

#define MCCI_STM32H7_REG_FLASH_CCR_PGSERR   (UINT32_C(1) << 18)

PGSERR flag clear.

Definition at line 341 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CCR_RDPERR

#define MCCI_STM32H7_REG_FLASH_CCR_RDPERR   (UINT32_C(1) << 23)

RDPERR flag clear.

Definition at line 336 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CCR_RDSERR

#define MCCI_STM32H7_REG_FLASH_CCR_RDSERR   (UINT32_C(1) << 24)

RDSERR flag clear.

Definition at line 335 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CCR_RSV0

#define MCCI_STM32H7_REG_FLASH_CCR_RSV0   (UINT32_C(0xFFFF) << 0)

Reserved, don't change.

Definition at line 343 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CCR_RSV20

#define MCCI_STM32H7_REG_FLASH_CCR_RSV20   (UINT32_C(1) << 20)

Reserved, don't change.

Definition at line 339 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CCR_RSV22

#define MCCI_STM32H7_REG_FLASH_CCR_RSV22   (UINT32_C(1) << 22)

Reserved, don't change.

Definition at line 337 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CCR_RSV29

#define MCCI_STM32H7_REG_FLASH_CCR_RSV29   (UINT32_C(7) << 29)

Reserved, don't change.

Definition at line 330 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CCR_SNECCERR

#define MCCI_STM32H7_REG_FLASH_CCR_SNECCERR   (UINT32_C(1) << 25)

SNECCERR flag clear.

Definition at line 334 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CCR_STRBERR

#define MCCI_STM32H7_REG_FLASH_CCR_STRBERR   (UINT32_C(1) << 19)

STRBERR flag clear.

Definition at line 340 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR1

#define MCCI_STM32H7_REG_FLASH_CR1   (MCCI_STM32H7_REG_FLASH + 0x00C)

Flash control register for bank 1.

Definition at line 218 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR2

#define MCCI_STM32H7_REG_FLASH_CR2   (MCCI_STM32H7_REG_FLASH + 0x10C)

Flash control register for bank 2.

Definition at line 241 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_BER

#define MCCI_STM32H7_REG_FLASH_CR_BER   (UINT32_C(1) << 3)

Bank erase request.

Definition at line 299 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_CRC_EN

#define MCCI_STM32H7_REG_FLASH_CR_CRC_EN   (UINT32_C(1) << 15)

CRC control.

Definition at line 293 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_CRCENDIE

#define MCCI_STM32H7_REG_FLASH_CR_CRCENDIE   (UINT32_C(1) << 27)

CRC end of calculation interrupt enable.

Definition at line 281 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_CRCRDERRIE

#define MCCI_STM32H7_REG_FLASH_CR_CRCRDERRIE   (UINT32_C(1) << 28)

ECC CRC read error interrupt enable.

Definition at line 280 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_DBECCERRIE

#define MCCI_STM32H7_REG_FLASH_CR_DBECCERRIE   (UINT32_C(1) << 26)

ECC double detection error interrupt enable.

Definition at line 282 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_EOPIE

#define MCCI_STM32H7_REG_FLASH_CR_EOPIE   (UINT32_C(1) << 16)

End-of-program interrupt control.

Definition at line 292 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_FW

#define MCCI_STM32H7_REG_FLASH_CR_FW   (UINT32_C(1) << 4)

Write forcing control.

Definition at line 298 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_INCERRIE

#define MCCI_STM32H7_REG_FLASH_CR_INCERRIE   (UINT32_C(1) << 21)

inconsistency error interrupt enable

Definition at line 287 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_LOCK

#define MCCI_STM32H7_REG_FLASH_CR_LOCK   (UINT32_C(1) << 0)

Lock the FLASH_CR register.

Definition at line 302 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_PG

#define MCCI_STM32H7_REG_FLASH_CR_PG   (UINT32_C(1) << 1)

Internal buffer control.

Definition at line 301 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_PGSERRIE

#define MCCI_STM32H7_REG_FLASH_CR_PGSERRIE   (UINT32_C(1) << 18)

programming sequence error interrupt enable

Definition at line 290 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_RDPERRIE

#define MCCI_STM32H7_REG_FLASH_CR_RDPERRIE   (UINT32_C(1) << 23)

read protection error interrupt enable

Definition at line 285 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_RDSERRIE

#define MCCI_STM32H7_REG_FLASH_CR_RDSERRIE   (UINT32_C(1) << 24)

secure error interrupt enable

Definition at line 284 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_RSV13

#define MCCI_STM32H7_REG_FLASH_CR_RSV13   (UINT32_C(3) << 13)

Reserved, don't change.

Definition at line 294 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_RSV20

#define MCCI_STM32H7_REG_FLASH_CR_RSV20   (UINT32_C(1) << 20)

Reserved, don't change.

Definition at line 288 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_RSV22

#define MCCI_STM32H7_REG_FLASH_CR_RSV22   (UINT32_C(1) << 22)

Reserved, don't change.

Definition at line 286 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_RSV29

#define MCCI_STM32H7_REG_FLASH_CR_RSV29   (UINT32_C(7) << 29)

Reserved, don't change.

Definition at line 279 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_SER

#define MCCI_STM32H7_REG_FLASH_CR_SER   (UINT32_C(1) << 2)

Sector erase request.

Definition at line 300 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_SNECCERRIE

#define MCCI_STM32H7_REG_FLASH_CR_SNECCERRIE   (UINT32_C(1) << 25)

ECC single correction error interrupt enable.

Definition at line 283 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_SSN

#define MCCI_STM32H7_REG_FLASH_CR_SSN   (UINT32_C(0x7F) << 6)

Sector erase selection number.

Definition at line 295 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_SSN_N

#define MCCI_STM32H7_REG_FLASH_CR_SSN_N (   n)    ((n) << 6)

Sector erase selection number.

Definition at line 296 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_START

#define MCCI_STM32H7_REG_FLASH_CR_START   (UINT32_C(1) << 5)

Erase start control.

Definition at line 297 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_STRBERRIE

#define MCCI_STM32H7_REG_FLASH_CR_STRBERRIE   (UINT32_C(1) << 19)

strobe error interrupt enable

Definition at line 289 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CR_WRPERRIE

#define MCCI_STM32H7_REG_FLASH_CR_WRPERRIE   (UINT32_C(1) << 17)

write protection error interrupt enable

Definition at line 291 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCCR1

#define MCCI_STM32H7_REG_FLASH_CRCCR1   (MCCI_STM32H7_REG_FLASH + 0x050)

Flash CRC control register for bank 1.

Definition at line 233 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCCR2

#define MCCI_STM32H7_REG_FLASH_CRCCR2   (MCCI_STM32H7_REG_FLASH + 0x150)

Flash CRC control register for bank 2.

Definition at line 250 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCCR_ADD_SECT

#define MCCI_STM32H7_REG_FLASH_CRCCR_ADD_SECT   (UINT32_C(1) << 9)

CRC sector select bit.

Definition at line 437 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCCR_ALL_BANK

#define MCCI_STM32H7_REG_FLASH_CRCCR_ALL_BANK   (UINT32_C(1) << 22)

all CRC select

Definition at line 430 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCCR_CLEAN_CRC

#define MCCI_STM32H7_REG_FLASH_CRCCR_CLEAN_CRC   (UINT32_C(1) << 17)

CRC clear bit.

Definition at line 433 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCCR_CLEAN_SECT

#define MCCI_STM32H7_REG_FLASH_CRCCR_CLEAN_SECT   (UINT32_C(1) << 10)

CRC sector list clear bit.

Definition at line 436 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCCR_CRC_BURST

#define MCCI_STM32H7_REG_FLASH_CRCCR_CRC_BURST   (UINT32_C(3) << 20)

CRC burst size.

Definition at line 431 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCCR_CRC_BY_SECT

#define MCCI_STM32H7_REG_FLASH_CRCCR_CRC_BY_SECT   (UINT32_C(1) << 8)

CRC sector mode select bit.

Definition at line 438 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCCR_CRC_SECT

#define MCCI_STM32H7_REG_FLASH_CRCCR_CRC_SECT   (UINT32_C(0x7F) << 0)

CRC sector number.

Definition at line 440 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCCR_RSV11

#define MCCI_STM32H7_REG_FLASH_CRCCR_RSV11   (UINT32_C(0x1F) << 11)

Reserved, don't change.

Definition at line 435 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCCR_RSV18

#define MCCI_STM32H7_REG_FLASH_CRCCR_RSV18   (UINT32_C(3) << 18)

Reserved, don't change.

Definition at line 432 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCCR_RSV23

#define MCCI_STM32H7_REG_FLASH_CRCCR_RSV23   (UINT32_C(0x1FF) << 23)

Reserved, don't change.

Definition at line 429 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCCR_RSV7

#define MCCI_STM32H7_REG_FLASH_CRCCR_RSV7   (UINT32_C(1) << 7)

Reserved, don't change.

Definition at line 439 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCCR_START_CRC

#define MCCI_STM32H7_REG_FLASH_CRCCR_START_CRC   (UINT32_C(1) << 16)

CRC start bit.

Definition at line 434 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCDATA

#define MCCI_STM32H7_REG_FLASH_CRCDATA   (MCCI_STM32H7_REG_FLASH + 0x05C)

Flash CRC data register.

Definition at line 236 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCEADD1

#define MCCI_STM32H7_REG_FLASH_CRCEADD1   (MCCI_STM32H7_REG_FLASH + 0x058)

Flash CRC end address register for bank 1.

Definition at line 235 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCEADD2

#define MCCI_STM32H7_REG_FLASH_CRCEADD2   (MCCI_STM32H7_REG_FLASH + 0x158)

Flash CRC end address register for bank 2.

Definition at line 252 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCEADD_CRC_START_ADDR

#define MCCI_STM32H7_REG_FLASH_CRCEADD_CRC_START_ADDR   (UINT32_C(0x3FFFF) << 2)

CRC end address on bank 1/2.

Definition at line 453 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCEADD_RSV0

#define MCCI_STM32H7_REG_FLASH_CRCEADD_RSV0   (UINT32_C(3) << 0)

Reserved, don't change.

Definition at line 454 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCEADD_RSV20

#define MCCI_STM32H7_REG_FLASH_CRCEADD_RSV20   (UINT32_C(0xFFF) << 20)

Reserved, don't change.

Definition at line 452 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCSADD1

#define MCCI_STM32H7_REG_FLASH_CRCSADD1   (MCCI_STM32H7_REG_FLASH + 0x054)

Flash CRC start address register for bank 1.

Definition at line 234 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCSADD2

#define MCCI_STM32H7_REG_FLASH_CRCSADD2   (MCCI_STM32H7_REG_FLASH + 0x154)

Flash CRC start address register for bank 2.

Definition at line 251 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCSADD_CRC_START_ADDR

#define MCCI_STM32H7_REG_FLASH_CRCSADD_CRC_START_ADDR   (UINT32_C(0x3FFFF) << 2)

CRC start address on bank 1/2.

Definition at line 446 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCSADD_RSV0

#define MCCI_STM32H7_REG_FLASH_CRCSADD_RSV0   (UINT32_C(3) << 0)

Reserved, don't change.

Definition at line 447 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_CRCSADD_RSV20

#define MCCI_STM32H7_REG_FLASH_CRCSADD_RSV20   (UINT32_C(0xFFF) << 20)

Reserved, don't change.

Definition at line 445 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_ECC_FA1

#define MCCI_STM32H7_REG_FLASH_ECC_FA1   (MCCI_STM32H7_REG_FLASH + 0x060)

Flash ECC fail address for bank 1.

Definition at line 237 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_ECC_FA2

#define MCCI_STM32H7_REG_FLASH_ECC_FA2   (MCCI_STM32H7_REG_FLASH + 0x160)

Flash ECC fail address for bank 2.

Definition at line 253 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_ECC_FA_FAIL_ECC_ADDR

#define MCCI_STM32H7_REG_FLASH_ECC_FA_FAIL_ECC_ADDR   (UINT32_C(0xFFFF) << 0)

ECC error address.

Definition at line 461 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_ECC_FA_OTP_FAIL_ECC

#define MCCI_STM32H7_REG_FLASH_ECC_FA_OTP_FAIL_ECC   (UINT32_C(1) << 31)

OTP ECC error bit.

Definition at line 459 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_ECC_FA_RSV16

#define MCCI_STM32H7_REG_FLASH_ECC_FA_RSV16   (UINT32_C(0x7FFF) << 16)

Reserved, don't change.

Definition at line 460 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_KEYR1

#define MCCI_STM32H7_REG_FLASH_KEYR1   (MCCI_STM32H7_REG_FLASH + 0x004)

Flash key register for bank 1.

Definition at line 216 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_KEYR2

#define MCCI_STM32H7_REG_FLASH_KEYR2   (MCCI_STM32H7_REG_FLASH + 0x104)

Flash key register for bank 2.

Definition at line 240 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_KEYR_UNLOCK1

#define MCCI_STM32H7_REG_FLASH_KEYR_UNLOCK1   UINT32_C(0x45670123)

unlock word 1 for FLASH_CR1

Definition at line 267 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_KEYR_UNLOCK2

#define MCCI_STM32H7_REG_FLASH_KEYR_UNLOCK2   UINT32_C(0xCDEF89AB)

unlock word 2 for FLASH_CR1

Definition at line 268 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTCCR

#define MCCI_STM32H7_REG_FLASH_OPTCCR   (MCCI_STM32H7_REG_FLASH + 0x024)

Flash option clear control register.

Definition at line 224 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTCCR_OPTCHANGEERR

#define MCCI_STM32H7_REG_FLASH_OPTCCR_OPTCHANGEERR   (UINT32_C(1) << 30)

OPTCHANGEERR reset.

Definition at line 394 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTCCR_RSV0

#define MCCI_STM32H7_REG_FLASH_OPTCCR_RSV0   (0x3FFFFFFF)

Reserved, don't change.

Definition at line 395 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTCCR_RSV31

#define MCCI_STM32H7_REG_FLASH_OPTCCR_RSV31   (UINT32_C(1) << 31)

Reserved, don't change.

Definition at line 393 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTCR

#define MCCI_STM32H7_REG_FLASH_OPTCR   (MCCI_STM32H7_REG_FLASH + 0x018)

Flash option control register.

Definition at line 221 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTCR_MER

#define MCCI_STM32H7_REG_FLASH_OPTCR_MER   (UINT32_C(1) << 4)

mass erase request

Definition at line 352 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTCR_OPTCHANGEERRIE

#define MCCI_STM32H7_REG_FLASH_OPTCR_OPTCHANGEERRIE   (UINT32_C(1) << 30)

Option byte change error interrupt enable.

Definition at line 349 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTCR_OPTLOCK

#define MCCI_STM32H7_REG_FLASH_OPTCR_OPTLOCK   (UINT32_C(1) << 0)

FLASH_OPTCR lock option configuration.

Definition at line 355 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTCR_OPTSTART

#define MCCI_STM32H7_REG_FLASH_OPTCR_OPTSTART   (UINT32_C(1) << 1)

Option byte start change option configuration.

Definition at line 354 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTCR_PG_OTP

#define MCCI_STM32H7_REG_FLASH_OPTCR_PG_OTP   (UINT32_C(1) << 5)

OTP program control.

Definition at line 351 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTCR_RSV22

#define MCCI_STM32H7_REG_FLASH_OPTCR_RSV22   (UINT32_C(3) << 2)

Reserved, don't change.

Definition at line 353 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTCR_RSV29

#define MCCI_STM32H7_REG_FLASH_OPTCR_RSV29   (UINT32_C(1) << 29)

Reserved, don't change.

Definition at line 350 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTCR_SWAP_BANK

#define MCCI_STM32H7_REG_FLASH_OPTCR_SWAP_BANK   (UINT32_C(1) << 31)

Bank swapping option configuration.

Definition at line 348 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTKEYR

#define MCCI_STM32H7_REG_FLASH_OPTKEYR   (MCCI_STM32H7_REG_FLASH + 0x008)

Flash option key register.

Definition at line 217 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTKEYR_UNLOCK1

#define MCCI_STM32H7_REG_FLASH_OPTKEYR_UNLOCK1   UINT32_C(0x08192A3B)

unlock word 1 for option bytes

Definition at line 273 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTKEYR_UNLOCK2

#define MCCI_STM32H7_REG_FLASH_OPTKEYR_UNLOCK2   UINT32_C(0x4C5D6E7F)

unlock word 2 for option bytes

Definition at line 274 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_BOR_LEV

#define MCCI_STM32H7_REG_FLASH_OPTSR_BOR_LEV   (UINT32_C(3) << 2)

Brownout level option status.

Definition at line 382 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_BOR_LEV_1

#define MCCI_STM32H7_REG_FLASH_OPTSR_BOR_LEV_1   (UINT32_C(1) << 2)

BOR Level 1, the threshold level is low (around 2.1 V)

Definition at line 384 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_BOR_LEV_2

#define MCCI_STM32H7_REG_FLASH_OPTSR_BOR_LEV_2   (UINT32_C(2) << 2)

BOR Level 2, the threshold level is medium (around 2.4 V)

Definition at line 385 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_BOR_LEV_3

#define MCCI_STM32H7_REG_FLASH_OPTSR_BOR_LEV_3   (UINT32_C(3) << 2)

BOR Level 3, the threshold level is high (around 2.7 V)

Definition at line 386 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_BOR_LEV_OFF

#define MCCI_STM32H7_REG_FLASH_OPTSR_BOR_LEV_OFF   (UINT32_C(0) << 2)

BOR OFF.

Definition at line 383 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_CUR

#define MCCI_STM32H7_REG_FLASH_OPTSR_CUR   (MCCI_STM32H7_REG_FLASH + 0x01C)

Flash option status register.

Definition at line 222 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_IWDG_FZ_SDBY

#define MCCI_STM32H7_REG_FLASH_OPTSR_IWDG_FZ_SDBY   (UINT32_C(1) << 18)

IWDG Standby mode freeze option status.

Definition at line 371 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_IWDG_FZ_STOP

#define MCCI_STM32H7_REG_FLASH_OPTSR_IWDG_FZ_STOP   (UINT32_C(1) << 17)

IWDG Stop mode freeze option status.

Definition at line 372 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_IWDG_SW

#define MCCI_STM32H7_REG_FLASH_OPTSR_IWDG_SW   (UINT32_C(1) << 4)

IWDG control mode option status.

Definition at line 381 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_NRST_STDY

#define MCCI_STM32H7_REG_FLASH_OPTSR_NRST_STDY   (UINT32_C(1) << 7)

Core domain Standby entry reset option status.

Definition at line 378 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_NRST_STOP

#define MCCI_STM32H7_REG_FLASH_OPTSR_NRST_STOP   (UINT32_C(1) << 6)

Core domain DStop entry reset option status.

Definition at line 379 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_OPT_BUSY

#define MCCI_STM32H7_REG_FLASH_OPTSR_OPT_BUSY   (UINT32_C(1) << 0)

Option byte change ongoing flag.

Definition at line 388 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_OPTCHANGEERR

#define MCCI_STM32H7_REG_FLASH_OPTSR_OPTCHANGEERR   (UINT32_C(1) << 30)

Option byte change error flag.

Definition at line 361 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_PRG

#define MCCI_STM32H7_REG_FLASH_OPTSR_PRG   (MCCI_STM32H7_REG_FLASH + 0x020)

Flash option status register.

Definition at line 223 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_RDP

#define MCCI_STM32H7_REG_FLASH_OPTSR_RDP   (UINT32_C(0xFF) << 8)

Readout protection level option status.

Definition at line 374 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_RDP_LEVEL_0

#define MCCI_STM32H7_REG_FLASH_OPTSR_RDP_LEVEL_0   (UINT32_C(0xAA) << 8)

global readout protection level 0

Definition at line 375 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_RDP_LEVEL_1

#define MCCI_STM32H7_REG_FLASH_OPTSR_RDP_LEVEL_1   (UINT32_C(0xBB) << 8)

others values: global readout protection level 1

Definition at line 377 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_RDP_LEVEL_2

#define MCCI_STM32H7_REG_FLASH_OPTSR_RDP_LEVEL_2   (UINT32_C(0xCC) << 8)

global readout protection level 2

Definition at line 376 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_RSV1

#define MCCI_STM32H7_REG_FLASH_OPTSR_RSV1   (UINT32_C(1) << 1)

Reserved, don't change.

Definition at line 387 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_RSV22

#define MCCI_STM32H7_REG_FLASH_OPTSR_RSV22   (UINT32_C(0xF) << 22)

Reserved, don't change.

Definition at line 364 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_RSV26

#define MCCI_STM32H7_REG_FLASH_OPTSR_RSV26   (UINT32_C(7) << 26)

Reserved, don't change.

Definition at line 363 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_RSV5

#define MCCI_STM32H7_REG_FLASH_OPTSR_RSV5   (UINT32_C(1) << 5)

Reserved, don't change.

Definition at line 380 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_SECURITY

#define MCCI_STM32H7_REG_FLASH_OPTSR_SECURITY   (UINT32_C(1) << 21)

Security enable option status.

Definition at line 365 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_ST_RAM_SIZE

#define MCCI_STM32H7_REG_FLASH_OPTSR_ST_RAM_SIZE   (UINT32_C(3) << 19)

ST RAM size option.

Definition at line 366 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_ST_RAM_SIZE_16KB

#define MCCI_STM32H7_REG_FLASH_OPTSR_ST_RAM_SIZE_16KB   (UINT32_C(3) << 19)

2KB reserved to ST code

Definition at line 370 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_ST_RAM_SIZE_2KB

#define MCCI_STM32H7_REG_FLASH_OPTSR_ST_RAM_SIZE_2KB   (UINT32_C(0) << 19)

2KB reserved to ST code

Definition at line 367 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_ST_RAM_SIZE_4KB

#define MCCI_STM32H7_REG_FLASH_OPTSR_ST_RAM_SIZE_4KB   (UINT32_C(1) << 19)

2KB reserved to ST code

Definition at line 368 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_ST_RAM_SIZE_8KB

#define MCCI_STM32H7_REG_FLASH_OPTSR_ST_RAM_SIZE_8KB   (UINT32_C(2) << 19)

2KB reserved to ST code

Definition at line 369 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_SWAP_BANK_OPT

#define MCCI_STM32H7_REG_FLASH_OPTSR_SWAP_BANK_OPT   (UINT32_C(1) << 31)

Bank swapping option status.

Definition at line 360 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_VDDIO_HSLV

#define MCCI_STM32H7_REG_FLASH_OPTSR_VDDIO_HSLV   (UINT32_C(1) << 29)

VDD I/O high-speed at low-voltage status.

Definition at line 362 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OPTSR_VDDMMC_HSLV

#define MCCI_STM32H7_REG_FLASH_OPTSR_VDDMMC_HSLV   (UINT32_C(1) << 16)

VDDMMC I/O high-speed at low-voltage status.

Definition at line 373 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OTPBL_CUR

#define MCCI_STM32H7_REG_FLASH_OTPBL_CUR   (MCCI_STM32H7_REG_FLASH + 0x068)

Flash OTP block lock.

Definition at line 238 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OTPBL_LOCKBL

#define MCCI_STM32H7_REG_FLASH_OTPBL_LOCKBL   (UINT32_C(0xFFFF) << 0)

OTP Block Lock.

Definition at line 467 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OTPBL_PRG

#define MCCI_STM32H7_REG_FLASH_OTPBL_PRG   (MCCI_STM32H7_REG_FLASH + 0x06C)

Flash OTP block lock.

Definition at line 239 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_OTPBL_RSV16

#define MCCI_STM32H7_REG_FLASH_OTPBL_RSV16   (UINT32_C(0xFFFF) << 16)

Reserved, don't change.

Definition at line 466 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_PRAR_CUR1

#define MCCI_STM32H7_REG_FLASH_PRAR_CUR1   (MCCI_STM32H7_REG_FLASH + 0x028)

Flash protection address for bank 1.

Definition at line 225 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_PRAR_CUR2

#define MCCI_STM32H7_REG_FLASH_PRAR_CUR2   (MCCI_STM32H7_REG_FLASH + 0x128)

Flash protection address for bank 2.

Definition at line 244 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_PRAR_DMEP

#define MCCI_STM32H7_REG_FLASH_PRAR_DMEP   (UINT32_C(1) << 31)

PCROP protected erase enable option status.

Definition at line 400 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_PRAR_PRG1

#define MCCI_STM32H7_REG_FLASH_PRAR_PRG1   (MCCI_STM32H7_REG_FLASH + 0x02C)

Flash protection address for bank 1.

Definition at line 226 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_PRAR_PRG2

#define MCCI_STM32H7_REG_FLASH_PRAR_PRG2   (MCCI_STM32H7_REG_FLASH + 0x12C)

Flash protection address for bank 2.

Definition at line 245 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_PRAR_PROT_AREA_END

#define MCCI_STM32H7_REG_FLASH_PRAR_PROT_AREA_END   (UINT32_C(0xFFF) << 16)

PCROP area end status.

Definition at line 402 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_PRAR_PROT_AREA_START

#define MCCI_STM32H7_REG_FLASH_PRAR_PROT_AREA_START   (UINT32_C(0xFFF) << 0)

PCROP area start status.

Definition at line 404 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_PRAR_RSV12

#define MCCI_STM32H7_REG_FLASH_PRAR_RSV12   (UINT32_C(15) << 12)

Reserved, don't change.

Definition at line 403 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_PRAR_RSV28

#define MCCI_STM32H7_REG_FLASH_PRAR_RSV28   (UINT32_C(7) << 28)

Reserved, don't change.

Definition at line 401 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SCAR_CUR1

#define MCCI_STM32H7_REG_FLASH_SCAR_CUR1   (MCCI_STM32H7_REG_FLASH + 0x030)

Flash secure address for bank 1.

Definition at line 227 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SCAR_CUR2

#define MCCI_STM32H7_REG_FLASH_SCAR_CUR2   (MCCI_STM32H7_REG_FLASH + 0x130)

Flash secure address for bank 2.

Definition at line 246 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SCAR_DMES

#define MCCI_STM32H7_REG_FLASH_SCAR_DMES   (UINT32_C(1) << 31)

secure access protected erase enable option status

Definition at line 409 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SCAR_PRG1

#define MCCI_STM32H7_REG_FLASH_SCAR_PRG1   (MCCI_STM32H7_REG_FLASH + 0x034)

Flash secure address for bank 1.

Definition at line 228 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SCAR_PRG2

#define MCCI_STM32H7_REG_FLASH_SCAR_PRG2   (MCCI_STM32H7_REG_FLASH + 0x134)

Flash secure address for bank 2.

Definition at line 247 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SCAR_RSV12

#define MCCI_STM32H7_REG_FLASH_SCAR_RSV12   (UINT32_C(15) << 12)

Reserved, don't change.

Definition at line 412 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SCAR_RSV28

#define MCCI_STM32H7_REG_FLASH_SCAR_RSV28   (UINT32_C(7) << 28)

Reserved, don't change.

Definition at line 410 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SCAR_SEC_AREA_END

#define MCCI_STM32H7_REG_FLASH_SCAR_SEC_AREA_END   (UINT32_C(0xFFF) << 16)

secure-only area end status

Definition at line 411 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SCAR_SEC_AREA_START

#define MCCI_STM32H7_REG_FLASH_SCAR_SEC_AREA_START   (UINT32_C(0xFFF) << 0)

secure-only area start status

Definition at line 413 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR1

#define MCCI_STM32H7_REG_FLASH_SR1   (MCCI_STM32H7_REG_FLASH + 0x010)

Flash status register for bank 1.

Definition at line 219 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR2

#define MCCI_STM32H7_REG_FLASH_SR2   (MCCI_STM32H7_REG_FLASH + 0x110)

Flash status register for bank 2.

Definition at line 242 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR_BSY

#define MCCI_STM32H7_REG_FLASH_SR_BSY   (UINT32_C(1) << 0)

Busy flag.

Definition at line 325 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR_CRC_BUSY

#define MCCI_STM32H7_REG_FLASH_SR_CRC_BUSY   (UINT32_C(1) << 3)

CRC busy flag.

Definition at line 322 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR_CRCEND

#define MCCI_STM32H7_REG_FLASH_SR_CRCEND   (UINT32_C(1) << 27)

CRC end of calculation flag.

Definition at line 309 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR_CRCRDERR

#define MCCI_STM32H7_REG_FLASH_SR_CRCRDERR   (UINT32_C(1) << 28)

ECC CRC read error flag.

Definition at line 308 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR_DBECCERR

#define MCCI_STM32H7_REG_FLASH_SR_DBECCERR   (UINT32_C(1) << 26)

ECC double detection error flag.

Definition at line 310 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR_EOP

#define MCCI_STM32H7_REG_FLASH_SR_EOP   (UINT32_C(1) << 16)

End-of-program flag.

Definition at line 320 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR_INCERR

#define MCCI_STM32H7_REG_FLASH_SR_INCERR   (UINT32_C(1) << 21)

inconsistency error flag

Definition at line 315 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR_PGSERR

#define MCCI_STM32H7_REG_FLASH_SR_PGSERR   (UINT32_C(1) << 18)

programming sequence error flag

Definition at line 318 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR_QW

#define MCCI_STM32H7_REG_FLASH_SR_QW   (UINT32_C(1) << 2)

wait queue flag

Definition at line 323 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR_RDPERR

#define MCCI_STM32H7_REG_FLASH_SR_RDPERR   (UINT32_C(1) << 23)

read protection error flag

Definition at line 313 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR_RDSERR

#define MCCI_STM32H7_REG_FLASH_SR_RDSERR   (UINT32_C(1) << 24)

secure error flag

Definition at line 312 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR_RSV20

#define MCCI_STM32H7_REG_FLASH_SR_RSV20   (UINT32_C(1) << 20)

Reserved, don't change.

Definition at line 316 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR_RSV22

#define MCCI_STM32H7_REG_FLASH_SR_RSV22   (UINT32_C(1) << 22)

Reserved, don't change.

Definition at line 314 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR_RSV29

#define MCCI_STM32H7_REG_FLASH_SR_RSV29   (UINT32_C(7) << 29)

Reserved, don't change.

Definition at line 307 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR_RSV4

#define MCCI_STM32H7_REG_FLASH_SR_RSV4   (UINT32_C(0xFFF) << 4)

Reserved, don't change.

Definition at line 321 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR_SNECCERR

#define MCCI_STM32H7_REG_FLASH_SR_SNECCERR   (UINT32_C(1) << 25)

ECC single correction error flag.

Definition at line 311 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR_STRBERR

#define MCCI_STM32H7_REG_FLASH_SR_STRBERR   (UINT32_C(1) << 19)

strobe error flag

Definition at line 317 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR_WBNE

#define MCCI_STM32H7_REG_FLASH_SR_WBNE   (UINT32_C(1) << 1)

write buffer not empty flag

Definition at line 324 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_SR_WRPERR

#define MCCI_STM32H7_REG_FLASH_SR_WRPERR   (UINT32_C(1) << 17)

write protection error flag

Definition at line 319 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_WPSGN_CUR1

#define MCCI_STM32H7_REG_FLASH_WPSGN_CUR1   (MCCI_STM32H7_REG_FLASH + 0x038)

Flash write sector group protection for bank 1.

Definition at line 229 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_WPSGN_CUR2

#define MCCI_STM32H7_REG_FLASH_WPSGN_CUR2   (MCCI_STM32H7_REG_FLASH + 0x138)

Flash write sector group protection for bank 2.

Definition at line 248 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_WPSGN_PRG1

#define MCCI_STM32H7_REG_FLASH_WPSGN_PRG1   (MCCI_STM32H7_REG_FLASH + 0x03C)

Flash write sector group protection for bank 1.

Definition at line 230 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_WPSGN_PRG2

#define MCCI_STM32H7_REG_FLASH_WPSGN_PRG2   (MCCI_STM32H7_REG_FLASH + 0x13C)

Flash write sector group protection for bank 2.

Definition at line 249 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FLASH_WPSGN_SECT

#define MCCI_STM32H7_REG_FLASH_WPSGN_SECT (   n)    (UINT32_C(1) << (((n) & 127) >> 2))

Group embedding sectors.

Definition at line 418 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_FMC

#define MCCI_STM32H7_REG_FMC   UINT32_C(0x52004000)

Section 23.7.6: 23.8.7: 23.9.5: FMC register map (4K)

Definition at line 137 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_GFXMMU

#define MCCI_STM32H7_REG_GFXMMU   UINT32_C(0x5200C000)

Section 21.5: GFXMMU register map (8K)

Definition at line 148 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_GPIOA

#define MCCI_STM32H7_REG_GPIOA   UINT32_C(0x58020000)

Section 11.4: GPIO register map (1K)

Definition at line 165 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_GPIOB

#define MCCI_STM32H7_REG_GPIOB   UINT32_C(0x58020400)

Section 11.4: GPIO register map (1K)

Definition at line 166 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_GPIOC

#define MCCI_STM32H7_REG_GPIOC   UINT32_C(0x58020800)

Section 11.4: GPIO register map (1K)

Definition at line 167 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_GPIOD

#define MCCI_STM32H7_REG_GPIOD   UINT32_C(0x58020C00)

Section 11.4: GPIO register map (1K)

Definition at line 168 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_GPIOE

#define MCCI_STM32H7_REG_GPIOE   UINT32_C(0x58021000)

Section 11.4: GPIO register map (1K)

Definition at line 169 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_GPIOF

#define MCCI_STM32H7_REG_GPIOF   UINT32_C(0x58021400)

Section 11.4: GPIO register map (1K)

Definition at line 170 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_GPIOG

#define MCCI_STM32H7_REG_GPIOG   UINT32_C(0x58021800)

Section 11.4: GPIO register map (1K)

Definition at line 171 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_GPIOH

#define MCCI_STM32H7_REG_GPIOH   UINT32_C(0x58021C00)

Section 11.4: GPIO register map (1K)

Definition at line 172 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_GPIOI

#define MCCI_STM32H7_REG_GPIOI   UINT32_C(0x58022000)

Section 11.4: GPIO register map (1K)

Definition at line 173 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_GPIOJ

#define MCCI_STM32H7_REG_GPIOJ   UINT32_C(0x58022400)

Section 11.4: GPIO register map (1K)

Definition at line 174 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_GPIOK

#define MCCI_STM32H7_REG_GPIOK   UINT32_C(0x58022800)

Section 11.4: GPIO register map (1K)

Definition at line 175 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_GPV

#define MCCI_STM32H7_REG_GPV   UINT32_C(0x51000000)

Section 2.2.4: AXI interconnect register map (1M)

Definition at line 132 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_HASH

#define MCCI_STM32H7_REG_HASH   UINT32_C(0x48021400)

Section 40.7: HASH register map (1K)

Definition at line 125 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_HDMI_CEC

#define MCCI_STM32H7_REG_HDMI_CEC   UINT32_C(0x40006C00)

Section 63.7: HDMI-CEC register map (1K)

Definition at line 87 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_HSEM

#define MCCI_STM32H7_REG_HSEM   UINT32_C(0x48020800)

Section 10.4: HSEM register map (1K)

Definition at line 123 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_I2C1

#define MCCI_STM32H7_REG_I2C1   UINT32_C(0x40005400)

Section 52.7: I2C register map (1K)

Definition at line 84 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_I2C2

#define MCCI_STM32H7_REG_I2C2   UINT32_C(0x40005800)

Section 52.7: I2C register map (1K)

Definition at line 85 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_I2C3

#define MCCI_STM32H7_REG_I2C3   UINT32_C(0x40005C00)

Section 52.7: I2C register map (1K)

Definition at line 86 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_I2C4

#define MCCI_STM32H7_REG_I2C4   UINT32_C(0x58001C00)

Section 52.7: I2C register map (1K)

Definition at line 154 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_I2S1

#define MCCI_STM32H7_REG_I2S1   UINT32_C(0x40013000)

Section 55.11: SPI register map (1K)

Definition at line 106 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_I2S6

#define MCCI_STM32H7_REG_I2S6   UINT32_C(0x58001400)

Section 55.11: I2S register map (1K)

Definition at line 153 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_IWDG

#define MCCI_STM32H7_REG_IWDG   UINT32_C(0x58004800)

Section 49.4: IWDG register map (1K)

Definition at line 162 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_JPEG

#define MCCI_STM32H7_REG_JPEG   UINT32_C(0x52003000)

Section 4.9: JPEG register map (4K)

Definition at line 136 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_LPTIM1

#define MCCI_STM32H7_REG_LPTIM1   UINT32_C(0x40002400)

Section 47.7: LPTIM register map (1K)

Definition at line 76 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_LPTIM2

#define MCCI_STM32H7_REG_LPTIM2   UINT32_C(0x58002400)

Section 47.7: LPTIM register map (1K)

Definition at line 155 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_LPTIM3

#define MCCI_STM32H7_REG_LPTIM3   UINT32_C(0x58002800)

Section 47.7: LPTIM register map (1K)

Definition at line 156 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_LPUART1

#define MCCI_STM32H7_REG_LPUART1   UINT32_C(0x58000C00)

Section 54.6: LPUART register map (1K)

Definition at line 151 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_LTDC

#define MCCI_STM32H7_REG_LTDC   UINT32_C(0x50001000)

Section 36.7: LTDC register map (4K)

Definition at line 130 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_MDIOS

#define MCCI_STM32H7_REG_MDIOS   UINT32_C(0x40009400)

Section 59.4: MDIOS register map (1K)

Definition at line 94 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_MDMA

#define MCCI_STM32H7_REG_MDMA   UINT32_C(0x52000000)

Section 14.5: MDMA register map (4K)

Definition at line 133 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_OCTOSPI1

#define MCCI_STM32H7_REG_OCTOSPI1   UINT32_C(0x52005000)

Section 24.7: OCTOSPI register map (4K)

Definition at line 138 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_OCTOSPI2

#define MCCI_STM32H7_REG_OCTOSPI2   UINT32_C(0x5200A000)

Section 24.7: OCTOSPI register map (4K)

Definition at line 143 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_OPAMP

#define MCCI_STM32H7_REG_OPAMP   UINT32_C(0x40009000)

Section 32.6: OPAMP register map (1K)

Definition at line 93 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_OTCOSPIM

#define MCCI_STM32H7_REG_OTCOSPIM   UINT32_C(0x5200B400)

Section 25.4: OTCOSPIM register map (1K)

Definition at line 145 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_OTFDEC1

#define MCCI_STM32H7_REG_OTFDEC1   UINT32_C(0x5200B800)

Section 41.6: OTFDEC register map (1K)

Definition at line 146 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_OTFDEC2

#define MCCI_STM32H7_REG_OTFDEC2   UINT32_C(0x5200BC00)

Section 41.6: OTFDEC register map (1K)

Definition at line 147 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_OTG_HS

#define MCCI_STM32H7_REG_OTG_HS   UINT32_C(0x40040000)

Section 62.14: OTG_HS register map (1K)

Definition at line 120 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PSSI

#define MCCI_STM32H7_REG_PSSI   UINT32_C(0x48020400)

Section 35.5: PSSI register map (1K)

Definition at line 122 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR

#define MCCI_STM32H7_REG_PWR   UINT32_C(0x58024800)

Section 6.8: PWR register map (1K)

Definition at line 177 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CPUCR

#define MCCI_STM32H7_REG_PWR_CPUCR   (MCCI_STM32H7_REG_PWR + 0x10)

CPU control.

Definition at line 494 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CPUCR_CSSF

#define MCCI_STM32H7_REG_PWR_CPUCR_CSSF   (UINT32_C(1) << 9)

clear Standby and Stop flags (always read as 0)

Definition at line 594 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CPUCR_PDDS_SRD

#define MCCI_STM32H7_REG_PWR_CPUCR_PDDS_SRD   (UINT32_C(1) << 2)

system SmartRun domain power down Deepsleep

Definition at line 599 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CPUCR_RETDS_CD

#define MCCI_STM32H7_REG_PWR_CPUCR_RETDS_CD   (UINT32_C(1) << 0)

CPU domain power down Deepsleep selection.

Definition at line 601 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CPUCR_RSV1

#define MCCI_STM32H7_REG_PWR_CPUCR_RSV1   (UINT32_C(1) << 1)

Reserved, don't change.

Definition at line 600 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CPUCR_RSV10

#define MCCI_STM32H7_REG_PWR_CPUCR_RSV10   (UINT32_C(1) << 10)

Reserved, don't change.

Definition at line 593 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CPUCR_RSV12

#define MCCI_STM32H7_REG_PWR_CPUCR_RSV12   UINT32_C(0xFFFFF000)

Reserved, don't change.

Definition at line 591 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CPUCR_RSV3

#define MCCI_STM32H7_REG_PWR_CPUCR_RSV3   (UINT32_C(3) << 3)

Reserved, don't change.

Definition at line 598 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CPUCR_RSV7

#define MCCI_STM32H7_REG_PWR_CPUCR_RSV7   (UINT32_C(3) << 7)

Reserved, don't change.

Definition at line 595 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CPUCR_RUN_SRD

#define MCCI_STM32H7_REG_PWR_CPUCR_RUN_SRD   (UINT32_C(1) << 11)

temperature level monitoring versus high threshold

Definition at line 592 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CPUCR_SBF

#define MCCI_STM32H7_REG_PWR_CPUCR_SBF   (UINT32_C(1) << 6)

system Standby flag

Definition at line 596 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CPUCR_STOPF

#define MCCI_STM32H7_REG_PWR_CPUCR_STOPF   (UINT32_C(1) << 5)

STOP flag.

Definition at line 597 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1

#define MCCI_STM32H7_REG_PWR_CR1   (MCCI_STM32H7_REG_PWR + 0x00)

control

Definition at line 490 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_AHBRAM1SO

#define MCCI_STM32H7_REG_PWR_CR1_AHBRAM1SO   (UINT32_C(1) << 22)

AHB SRAM1 shut-off in DStop/DStop2 mode.

Definition at line 509 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_AHBRAM2SO

#define MCCI_STM32H7_REG_PWR_CR1_AHBRAM2SO   (UINT32_C(1) << 23)

AHB SRAM2 shut-off in DStop/DStop2 mode.

Definition at line 508 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_ALS

#define MCCI_STM32H7_REG_PWR_CR1_ALS   (UINT32_C(3) << 17)

analog voltage detector level selection

Definition at line 513 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_ALS_1_7V

#define MCCI_STM32H7_REG_PWR_CR1_ALS_1_7V   (UINT32_C(0) << 17)

1.7V

Definition at line 514 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_ALS_2_1V

#define MCCI_STM32H7_REG_PWR_CR1_ALS_2_1V   (UINT32_C(1) << 17)

2.1V

Definition at line 515 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_ALS_2_5V

#define MCCI_STM32H7_REG_PWR_CR1_ALS_2_5V   (UINT32_C(2) << 17)

2.5V

Definition at line 516 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_ALS_2_8V

#define MCCI_STM32H7_REG_PWR_CR1_ALS_2_8V   (UINT32_C(3) << 17)

2.8V

Definition at line 517 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_AVD_READY

#define MCCI_STM32H7_REG_PWR_CR1_AVD_READY   (UINT32_C(1) << 13)

analog voltage ready

Definition at line 523 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_AVDEN

#define MCCI_STM32H7_REG_PWR_CR1_AVDEN   (UINT32_C(1) << 16)

peripheral voltage monitor on VDDA enable

Definition at line 518 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_AXIRAM1SO

#define MCCI_STM32H7_REG_PWR_CR1_AXIRAM1SO   (UINT32_C(1) << 19)

AXI SRAM1 shut-off in DStop/DStop2 mode.

Definition at line 512 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_AXIRAM2SO

#define MCCI_STM32H7_REG_PWR_CR1_AXIRAM2SO   (UINT32_C(1) << 20)

AXI SRAM2 shut-off in DStop/DStop2 mode.

Definition at line 511 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_AXIRAM3SO

#define MCCI_STM32H7_REG_PWR_CR1_AXIRAM3SO   (UINT32_C(1) << 21)

AXI SRAM3 shut-off in DStop/DStop2 mode.

Definition at line 510 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_BOOSTE

#define MCCI_STM32H7_REG_PWR_CR1_BOOSTE   (UINT32_C(1) << 12)

analog switch VBoost control

Definition at line 524 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_DBP

#define MCCI_STM32H7_REG_PWR_CR1_DBP   (UINT32_C(1) << 8)

disable Backup domain write protection

Definition at line 527 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_FLPS

#define MCCI_STM32H7_REG_PWR_CR1_FLPS   (UINT32_C(1) << 9)

Flash memory low-power mode in DStop or DStop2 mode.

Definition at line 526 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_GFXSO

#define MCCI_STM32H7_REG_PWR_CR1_GFXSO   (UINT32_C(1) << 25)

GFXMMU and JPEG memory shut-off in DStop/DStop2 mode.

Definition at line 506 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_HSITFSO

#define MCCI_STM32H7_REG_PWR_CR1_HSITFSO   (UINT32_C(1) << 26)

high-speed interfaces USB and FDCAN memory shut-off in DStop/DStop2 mode

Definition at line 505 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_ITCMSO

#define MCCI_STM32H7_REG_PWR_CR1_ITCMSO   (UINT32_C(1) << 24)

instruction TCM and ETM memory shut-off in DStop/DStop2 mode

Definition at line 507 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_LPDS

#define MCCI_STM32H7_REG_PWR_CR1_LPDS   (UINT32_C(1) << 0)

low-power Deepsleep with SVOS3

Definition at line 539 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_PLS

#define MCCI_STM32H7_REG_PWR_CR1_PLS   (UINT32_C(7) << 5)

programmable voltage detector level selection

Definition at line 528 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_PLS_1_95V

#define MCCI_STM32H7_REG_PWR_CR1_PLS_1_95V   (UINT32_C(0) << 5)

1.95V

Definition at line 529 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_PLS_2_1V

#define MCCI_STM32H7_REG_PWR_CR1_PLS_2_1V   (UINT32_C(1) << 5)

2.1V

Definition at line 530 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_PLS_2_25V

#define MCCI_STM32H7_REG_PWR_CR1_PLS_2_25V   (UINT32_C(2) << 5)

2.25V

Definition at line 531 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_PLS_2_4V

#define MCCI_STM32H7_REG_PWR_CR1_PLS_2_4V   (UINT32_C(3) << 5)

2.4V

Definition at line 532 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_PLS_2_55V

#define MCCI_STM32H7_REG_PWR_CR1_PLS_2_55V   (UINT32_C(4) << 5)

2.55V

Definition at line 533 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_PLS_2_7V

#define MCCI_STM32H7_REG_PWR_CR1_PLS_2_7V   (UINT32_C(5) << 5)

2.7V

Definition at line 534 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_PLS_2_85V

#define MCCI_STM32H7_REG_PWR_CR1_PLS_2_85V   (UINT32_C(6) << 5)

2.85V

Definition at line 535 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_PLS_PVD_IN

#define MCCI_STM32H7_REG_PWR_CR1_PLS_PVD_IN   (UINT32_C(7) << 5)

PVD_IN pin.

Definition at line 536 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_PVDE

#define MCCI_STM32H7_REG_PWR_CR1_PVDE   (UINT32_C(1) << 4)

programmable voltage detector enable

Definition at line 537 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_RSV1

#define MCCI_STM32H7_REG_PWR_CR1_RSV1   (UINT32_C(7) << 1)

Reserved, don't change.

Definition at line 538 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_RSV10

#define MCCI_STM32H7_REG_PWR_CR1_RSV10   (UINT32_C(3) << 10)

Reserved, don't change.

Definition at line 525 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_RSV28

#define MCCI_STM32H7_REG_PWR_CR1_RSV28   (UINT32_C(15) << 28)

Reserved, don't change.

Definition at line 503 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_SRDRAMSO

#define MCCI_STM32H7_REG_PWR_CR1_SRDRAMSO   (UINT32_C(1) << 27)

SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode.

Definition at line 504 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_SVOS

#define MCCI_STM32H7_REG_PWR_CR1_SVOS   (UINT32_C(3) << 14)

system stop mode voltage scaling selection

Definition at line 519 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_SVOS_3

#define MCCI_STM32H7_REG_PWR_CR1_SVOS_3   (UINT32_C(3) << 14)

SVOS5 scale 3.

Definition at line 522 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_SVOS_4

#define MCCI_STM32H7_REG_PWR_CR1_SVOS_4   (UINT32_C(2) << 14)

SVOS5 scale 4.

Definition at line 521 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR1_SVOS_5

#define MCCI_STM32H7_REG_PWR_CR1_SVOS_5   (UINT32_C(1) << 14)

SVOS5 scale 5.

Definition at line 520 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR2

#define MCCI_STM32H7_REG_PWR_CR2   (MCCI_STM32H7_REG_PWR + 0x08)

control 2

Definition at line 492 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR2_BREN

#define MCCI_STM32H7_REG_PWR_CR2_BREN   (UINT32_C(1) << 0)

backup regulator enable

Definition at line 564 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR2_BRRDY

#define MCCI_STM32H7_REG_PWR_CR2_BRRDY   (UINT32_C(1) << 16)

backup regulator ready

Definition at line 560 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR2_MONEN

#define MCCI_STM32H7_REG_PWR_CR2_MONEN   (UINT32_C(1) << 4)

VBAT and temperature monitoring enable.

Definition at line 562 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR2_RSV1

#define MCCI_STM32H7_REG_PWR_CR2_RSV1   (UINT32_C(7) << 1)

Reserved, don't change.

Definition at line 563 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR2_RSV17

#define MCCI_STM32H7_REG_PWR_CR2_RSV17   (UINT32_C(0x1F) << 17)

Reserved, don't change.

Definition at line 559 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR2_RSV24

#define MCCI_STM32H7_REG_PWR_CR2_RSV24   (UINT32_C(0xFF) << 24)

Reserved, don't change.

Definition at line 556 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR2_RSV5

#define MCCI_STM32H7_REG_PWR_CR2_RSV5   (UINT32_C(0x7FF) << 5)

Reserved, don't change.

Definition at line 561 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR2_TEMPH

#define MCCI_STM32H7_REG_PWR_CR2_TEMPH   (UINT32_C(1) << 23)

temperature level monitoring versus high threshold

Definition at line 557 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR2_TEMPL

#define MCCI_STM32H7_REG_PWR_CR2_TEMPL   (UINT32_C(1) << 22)

temperature level monitoring versus low threshold

Definition at line 558 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR3

#define MCCI_STM32H7_REG_PWR_CR3   (MCCI_STM32H7_REG_PWR + 0x0C)

control 3

Definition at line 493 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR3_BYPASS

#define MCCI_STM32H7_REG_PWR_CR3_BYPASS   (UINT32_C(1) << 0)

power management unit bypass

Definition at line 586 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR3_LDOEN

#define MCCI_STM32H7_REG_PWR_CR3_LDOEN   (UINT32_C(1) << 1)

low drop-out regulator enable

Definition at line 585 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR3_RSV10

#define MCCI_STM32H7_REG_PWR_CR3_RSV10   (UINT32_C(0x3F) << 10)

Reserved, don't change.

Definition at line 575 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR3_RSV17

#define MCCI_STM32H7_REG_PWR_CR3_RSV17   (UINT32_C(0x7F) << 17)

Reserved, don't change.

Definition at line 573 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR3_RSV27

#define MCCI_STM32H7_REG_PWR_CR3_RSV27   (UINT32_C(0x1F) << 27)

Reserved, don't change.

Definition at line 569 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR3_RSV6

#define MCCI_STM32H7_REG_PWR_CR3_RSV6   (UINT32_C(3) << 6)

Reserved, don't change.

Definition at line 578 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR3_SMPSEN

#define MCCI_STM32H7_REG_PWR_CR3_SMPSEN   (UINT32_C(1) << 2)

SMPS step-down converter enable.

Definition at line 584 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR3_SMPSEXTHP

#define MCCI_STM32H7_REG_PWR_CR3_SMPSEXTHP   (UINT32_C(1) << 3)

SMPS step-down converter external power delivery selection.

Definition at line 583 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR3_SMPSEXTRDY

#define MCCI_STM32H7_REG_PWR_CR3_SMPSEXTRDY   (UINT32_C(1) << 16)

SMPS step-down converter external supply ready.

Definition at line 574 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR3_SMPSLEVEL

#define MCCI_STM32H7_REG_PWR_CR3_SMPSLEVEL   (UINT32_C(3) << 4)

SMPS step-down converter voltage output level selection.

Definition at line 579 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR3_SMPSLEVEL_1_8V

#define MCCI_STM32H7_REG_PWR_CR3_SMPSLEVEL_1_8V   (UINT32_C(1) << 4)

1.8V

Definition at line 580 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR3_SMPSLEVEL_2_5V

#define MCCI_STM32H7_REG_PWR_CR3_SMPSLEVEL_2_5V   (UINT32_C(2) << 4)

2.5V

Definition at line 581 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR3_SMPSLEVEL_2V5

#define MCCI_STM32H7_REG_PWR_CR3_SMPSLEVEL_2V5   (UINT32_C(3) << 4)

2.5V

Definition at line 582 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR3_USB33DEN

#define MCCI_STM32H7_REG_PWR_CR3_USB33DEN   (UINT32_C(1) << 24)

VDD33USB voltage level detector enable.

Definition at line 572 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR3_USB33RDY

#define MCCI_STM32H7_REG_PWR_CR3_USB33RDY   (UINT32_C(1) << 26)

USB supply ready.

Definition at line 570 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR3_USBREGEN

#define MCCI_STM32H7_REG_PWR_CR3_USBREGEN   (UINT32_C(1) << 25)

USB regulator enable.

Definition at line 571 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR3_VBE

#define MCCI_STM32H7_REG_PWR_CR3_VBE   (UINT32_C(1) << 8)

VBAT charging enable.

Definition at line 577 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CR3_VBRS

#define MCCI_STM32H7_REG_PWR_CR3_VBRS   (UINT32_C(1) << 9)

VBAT charging resistor selection.

Definition at line 576 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CSR1

#define MCCI_STM32H7_REG_PWR_CSR1   (MCCI_STM32H7_REG_PWR + 0x04)

control status

Definition at line 491 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CSR1_ACTVOS

#define MCCI_STM32H7_REG_PWR_CSR1_ACTVOS   (UINT32_C(3) << 14)

VOS currently applied for VCORE voltage scaling selection.

Definition at line 547 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CSR1_ACTVOSRDY

#define MCCI_STM32H7_REG_PWR_CSR1_ACTVOSRDY   (UINT32_C(1) << 13)

Regulator low-power flag.

Definition at line 548 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CSR1_AVDO

#define MCCI_STM32H7_REG_PWR_CSR1_AVDO   (UINT32_C(1) << 16)

analog voltage detector output on VDDA

Definition at line 546 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CSR1_MMCVDO

#define MCCI_STM32H7_REG_PWR_CSR1_MMCVDO   (UINT32_C(1) << 17)

voltage detector output on VDDMMC

Definition at line 545 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CSR1_PVDO

#define MCCI_STM32H7_REG_PWR_CSR1_PVDO   (UINT32_C(1) << 4)

programmable voltage detect output

Definition at line 550 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CSR1_RSV0

#define MCCI_STM32H7_REG_PWR_CSR1_RSV0   (UINT32_C(0xF) << 0)

Reserved, do not change.

Definition at line 551 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CSR1_RSV18

#define MCCI_STM32H7_REG_PWR_CSR1_RSV18   UINT32C(0xFFFC0000)

reserved, do not change

Definition at line 544 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_CSR1_RSV5

#define MCCI_STM32H7_REG_PWR_CSR1_RSV5   (UINT32_C(0xFF) << 5)

Reserved, do not change.

Definition at line 549 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_SRDCR

#define MCCI_STM32H7_REG_PWR_SRDCR   (MCCI_STM32H7_REG_PWR + 0x18)

SmartRun domain control.

Definition at line 495 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_SRDCR_RSV0

#define MCCI_STM32H7_REG_PWR_SRDCR_RSV0   UINT32_C(0x00001FFF)

Reserved, don't change.

Definition at line 613 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_SRDCR_RSV16

#define MCCI_STM32H7_REG_PWR_SRDCR_RSV16   UINT32_C(0xFFFF0000)

Reserved, don't change.

Definition at line 606 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_SRDCR_VOS

#define MCCI_STM32H7_REG_PWR_SRDCR_VOS   (UINT32_C(3) << 14)

voltage scaling selection according to performance

Definition at line 607 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_SRDCR_VOS_SCALE0

#define MCCI_STM32H7_REG_PWR_SRDCR_VOS_SCALE0   (UINT32_C(3) << 14)

scale 0

Definition at line 611 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_SRDCR_VOS_SCALE1

#define MCCI_STM32H7_REG_PWR_SRDCR_VOS_SCALE1   (UINT32_C(2) << 14)

scale 1

Definition at line 610 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_SRDCR_VOS_SCALE2

#define MCCI_STM32H7_REG_PWR_SRDCR_VOS_SCALE2   (UINT32_C(1) << 14)

scale 2

Definition at line 609 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_SRDCR_VOS_SCALE3

#define MCCI_STM32H7_REG_PWR_SRDCR_VOS_SCALE3   (UINT32_C(0) << 14)

scale 3

Definition at line 608 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_SRDCR_VOSRDY

#define MCCI_STM32H7_REG_PWR_SRDCR_VOSRDY   (UINT32_C(1) << 13)

VOS ready bit for VCORE voltage scaling output selection.

Definition at line 612 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPCR

#define MCCI_STM32H7_REG_PWR_WKUPCR   (MCCI_STM32H7_REG_PWR + 0x20)

wakeup clear

Definition at line 496 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPCR_RSV6

#define MCCI_STM32H7_REG_PWR_WKUPCR_RSV6   UINT32_C(0xFFFFFC00)

Reserved, don't change.

Definition at line 618 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC

#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC (   n)    (UINT32_C(1) << ((n)-1))

Definition at line 626 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC1

#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC1   (UINT32_C(1) << 0)

clear wakeup pin flag for WKUP1

Definition at line 624 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC2

#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC2   (UINT32_C(1) << 1)

clear wakeup pin flag for WKUP2

Definition at line 623 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC3

#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC3   (UINT32_C(1) << 2)

clear wakeup pin flag for WKUP3

Definition at line 622 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC4

#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC4   (UINT32_C(1) << 3)

clear wakeup pin flag for WKUP4

Definition at line 621 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC5

#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC5   (UINT32_C(1) << 4)

clear wakeup pin flag for WKUP5

Definition at line 620 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC6

#define MCCI_STM32H7_REG_PWR_WKUPCR_WKUPC6   (UINT32_C(1) << 5)

clear wakeup pin flag for WKUP6

Definition at line 619 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR

#define MCCI_STM32H7_REG_PWR_WKUPEPR   (MCCI_STM32H7_REG_PWR + 0x28)

wakeup enable and polarity

Definition at line 498 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_NOPU

#define MCCI_STM32H7_REG_PWR_WKUPEPR_NOPU (   n)    (UINT32_C(0) << ((((n)-1)*2)+16))

no pull-up WKUPn

Definition at line 652 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_PD

#define MCCI_STM32H7_REG_PWR_WKUPEPR_PD (   n)    (UINT32_C(2) << ((((n)-1)*2)+16))

pull-down WKUPn

Definition at line 654 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_PU

#define MCCI_STM32H7_REG_PWR_WKUPEPR_PU (   n)    (UINT32_C(1) << ((((n)-1)*2)+16))

pull-up WKUPn

Definition at line 653 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD1

#define MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD1   (UINT32_C(3) << 16)

wakeup pin pull configuration for WKUP1

Definition at line 650 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD2

#define MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD2   (UINT32_C(3) << 18)

wakeup pin pull configuration for WKUP2

Definition at line 649 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD3

#define MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD3   (UINT32_C(3) << 20)

wakeup pin pull configuration for WKUP3

Definition at line 648 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD4

#define MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD4   (UINT32_C(3) << 22)

wakeup pin pull configuration for WKUP4

Definition at line 647 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD5

#define MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD5   (UINT32_C(3) << 24)

wakeup pin pull configuration for WKUP5

Definition at line 646 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD6

#define MCCI_STM32H7_REG_PWR_WKUPEPR_PUPD6   (UINT32_C(3) << 26)

wakeup pin pull configuration for WKUP6

Definition at line 645 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_RSV14

#define MCCI_STM32H7_REG_PWR_WKUPEPR_RSV14   (UINT32_C(3) << 14)

Reserved, don't change.

Definition at line 656 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_RSV28

#define MCCI_STM32H7_REG_PWR_WKUPEPR_RSV28   UINT32_C(0xF0000000)

Reserved, don't change.

Definition at line 644 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_RSV6

#define MCCI_STM32H7_REG_PWR_WKUPEPR_RSV6   (UINT32_C(3) << 6)

Reserved, don't change.

Definition at line 663 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN1

#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN1   (UINT32_C(1) << 0)

enable wakeup pin for WKUP1

Definition at line 669 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN2

#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN2   (UINT32_C(1) << 1)

enable wakeup pin for WKUP2

Definition at line 668 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN3

#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN3   (UINT32_C(1) << 2)

enable wakeup pin for WKUP3

Definition at line 667 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN4

#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN4   (UINT32_C(1) << 3)

enable wakeup pin for WKUP4

Definition at line 666 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN5

#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN5   (UINT32_C(1) << 4)

enable wakeup pin for WKUP5

Definition at line 665 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN6

#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPEN6   (UINT32_C(1) << 5)

enable wakeup pin for WKUP6

Definition at line 664 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP1

#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP1   (UINT32_C(1) << 8)

wakeup pin polarity for WKUP1

Definition at line 662 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP2

#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP2   (UINT32_C(1) << 9)

wakeup pin polarity for WKUP2

Definition at line 661 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP3

#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP3   (UINT32_C(1) << 10)

wakeup pin polarity for WKUP3

Definition at line 660 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP4

#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP4   (UINT32_C(1) << 11)

wakeup pin polarity for WKUP4

Definition at line 659 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP5

#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP5   (UINT32_C(1) << 12)

wakeup pin polarity for WKUP5

Definition at line 658 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP6

#define MCCI_STM32H7_REG_PWR_WKUPEPR_WKUPP6   (UINT32_C(1) << 13)

wakeup pin polarity for WKUP6

Definition at line 657 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPFR

#define MCCI_STM32H7_REG_PWR_WKUPFR   (MCCI_STM32H7_REG_PWR + 0x24)

wakeup flag

Definition at line 497 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPFR_RSV6

#define MCCI_STM32H7_REG_PWR_WKUPFR_RSV6   UINT32_C(0xFFFFFC00)

Reserved, don't change.

Definition at line 631 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF

#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF (   n)    (UINT32_C(1) << ((n)-1))

Definition at line 639 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF1

#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF1   (UINT32_C(1) << 0)

wakeup pin flag for WKUP1

Definition at line 637 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF2

#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF2   (UINT32_C(1) << 1)

wakeup pin flag for WKUP2

Definition at line 636 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF3

#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF3   (UINT32_C(1) << 2)

wakeup pin flag for WKUP3

Definition at line 635 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF4

#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF4   (UINT32_C(1) << 3)

wakeup pin flag for WKUP4

Definition at line 634 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF5

#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF5   (UINT32_C(1) << 4)

wakeup pin flag for WKUP5

Definition at line 633 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF6

#define MCCI_STM32H7_REG_PWR_WKUPFR_WKUPF6   (UINT32_C(1) << 5)

wakeup pin flag for WKUP6

Definition at line 632 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RAMECC

#define MCCI_STM32H7_REG_RAMECC   UINT32_C(0x52009000)

Section 3.4: RAMECC register map (1K)

Definition at line 142 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC

#define MCCI_STM32H7_REG_RCC   UINT32_C(0x58024400)

Section 8.7: RCC register map (1K)

Definition at line 176 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1ENR

#define MCCI_STM32H7_REG_RCC_AHB1ENR   (MCCI_STM32H7_REG_RCC + 0x138)

AHB1 clock.

Definition at line 718 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1ENR_ADC12EN

#define MCCI_STM32H7_REG_RCC_AHB1ENR_ADC12EN   (UINT32_C(1) << 5)

Definition at line 1534 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1ENR_CRCEN

#define MCCI_STM32H7_REG_RCC_AHB1ENR_CRCEN   (UINT32_C(1) << 9)

Definition at line 1532 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1ENR_DMA1EN

#define MCCI_STM32H7_REG_RCC_AHB1ENR_DMA1EN   (UINT32_C(1) << 0)

Definition at line 1537 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1ENR_DMA2EN

#define MCCI_STM32H7_REG_RCC_AHB1ENR_DMA2EN   (UINT32_C(1) << 1)

Definition at line 1536 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1ENR_RSV10

#define MCCI_STM32H7_REG_RCC_AHB1ENR_RSV10   (UINT32_C(0x7FFF) << 10)

Definition at line 1531 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1ENR_RSV2

#define MCCI_STM32H7_REG_RCC_AHB1ENR_RSV2   (UINT32_C(7) << 2)

Definition at line 1535 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1ENR_RSV27

#define MCCI_STM32H7_REG_RCC_AHB1ENR_RSV27   (UINT32_C(0x1F) << 27)

Definition at line 1528 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1ENR_RSV6

#define MCCI_STM32H7_REG_RCC_AHB1ENR_RSV6   (UINT32_C(7) << 6)

Definition at line 1533 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1ENR_USB1OTGEN

#define MCCI_STM32H7_REG_RCC_AHB1ENR_USB1OTGEN   (UINT32_C(1) << 25)

Definition at line 1530 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1ENR_USB1ULPIEN

#define MCCI_STM32H7_REG_RCC_AHB1ENR_USB1ULPIEN   (UINT32_C(1) << 26)

Definition at line 1529 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1LPENR

#define MCCI_STM32H7_REG_RCC_AHB1LPENR   (MCCI_STM32H7_REG_RCC + 0x160)

AHB1 sleep clock.

Definition at line 727 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1LPENR_ADC12LPEN

#define MCCI_STM32H7_REG_RCC_AHB1LPENR_ADC12LPEN   (UINT32_C(1) << 5)

Definition at line 1722 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1LPENR_CRCLPEN

#define MCCI_STM32H7_REG_RCC_AHB1LPENR_CRCLPEN   (UINT32_C(1) << 9)

Definition at line 1720 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1LPENR_DMA1LPEN

#define MCCI_STM32H7_REG_RCC_AHB1LPENR_DMA1LPEN   (UINT32_C(1) << 0)

Definition at line 1725 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1LPENR_DMA2LPEN

#define MCCI_STM32H7_REG_RCC_AHB1LPENR_DMA2LPEN   (UINT32_C(1) << 1)

Definition at line 1724 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1LPENR_RSV10

#define MCCI_STM32H7_REG_RCC_AHB1LPENR_RSV10   (UINT32_C(0x7FFF) << 10)

Definition at line 1719 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1LPENR_RSV2

#define MCCI_STM32H7_REG_RCC_AHB1LPENR_RSV2   (UINT32_C(7) << 2)

Definition at line 1723 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1LPENR_RSV27

#define MCCI_STM32H7_REG_RCC_AHB1LPENR_RSV27   (UINT32_C(0x1F) << 27)

Definition at line 1716 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1LPENR_RSV6

#define MCCI_STM32H7_REG_RCC_AHB1LPENR_RSV6   (UINT32_C(7) << 6)

Definition at line 1721 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1LPENR_USB1OTGLPEN

#define MCCI_STM32H7_REG_RCC_AHB1LPENR_USB1OTGLPEN   (UINT32_C(1) << 25)

Definition at line 1718 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1LPENR_USB1ULPILPEN

#define MCCI_STM32H7_REG_RCC_AHB1LPENR_USB1ULPILPEN   (UINT32_C(1) << 26)

Definition at line 1717 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1RSTR

#define MCCI_STM32H7_REG_RCC_AHB1RSTR   (MCCI_STM32H7_REG_RCC + 0x80)

AHB1 peripheral reset.

Definition at line 706 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1RSTR_ADC12RST

#define MCCI_STM32H7_REG_RCC_AHB1RSTR_ADC12RST   (UINT32_C(1) << 5)

Definition at line 1291 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1RSTR_CRCRST

#define MCCI_STM32H7_REG_RCC_AHB1RSTR_CRCRST   (UINT32_C(1) << 9)

Definition at line 1289 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1RSTR_DMA1RST

#define MCCI_STM32H7_REG_RCC_AHB1RSTR_DMA1RST   (UINT32_C(1) << 0)

Definition at line 1294 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1RSTR_DMA2RST

#define MCCI_STM32H7_REG_RCC_AHB1RSTR_DMA2RST   (UINT32_C(1) << 1)

Definition at line 1293 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1RSTR_RSV10

#define MCCI_STM32H7_REG_RCC_AHB1RSTR_RSV10   (UINT32_C(0x7FFF) << 10)

Definition at line 1288 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1RSTR_RSV2

#define MCCI_STM32H7_REG_RCC_AHB1RSTR_RSV2   (UINT32_C(7) << 2)

Definition at line 1292 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1RSTR_RSV26

#define MCCI_STM32H7_REG_RCC_AHB1RSTR_RSV26   (UINT32_C(0x3F) << 26)

Definition at line 1286 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1RSTR_RSV6

#define MCCI_STM32H7_REG_RCC_AHB1RSTR_RSV6   (UINT32_C(7) << 6)

Definition at line 1290 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB1RSTR_USB1OTGRST

#define MCCI_STM32H7_REG_RCC_AHB1RSTR_USB1OTGRST   (UINT32_C(1) << 25)

Definition at line 1287 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2ENR

#define MCCI_STM32H7_REG_RCC_AHB2ENR   (MCCI_STM32H7_REG_RCC + 0x13C)

AHB2 clock.

Definition at line 719 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2ENR_AHBSRAM1EN

#define MCCI_STM32H7_REG_RCC_AHB2ENR_AHBSRAM1EN   (UINT32_C(1) << 29)

Definition at line 1544 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2ENR_AHBSRAM2EN

#define MCCI_STM32H7_REG_RCC_AHB2ENR_AHBSRAM2EN   (UINT32_C(1) << 30)

Definition at line 1543 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2ENR_BDMA1EN

#define MCCI_STM32H7_REG_RCC_AHB2ENR_BDMA1EN   (UINT32_C(1) << 11)

Definition at line 1546 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2ENR_CRYPTEN

#define MCCI_STM32H7_REG_RCC_AHB2ENR_CRYPTEN   (UINT32_C(1) << 4)

Definition at line 1552 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2ENR_DCMIEN

#define MCCI_STM32H7_REG_RCC_AHB2ENR_DCMIEN   (UINT32_C(1) << 0)

Definition at line 1556 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2ENR_HASHEN

#define MCCI_STM32H7_REG_RCC_AHB2ENR_HASHEN   (UINT32_C(1) << 5)

Definition at line 1551 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2ENR_HSEMEN

#define MCCI_STM32H7_REG_RCC_AHB2ENR_HSEMEN   (UINT32_C(1) << 2)

Definition at line 1554 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2ENR_PSSIEN

#define MCCI_STM32H7_REG_RCC_AHB2ENR_PSSIEN   (UINT32_C(1) << 0)

Definition at line 1557 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2ENR_RNGEN

#define MCCI_STM32H7_REG_RCC_AHB2ENR_RNGEN   (UINT32_C(1) << 6)

Definition at line 1550 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2ENR_RSV1

#define MCCI_STM32H7_REG_RCC_AHB2ENR_RSV1   (UINT32_C(1) << 1)

Definition at line 1555 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2ENR_RSV10

#define MCCI_STM32H7_REG_RCC_AHB2ENR_RSV10   (UINT32_C(1) << 10)

Definition at line 1547 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2ENR_RSV12

#define MCCI_STM32H7_REG_RCC_AHB2ENR_RSV12   (UINT32_C(0x1FFFF) << 12)

Definition at line 1545 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2ENR_RSV3

#define MCCI_STM32H7_REG_RCC_AHB2ENR_RSV3   (UINT32_C(1) << 3)

Definition at line 1553 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2ENR_RSV31

#define MCCI_STM32H7_REG_RCC_AHB2ENR_RSV31   (UINT32_C(1) << 31)

Definition at line 1542 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2ENR_RSV7

#define MCCI_STM32H7_REG_RCC_AHB2ENR_RSV7   (UINT32_C(3) << 7)

Definition at line 1549 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2ENR_SDMMC2EN

#define MCCI_STM32H7_REG_RCC_AHB2ENR_SDMMC2EN   (UINT32_C(1) << 9)

Definition at line 1548 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2LPENR

#define MCCI_STM32H7_REG_RCC_AHB2LPENR   (MCCI_STM32H7_REG_RCC + 0x164)

AHB2 sleep clock.

Definition at line 728 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2LPENR_AHBSRAM1LPEN

#define MCCI_STM32H7_REG_RCC_AHB2LPENR_AHBSRAM1LPEN   (UINT32_C(1) << 29)

Definition at line 1732 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2LPENR_AHBSRAM2LPEN

#define MCCI_STM32H7_REG_RCC_AHB2LPENR_AHBSRAM2LPEN   (UINT32_C(1) << 30)

Definition at line 1731 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2LPENR_CRYPTLPEN

#define MCCI_STM32H7_REG_RCC_AHB2LPENR_CRYPTLPEN   (UINT32_C(1) << 4)

Definition at line 1740 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2LPENR_DCMILPEN

#define MCCI_STM32H7_REG_RCC_AHB2LPENR_DCMILPEN   (UINT32_C(1) << 0)

Definition at line 1742 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2LPENR_DFSDMDMALPEN

#define MCCI_STM32H7_REG_RCC_AHB2LPENR_DFSDMDMALPEN   (UINT32_C(1) << 11)

Definition at line 1734 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2LPENR_HASHLPEN

#define MCCI_STM32H7_REG_RCC_AHB2LPENR_HASHLPEN   (UINT32_C(1) << 5)

Definition at line 1739 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2LPENR_PSSILPEN

#define MCCI_STM32H7_REG_RCC_AHB2LPENR_PSSILPEN   (UINT32_C(1) << 0)

Definition at line 1743 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2LPENR_RNGLPEN

#define MCCI_STM32H7_REG_RCC_AHB2LPENR_RNGLPEN   (UINT32_C(1) << 6)

Definition at line 1738 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2LPENR_RSV1

#define MCCI_STM32H7_REG_RCC_AHB2LPENR_RSV1   (UINT32_C(7) << 1)

Definition at line 1741 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2LPENR_RSV10

#define MCCI_STM32H7_REG_RCC_AHB2LPENR_RSV10   (UINT32_C(1) << 10)

Definition at line 1735 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2LPENR_RSV12

#define MCCI_STM32H7_REG_RCC_AHB2LPENR_RSV12   (UINT32_C(0x1FFFF) << 12)

Definition at line 1733 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2LPENR_RSV31

#define MCCI_STM32H7_REG_RCC_AHB2LPENR_RSV31   (UINT32_C(1) << 31)

Definition at line 1730 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2LPENR_RSV7

#define MCCI_STM32H7_REG_RCC_AHB2LPENR_RSV7   (UINT32_C(3) << 7)

Definition at line 1737 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2LPENR_SDMMC2LPEN

#define MCCI_STM32H7_REG_RCC_AHB2LPENR_SDMMC2LPEN   (UINT32_C(1) << 9)

Definition at line 1736 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2RSTR

#define MCCI_STM32H7_REG_RCC_AHB2RSTR   (MCCI_STM32H7_REG_RCC + 0x84)

AHB2 peripheral reset.

Definition at line 707 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2RSTR_BDMA1RST

#define MCCI_STM32H7_REG_RCC_AHB2RSTR_BDMA1RST   (UINT32_C(1) << 11)

Definition at line 1300 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2RSTR_CRYPTRST

#define MCCI_STM32H7_REG_RCC_AHB2RSTR_CRYPTRST   (UINT32_C(1) << 4)

Definition at line 1306 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2RSTR_DCMIRST

#define MCCI_STM32H7_REG_RCC_AHB2RSTR_DCMIRST   (UINT32_C(1) << 0)

Definition at line 1310 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2RSTR_HASHRST

#define MCCI_STM32H7_REG_RCC_AHB2RSTR_HASHRST   (UINT32_C(1) << 5)

Definition at line 1305 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2RSTR_HSEMRST

#define MCCI_STM32H7_REG_RCC_AHB2RSTR_HSEMRST   (UINT32_C(1) << 2)

Definition at line 1308 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2RSTR_PSSIRST

#define MCCI_STM32H7_REG_RCC_AHB2RSTR_PSSIRST   (UINT32_C(1) << 0)

Definition at line 1311 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2RSTR_RNGRST

#define MCCI_STM32H7_REG_RCC_AHB2RSTR_RNGRST   (UINT32_C(1) << 6)

Definition at line 1304 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2RSTR_RSV1

#define MCCI_STM32H7_REG_RCC_AHB2RSTR_RSV1   (UINT32_C(1) << 1)

Definition at line 1309 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2RSTR_RSV10

#define MCCI_STM32H7_REG_RCC_AHB2RSTR_RSV10   (UINT32_C(1) << 10)

Definition at line 1301 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2RSTR_RSV12

#define MCCI_STM32H7_REG_RCC_AHB2RSTR_RSV12   UINT32_C(0xFFFFF000)

Definition at line 1299 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2RSTR_RSV3

#define MCCI_STM32H7_REG_RCC_AHB2RSTR_RSV3   (UINT32_C(1) << 3)

Definition at line 1307 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2RSTR_RSV7

#define MCCI_STM32H7_REG_RCC_AHB2RSTR_RSV7   (UINT32_C(3) << 7)

Definition at line 1303 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB2RSTR_SDMMC2RST

#define MCCI_STM32H7_REG_RCC_AHB2RSTR_SDMMC2RST   (UINT32_C(1) << 9)

Definition at line 1302 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3ENR

#define MCCI_STM32H7_REG_RCC_AHB3ENR   (MCCI_STM32H7_REG_RCC + 0x134)

AHB3 clock.

Definition at line 717 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3ENR_DMA2DEN

#define MCCI_STM32H7_REG_RCC_AHB3ENR_DMA2DEN   (UINT32_C(1) << 4)

Definition at line 1521 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3ENR_FMCEN

#define MCCI_STM32H7_REG_RCC_AHB3ENR_FMCEN   (UINT32_C(1) << 12)

Definition at line 1518 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3ENR_GFXMMUEN

#define MCCI_STM32H7_REG_RCC_AHB3ENR_GFXMMUEN   (UINT32_C(1) << 24)

Definition at line 1507 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3ENR_JPGDECEN

#define MCCI_STM32H7_REG_RCC_AHB3ENR_JPGDECEN   (UINT32_C(1) << 5)

Definition at line 1520 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3ENR_MDMAEN

#define MCCI_STM32H7_REG_RCC_AHB3ENR_MDMAEN   (UINT32_C(1) << 0)

Definition at line 1523 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3ENR_OCTOSPI1EN

#define MCCI_STM32H7_REG_RCC_AHB3ENR_OCTOSPI1EN   (UINT32_C(1) << 14)

Definition at line 1516 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3ENR_OCTOSPI2EN

#define MCCI_STM32H7_REG_RCC_AHB3ENR_OCTOSPI2EN   (UINT32_C(1) << 19)

Definition at line 1512 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3ENR_OCTOSPIMEN

#define MCCI_STM32H7_REG_RCC_AHB3ENR_OCTOSPIMEN   (UINT32_C(1) << 21)

Definition at line 1510 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3ENR_OTFD1EN

#define MCCI_STM32H7_REG_RCC_AHB3ENR_OTFD1EN   (UINT32_C(1) << 22)

Definition at line 1509 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3ENR_OTFD2EN

#define MCCI_STM32H7_REG_RCC_AHB3ENR_OTFD2EN   (UINT32_C(1) << 23)

Definition at line 1508 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3ENR_RSV1

#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV1   (UINT32_C(7) << 1)

Definition at line 1522 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3ENR_RSV13

#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV13   (UINT32_C(1) << 13)

Definition at line 1517 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3ENR_RSV15

#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV15   (UINT32_C(1) << 15)

Definition at line 1515 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3ENR_RSV17

#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV17   (UINT32_C(3) << 17)

Definition at line 1513 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3ENR_RSV20

#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV20   (UINT32_C(1) << 20)

Definition at line 1511 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3ENR_RSV25

#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV25   (UINT32_C(0x7F) << 25)

Definition at line 1506 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3ENR_RSV6

#define MCCI_STM32H7_REG_RCC_AHB3ENR_RSV6   (UINT32_C(0x3F) << 6)

Definition at line 1519 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3ENR_SDMMC1EN

#define MCCI_STM32H7_REG_RCC_AHB3ENR_SDMMC1EN   (UINT32_C(1) << 16)

Definition at line 1514 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR

#define MCCI_STM32H7_REG_RCC_AHB3LPENR   (MCCI_STM32H7_REG_RCC + 0x15C)

AHB3 sleep clock.

Definition at line 726 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_AXISRAM1LPEN

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_AXISRAM1LPEN   (UINT32_C(1) << 31)

Definition at line 1686 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_AXISRAM2LPEN

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_AXISRAM2LPEN   (UINT32_C(1) << 26)

Definition at line 1691 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_AXISRAM3LPEN

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_AXISRAM3LPEN   (UINT32_C(1) << 27)

Definition at line 1690 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_DMA2DLPEN

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_DMA2DLPEN   (UINT32_C(1) << 4)

Definition at line 1709 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_DTCM1LPEN

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_DTCM1LPEN   (UINT32_C(1) << 28)

Definition at line 1689 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_DTCM2LPEN

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_DTCM2LPEN   (UINT32_C(1) << 29)

Definition at line 1688 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_FLITFLPEN

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_FLITFLPEN   (UINT32_C(1) << 8)

Definition at line 1706 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_FMCLPEN

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_FMCLPEN   (UINT32_C(1) << 12)

Definition at line 1704 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_GFXMMULPEN

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_GFXMMULPEN   (UINT32_C(1) << 24)

Definition at line 1693 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_ITCMLPEN

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_ITCMLPEN   (UINT32_C(1) << 30)

Definition at line 1687 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_JPGDECLPEN

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_JPGDECLPEN   (UINT32_C(1) << 5)

Definition at line 1708 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_MDMALPEN

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_MDMALPEN   (UINT32_C(1) << 0)

Definition at line 1711 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_OCTOSPI1LPEN

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_OCTOSPI1LPEN   (UINT32_C(1) << 14)

Definition at line 1702 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_OCTOSPI2LPEN

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_OCTOSPI2LPEN   (UINT32_C(1) << 19)

Definition at line 1698 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_OCTOSPIMLPEN

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_OCTOSPIMLPEN   (UINT32_C(1) << 21)

Definition at line 1696 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_OTFD1LPEN

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_OTFD1LPEN   (UINT32_C(1) << 22)

Definition at line 1695 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_OTFD2LPEN

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_OTFD2LPEN   (UINT32_C(1) << 23)

Definition at line 1694 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV1

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV1   (UINT32_C(7) << 1)

Definition at line 1710 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV13

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV13   (UINT32_C(1) << 13)

Definition at line 1703 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV15

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV15   (UINT32_C(1) << 15)

Definition at line 1701 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV17

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV17   (UINT32_C(3) << 17)

Definition at line 1699 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV20

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV20   (UINT32_C(1) << 20)

Definition at line 1697 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV25

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV25   (UINT32_C(1) << 25)

Definition at line 1692 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV6

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV6   (UINT32_C(3) << 6)

Definition at line 1707 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV9

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_RSV9   (UINT32_C(7) << 9)

Definition at line 1705 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3LPENR_SDMMC1LPEN

#define MCCI_STM32H7_REG_RCC_AHB3LPENR_SDMMC1LPEN   (UINT32_C(1) << 16)

Definition at line 1700 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3RSTR

#define MCCI_STM32H7_REG_RCC_AHB3RSTR   (MCCI_STM32H7_REG_RCC + 0x7C)

AHB3 reset.

Definition at line 705 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3RSTR_DMA2DRST

#define MCCI_STM32H7_REG_RCC_AHB3RSTR_DMA2DRST   (UINT32_C(1) << 4)

Definition at line 1279 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3RSTR_FMCRST

#define MCCI_STM32H7_REG_RCC_AHB3RSTR_FMCRST   (UINT32_C(1) << 12)

Definition at line 1276 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3RSTR_GFXMMURST

#define MCCI_STM32H7_REG_RCC_AHB3RSTR_GFXMMURST   (UINT32_C(1) << 24)

Definition at line 1265 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3RSTR_JPGDECRST

#define MCCI_STM32H7_REG_RCC_AHB3RSTR_JPGDECRST   (UINT32_C(1) << 5)

Definition at line 1278 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3RSTR_MDMARST

#define MCCI_STM32H7_REG_RCC_AHB3RSTR_MDMARST   (UINT32_C(1) << 0)

Definition at line 1281 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3RSTR_OCTOSPI1RST

#define MCCI_STM32H7_REG_RCC_AHB3RSTR_OCTOSPI1RST   (UINT32_C(1) << 14)

Definition at line 1274 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3RSTR_OCTOSPI2RST

#define MCCI_STM32H7_REG_RCC_AHB3RSTR_OCTOSPI2RST   (UINT32_C(1) << 19)

Definition at line 1270 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3RSTR_OCTOSPIMRST

#define MCCI_STM32H7_REG_RCC_AHB3RSTR_OCTOSPIMRST   (UINT32_C(1) << 21)

Definition at line 1268 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3RSTR_OTFD1RST

#define MCCI_STM32H7_REG_RCC_AHB3RSTR_OTFD1RST   (UINT32_C(1) << 22)

Definition at line 1267 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3RSTR_OTFD2RST

#define MCCI_STM32H7_REG_RCC_AHB3RSTR_OTFD2RST   (UINT32_C(1) << 23)

Definition at line 1266 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV1

#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV1   (UINT32_C(7) << 1)

Definition at line 1280 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV13

#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV13   (UINT32_C(1) << 13)

Definition at line 1275 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV15

#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV15   (UINT32_C(1) << 15)

Definition at line 1273 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV17

#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV17   (UINT32_C(3) << 17)

Definition at line 1271 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV20

#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV20   (UINT32_C(1) << 20)

Definition at line 1269 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV25

#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV25   (UINT32_C(0x7F) << 25)

Definition at line 1264 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV6

#define MCCI_STM32H7_REG_RCC_AHB3RSTR_RSV6   (UINT32_C(0x3F) << 6)

Definition at line 1277 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB3RSTR_SDMMC1RST

#define MCCI_STM32H7_REG_RCC_AHB3RSTR_SDMMC1RST   (UINT32_C(1) << 16)

Definition at line 1272 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4ENR

#define MCCI_STM32H7_REG_RCC_AHB4ENR   (MCCI_STM32H7_REG_RCC + 0x140)

AHB4 clock.

Definition at line 720 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4ENR_BDMA2EN

#define MCCI_STM32H7_REG_RCC_AHB4ENR_BDMA2EN   (UINT32_C(1) << 21)

Definition at line 1566 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4ENR_BKPRAMEN

#define MCCI_STM32H7_REG_RCC_AHB4ENR_BKPRAMEN   (UINT32_C(1) << 28)

Definition at line 1564 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOAEN

#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOAEN   (UINT32_C(1) << 0)

Definition at line 1578 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOBEN

#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOBEN   (UINT32_C(1) << 1)

Definition at line 1577 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOCEN

#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOCEN   (UINT32_C(1) << 2)

Definition at line 1576 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4ENR_GPIODEN

#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIODEN   (UINT32_C(1) << 3)

Definition at line 1575 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOEEN

#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOEEN   (UINT32_C(1) << 4)

Definition at line 1574 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOFEN

#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOFEN   (UINT32_C(1) << 5)

Definition at line 1573 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOGEN

#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOGEN   (UINT32_C(1) << 6)

Definition at line 1572 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOHEN

#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOHEN   (UINT32_C(1) << 7)

Definition at line 1571 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOIEN

#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOIEN   (UINT32_C(1) << 8)

Definition at line 1570 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOJEN

#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOJEN   (UINT32_C(1) << 9)

Definition at line 1569 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOKEN

#define MCCI_STM32H7_REG_RCC_AHB4ENR_GPIOKEN   (UINT32_C(1) << 10)

Definition at line 1568 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4ENR_RSV11

#define MCCI_STM32H7_REG_RCC_AHB4ENR_RSV11   (UINT32_C(0x3FF) << 11)

Definition at line 1567 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4ENR_RSV22

#define MCCI_STM32H7_REG_RCC_AHB4ENR_RSV22   (UINT32_C(0x3F) << 22)

Definition at line 1565 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4ENR_RSV30

#define MCCI_STM32H7_REG_RCC_AHB4ENR_RSV30   (UINT32_C(3) << 30)

Definition at line 1562 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4ENR_SRDSRAMEN

#define MCCI_STM32H7_REG_RCC_AHB4ENR_SRDSRAMEN   (UINT32_C(1) << 29)

Definition at line 1563 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4LPENR

#define MCCI_STM32H7_REG_RCC_AHB4LPENR   (MCCI_STM32H7_REG_RCC + 0x168)

AHB4 sleep clock.

Definition at line 729 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4LPENR_BDMA2LPEN

#define MCCI_STM32H7_REG_RCC_AHB4LPENR_BDMA2LPEN   (UINT32_C(1) << 21)

Definition at line 1752 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4LPENR_BKPRAMLPEN

#define MCCI_STM32H7_REG_RCC_AHB4LPENR_BKPRAMLPEN   (UINT32_C(1) << 28)

Definition at line 1750 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOALPEN

#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOALPEN   (UINT32_C(1) << 0)

Definition at line 1764 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOBLPEN

#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOBLPEN   (UINT32_C(1) << 1)

Definition at line 1763 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOCLPEN

#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOCLPEN   (UINT32_C(1) << 2)

Definition at line 1762 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIODLPEN

#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIODLPEN   (UINT32_C(1) << 3)

Definition at line 1761 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOELPEN

#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOELPEN   (UINT32_C(1) << 4)

Definition at line 1760 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOFLPEN

#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOFLPEN   (UINT32_C(1) << 5)

Definition at line 1759 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOGLPEN

#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOGLPEN   (UINT32_C(1) << 6)

Definition at line 1758 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOHLPEN

#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOHLPEN   (UINT32_C(1) << 7)

Definition at line 1757 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOILPEN

#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOILPEN   (UINT32_C(1) << 8)

Definition at line 1756 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOJLPEN

#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOJLPEN   (UINT32_C(1) << 9)

Definition at line 1755 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOKLPEN

#define MCCI_STM32H7_REG_RCC_AHB4LPENR_GPIOKLPEN   (UINT32_C(1) << 10)

Definition at line 1754 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4LPENR_RSV11

#define MCCI_STM32H7_REG_RCC_AHB4LPENR_RSV11   (UINT32_C(0x3FF) << 11)

Definition at line 1753 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4LPENR_RSV22

#define MCCI_STM32H7_REG_RCC_AHB4LPENR_RSV22   (UINT32_C(0x3F) << 22)

Definition at line 1751 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4LPENR_RSV30

#define MCCI_STM32H7_REG_RCC_AHB4LPENR_RSV30   (UINT32_C(3) << 30)

Definition at line 1748 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4LPENR_SRDSRAMLPEN

#define MCCI_STM32H7_REG_RCC_AHB4LPENR_SRDSRAMLPEN   (UINT32_C(1) << 29)

Definition at line 1749 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4RSTR

#define MCCI_STM32H7_REG_RCC_AHB4RSTR   (MCCI_STM32H7_REG_RCC + 0x88)

AHB4 peripheral reset.

Definition at line 708 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4RSTR_BDMA2RST

#define MCCI_STM32H7_REG_RCC_AHB4RSTR_BDMA2RST   (UINT32_C(1) << 21)

Definition at line 1317 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOARST

#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOARST   (UINT32_C(1) << 0)

Definition at line 1329 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOBRST

#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOBRST   (UINT32_C(1) << 1)

Definition at line 1328 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOCRST

#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOCRST   (UINT32_C(1) << 2)

Definition at line 1327 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIODRST

#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIODRST   (UINT32_C(1) << 3)

Definition at line 1326 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOERST

#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOERST   (UINT32_C(1) << 4)

Definition at line 1325 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOFRST

#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOFRST   (UINT32_C(1) << 5)

Definition at line 1324 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOGRST

#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOGRST   (UINT32_C(1) << 6)

Definition at line 1323 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOHRST

#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOHRST   (UINT32_C(1) << 7)

Definition at line 1322 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOIRST

#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOIRST   (UINT32_C(1) << 8)

Definition at line 1321 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOJRST

#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOJRST   (UINT32_C(1) << 9)

Definition at line 1320 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOKRST

#define MCCI_STM32H7_REG_RCC_AHB4RSTR_GPIOKRST   (UINT32_C(1) << 10)

Definition at line 1319 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4RSTR_RSV11

#define MCCI_STM32H7_REG_RCC_AHB4RSTR_RSV11   (UINT32_C(0x3FF) << 11)

Definition at line 1318 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_AHB4RSTR_RSV22

#define MCCI_STM32H7_REG_RCC_AHB4RSTR_RSV22   UINT32_C(0xFFC00000)

Definition at line 1316 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HENR

#define MCCI_STM32H7_REG_RCC_APB1HENR   (MCCI_STM32H7_REG_RCC + 0x14C)

APB1 clock.

Definition at line 723 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HENR_CRSEN

#define MCCI_STM32H7_REG_RCC_APB1HENR_CRSEN   (UINT32_C(1) << 1)

Definition at line 1630 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HENR_FDCANEN

#define MCCI_STM32H7_REG_RCC_APB1HENR_FDCANEN   (UINT32_C(1) << 8)

Definition at line 1624 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HENR_MDIOSEN

#define MCCI_STM32H7_REG_RCC_APB1HENR_MDIOSEN   (UINT32_C(1) << 5)

Definition at line 1626 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HENR_OPAMPEN

#define MCCI_STM32H7_REG_RCC_APB1HENR_OPAMPEN   (UINT32_C(1) << 4)

Definition at line 1627 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HENR_RSV0

#define MCCI_STM32H7_REG_RCC_APB1HENR_RSV0   (UINT32_C(1) << 0)

Definition at line 1631 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HENR_RSV3

#define MCCI_STM32H7_REG_RCC_APB1HENR_RSV3   (UINT32_C(1) << 3)

Definition at line 1628 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HENR_RSV6

#define MCCI_STM32H7_REG_RCC_APB1HENR_RSV6   (UINT32_C(3) << 6)

Definition at line 1625 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HENR_RSV9

#define MCCI_STM32H7_REG_RCC_APB1HENR_RSV9   UINT32_C(0xFFFFFE00)

reserved, don't change

Definition at line 1623 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HENR_SWPMIEN

#define MCCI_STM32H7_REG_RCC_APB1HENR_SWPMIEN   (UINT32_C(1) << 2)

Definition at line 1629 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HLPENR

#define MCCI_STM32H7_REG_RCC_APB1HLPENR   (MCCI_STM32H7_REG_RCC + 0x174)

APB1 high-sleep clock.

Definition at line 732 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HLPENR_CRSLPEN

#define MCCI_STM32H7_REG_RCC_APB1HLPENR_CRSLPEN   (UINT32_C(1) << 1)

Definition at line 1816 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HLPENR_FDCANLPEN

#define MCCI_STM32H7_REG_RCC_APB1HLPENR_FDCANLPEN   (UINT32_C(1) << 8)

Definition at line 1810 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HLPENR_MDIOSLPEN

#define MCCI_STM32H7_REG_RCC_APB1HLPENR_MDIOSLPEN   (UINT32_C(1) << 5)

Definition at line 1812 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HLPENR_OPAMPLPEN

#define MCCI_STM32H7_REG_RCC_APB1HLPENR_OPAMPLPEN   (UINT32_C(1) << 4)

Definition at line 1813 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HLPENR_RSV0

#define MCCI_STM32H7_REG_RCC_APB1HLPENR_RSV0   (UINT32_C(1) << 0)

Definition at line 1817 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HLPENR_RSV3

#define MCCI_STM32H7_REG_RCC_APB1HLPENR_RSV3   (UINT32_C(1) << 3)

Definition at line 1814 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HLPENR_RSV6

#define MCCI_STM32H7_REG_RCC_APB1HLPENR_RSV6   (UINT32_C(3) << 6)

Definition at line 1811 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HLPENR_RSV9

#define MCCI_STM32H7_REG_RCC_APB1HLPENR_RSV9   UINT32_C(0xFFFFFE00)

reserved, don't change

Definition at line 1809 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HLPENR_SWPMILPEN

#define MCCI_STM32H7_REG_RCC_APB1HLPENR_SWPMILPEN   (UINT32_C(1) << 2)

Definition at line 1815 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HRSTR

#define MCCI_STM32H7_REG_RCC_APB1HRSTR   (MCCI_STM32H7_REG_RCC + 0x94)

APB1 peripheral reset.

Definition at line 711 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HRSTR_CRSRST

#define MCCI_STM32H7_REG_RCC_APB1HRSTR_CRSRST   (UINT32_C(1) << 1)

Definition at line 1379 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HRSTR_FDCANRST

#define MCCI_STM32H7_REG_RCC_APB1HRSTR_FDCANRST   (UINT32_C(1) << 8)

Definition at line 1373 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HRSTR_MDIOSRST

#define MCCI_STM32H7_REG_RCC_APB1HRSTR_MDIOSRST   (UINT32_C(1) << 5)

Definition at line 1375 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HRSTR_OPAMPRST

#define MCCI_STM32H7_REG_RCC_APB1HRSTR_OPAMPRST   (UINT32_C(1) << 4)

Definition at line 1376 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HRSTR_RSV0

#define MCCI_STM32H7_REG_RCC_APB1HRSTR_RSV0   (UINT32_C(1) << 0)

Definition at line 1380 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HRSTR_RSV3

#define MCCI_STM32H7_REG_RCC_APB1HRSTR_RSV3   (UINT32_C(1) << 3)

Definition at line 1377 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HRSTR_RSV6

#define MCCI_STM32H7_REG_RCC_APB1HRSTR_RSV6   (UINT32_C(3) << 6)

Definition at line 1374 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HRSTR_RSV9

#define MCCI_STM32H7_REG_RCC_APB1HRSTR_RSV9   UINT32_C(0xFFFFFE00)

reserved, don't change

Definition at line 1372 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1HRSTR_SWPMIRST

#define MCCI_STM32H7_REG_RCC_APB1HRSTR_SWPMIRST   (UINT32_C(1) << 2)

Definition at line 1378 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR

#define MCCI_STM32H7_REG_RCC_APB1LENR   (MCCI_STM32H7_REG_RCC + 0x148)

APB1 clock.

Definition at line 722 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_CECEN

#define MCCI_STM32H7_REG_RCC_APB1LENR_CECEN   (UINT32_C(1) << 27)

Definition at line 1596 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_DAC1EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_DAC1EN   (UINT32_C(1) << 29)

Definition at line 1594 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_I2C1EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_I2C1EN   (UINT32_C(1) << 21)

Definition at line 1600 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_I2C2EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_I2C2EN   (UINT32_C(1) << 22)

Definition at line 1599 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_I2C3EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_I2C3EN   (UINT32_C(1) << 23)

Definition at line 1598 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_LPTIM1EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_LPTIM1EN   (UINT32_C(1) << 9)

Definition at line 1609 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_RSV10

#define MCCI_STM32H7_REG_RCC_APB1LENR_RSV10   (UINT32_C(0xF) << 10)

Definition at line 1608 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_RSV24

#define MCCI_STM32H7_REG_RCC_APB1LENR_RSV24   (UINT32_C(7) << 24)

Definition at line 1597 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_RSV28

#define MCCI_STM32H7_REG_RCC_APB1LENR_RSV28   (UINT32_C(1) << 28)

Definition at line 1595 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_SPDIFRXEN

#define MCCI_STM32H7_REG_RCC_APB1LENR_SPDIFRXEN   (UINT32_C(1) << 16)

Definition at line 1605 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_SPI2EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_SPI2EN   (UINT32_C(1) << 14)

Definition at line 1607 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_SPI3EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_SPI3EN   (UINT32_C(1) << 15)

Definition at line 1606 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_TIM12EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM12EN   (UINT32_C(1) << 6)

Definition at line 1612 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_TIM13EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM13EN   (UINT32_C(1) << 7)

Definition at line 1611 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_TIM14EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM14EN   (UINT32_C(1) << 8)

Definition at line 1610 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_TIM2EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM2EN   (UINT32_C(1) << 0)

Definition at line 1618 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_TIM3EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM3EN   (UINT32_C(1) << 1)

Definition at line 1617 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_TIM4EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM4EN   (UINT32_C(1) << 2)

Definition at line 1616 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_TIM5EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM5EN   (UINT32_C(1) << 3)

Definition at line 1615 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_TIM6EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM6EN   (UINT32_C(1) << 4)

Definition at line 1614 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_TIM7EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_TIM7EN   (UINT32_C(1) << 5)

Definition at line 1613 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_UART7EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_UART7EN   (UINT32_C(1) << 30)

Definition at line 1593 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_UART8EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_UART8EN   (UINT32_C(1) << 31)

Definition at line 1592 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_USART2EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_USART2EN   (UINT32_C(1) << 17)

Definition at line 1604 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_USART3EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_USART3EN   (UINT32_C(1) << 18)

Definition at line 1603 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_USART4EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_USART4EN   (UINT32_C(1) << 19)

Definition at line 1602 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LENR_USART5EN

#define MCCI_STM32H7_REG_RCC_APB1LENR_USART5EN   (UINT32_C(1) << 20)

Definition at line 1601 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR

#define MCCI_STM32H7_REG_RCC_APB1LLPENR   (MCCI_STM32H7_REG_RCC + 0x170)

APB1 low-sleep clock.

Definition at line 731 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_CECLPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_CECLPEN   (UINT32_C(1) << 27)

Definition at line 1782 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_DAC1LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_DAC1LPEN   (UINT32_C(1) << 29)

Definition at line 1780 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_I2C1LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_I2C1LPEN   (UINT32_C(1) << 21)

Definition at line 1786 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_I2C2LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_I2C2LPEN   (UINT32_C(1) << 22)

Definition at line 1785 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_I2C3LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_I2C3LPEN   (UINT32_C(1) << 23)

Definition at line 1784 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_LPTIM1LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_LPTIM1LPEN   (UINT32_C(1) << 9)

Definition at line 1795 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_RSV10

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_RSV10   (UINT32_C(0xF) << 10)

Definition at line 1794 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_RSV24

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_RSV24   (UINT32_C(7) << 24)

Definition at line 1783 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_RSV28

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_RSV28   (UINT32_C(1) << 28)

Definition at line 1781 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_SPDIFRXLPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_SPDIFRXLPEN   (UINT32_C(1) << 16)

Definition at line 1791 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_SPI2LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_SPI2LPEN   (UINT32_C(1) << 14)

Definition at line 1793 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_SPI3LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_SPI3LPEN   (UINT32_C(1) << 15)

Definition at line 1792 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM12LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM12LPEN   (UINT32_C(1) << 6)

Definition at line 1798 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM13LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM13LPEN   (UINT32_C(1) << 7)

Definition at line 1797 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM14LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM14LPEN   (UINT32_C(1) << 8)

Definition at line 1796 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM2LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM2LPEN   (UINT32_C(1) << 0)

Definition at line 1804 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM3LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM3LPEN   (UINT32_C(1) << 1)

Definition at line 1803 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM4LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM4LPEN   (UINT32_C(1) << 2)

Definition at line 1802 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM5LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM5LPEN   (UINT32_C(1) << 3)

Definition at line 1801 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM6LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM6LPEN   (UINT32_C(1) << 4)

Definition at line 1800 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM7LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_TIM7LPEN   (UINT32_C(1) << 5)

Definition at line 1799 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_UART7LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_UART7LPEN   (UINT32_C(1) << 30)

Definition at line 1779 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_UART8LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_UART8LPEN   (UINT32_C(1) << 31)

Definition at line 1778 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_USART2LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_USART2LPEN   (UINT32_C(1) << 17)

Definition at line 1790 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_USART3LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_USART3LPEN   (UINT32_C(1) << 18)

Definition at line 1789 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_USART4LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_USART4LPEN   (UINT32_C(1) << 19)

Definition at line 1788 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LLPENR_USART5LPEN

#define MCCI_STM32H7_REG_RCC_APB1LLPENR_USART5LPEN   (UINT32_C(1) << 20)

Definition at line 1787 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR

#define MCCI_STM32H7_REG_RCC_APB1LRSTR   (MCCI_STM32H7_REG_RCC + 0x90)

APB1 peripheral reset.

Definition at line 710 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_CECRST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_CECRST   (UINT32_C(1) << 27)

Definition at line 1345 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_DAC1RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_DAC1RST   (UINT32_C(1) << 29)

Definition at line 1343 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_I2C1RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_I2C1RST   (UINT32_C(1) << 21)

Definition at line 1349 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_I2C2RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_I2C2RST   (UINT32_C(1) << 22)

Definition at line 1348 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_I2C3RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_I2C3RST   (UINT32_C(1) << 23)

Definition at line 1347 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_LPTIM1RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_LPTIM1RST   (UINT32_C(1) << 9)

Definition at line 1358 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_RSV10

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_RSV10   (UINT32_C(0xF) << 10)

Definition at line 1357 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_RSV24

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_RSV24   (UINT32_C(7) << 24)

Definition at line 1346 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_RSV28

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_RSV28   (UINT32_C(1) << 28)

Definition at line 1344 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_SPDIFRXRST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_SPDIFRXRST   (UINT32_C(1) << 16)

Definition at line 1354 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_SPI2RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_SPI2RST   (UINT32_C(1) << 14)

Definition at line 1356 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_SPI3RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_SPI3RST   (UINT32_C(1) << 15)

Definition at line 1355 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM12RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM12RST   (UINT32_C(1) << 6)

Definition at line 1361 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM13RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM13RST   (UINT32_C(1) << 7)

Definition at line 1360 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM14RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM14RST   (UINT32_C(1) << 8)

Definition at line 1359 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM2RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM2RST   (UINT32_C(1) << 0)

Definition at line 1367 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM3RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM3RST   (UINT32_C(1) << 1)

Definition at line 1366 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM4RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM4RST   (UINT32_C(1) << 2)

Definition at line 1365 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM5RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM5RST   (UINT32_C(1) << 3)

Definition at line 1364 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM6RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM6RST   (UINT32_C(1) << 4)

Definition at line 1363 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM7RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_TIM7RST   (UINT32_C(1) << 5)

Definition at line 1362 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_UART7RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_UART7RST   (UINT32_C(1) << 30)

Definition at line 1342 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_UART8RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_UART8RST   (UINT32_C(1) << 31)

Definition at line 1341 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_USART2RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_USART2RST   (UINT32_C(1) << 17)

Definition at line 1353 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_USART3RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_USART3RST   (UINT32_C(1) << 18)

Definition at line 1352 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_USART4RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_USART4RST   (UINT32_C(1) << 19)

Definition at line 1351 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB1LRSTR_USART5RST

#define MCCI_STM32H7_REG_RCC_APB1LRSTR_USART5RST   (UINT32_C(1) << 20)

Definition at line 1350 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR

#define MCCI_STM32H7_REG_RCC_APB2ENR   (MCCI_STM32H7_REG_RCC + 0x150)

APB2 clock.

Definition at line 724 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_DFSDM1EN

#define MCCI_STM32H7_REG_RCC_APB2ENR_DFSDM1EN   (UINT32_C(1) << 30)

DFSDM1 clock enable.

Definition at line 1637 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_RSV14

#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV14   (UINT32_C(3) << 14)

reserved, don't change

Definition at line 1647 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_RSV19

#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV19   (UINT32_C(1) << 19)

reserved, don't change

Definition at line 1643 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_RSV2

#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV2   (UINT32_C(3) << 2)

reserved, don't change

Definition at line 1655 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_RSV21

#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV21   (UINT32_C(1) << 21)

reserved, don't change

Definition at line 1641 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_RSV24

#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV24   (UINT32_C(0x3F) << 24)

reserved, don't change

Definition at line 1638 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_RSV31

#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV31   (UINT32_C(1) << 31)

reserved, don't change

Definition at line 1636 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_RSV8

#define MCCI_STM32H7_REG_RCC_APB2ENR_RSV8   (UINT32_C(0xF) << 8)

reserved, don't change

Definition at line 1650 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_SAI1EN

#define MCCI_STM32H7_REG_RCC_APB2ENR_SAI1EN   (UINT32_C(1) << 22)

SAI1 clock enable.

Definition at line 1640 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_SAI2EN

#define MCCI_STM32H7_REG_RCC_APB2ENR_SAI2EN   (UINT32_C(1) << 23)

SAI2 clock enable.

Definition at line 1639 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_SPI1EN

#define MCCI_STM32H7_REG_RCC_APB2ENR_SPI1EN   (UINT32_C(1) << 12)

SPI1 clock enable.

Definition at line 1649 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_SPI4EN

#define MCCI_STM32H7_REG_RCC_APB2ENR_SPI4EN   (UINT32_C(1) << 13)

SPI4 clock enable.

Definition at line 1648 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_SPI5EN

#define MCCI_STM32H7_REG_RCC_APB2ENR_SPI5EN   (UINT32_C(1) << 20)

SPI5 clock enable.

Definition at line 1642 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_TIM15EN

#define MCCI_STM32H7_REG_RCC_APB2ENR_TIM15EN   (UINT32_C(1) << 16)

TIM15 clock enable.

Definition at line 1646 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_TIM16EN

#define MCCI_STM32H7_REG_RCC_APB2ENR_TIM16EN   (UINT32_C(1) << 17)

TIM16 clock enable.

Definition at line 1645 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_TIM17EN

#define MCCI_STM32H7_REG_RCC_APB2ENR_TIM17EN   (UINT32_C(1) << 18)

TIM17 clock enable.

Definition at line 1644 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_TIM1EN

#define MCCI_STM32H7_REG_RCC_APB2ENR_TIM1EN   (UINT32_C(1) << 0)

TIM1 clock enable.

Definition at line 1657 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_TIM8EN

#define MCCI_STM32H7_REG_RCC_APB2ENR_TIM8EN   (UINT32_C(1) << 1)

TIM8 clock enable.

Definition at line 1656 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_UART9EN

#define MCCI_STM32H7_REG_RCC_APB2ENR_UART9EN   (UINT32_C(1) << 6)

UART9 clock enable.

Definition at line 1652 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_USART10EN

#define MCCI_STM32H7_REG_RCC_APB2ENR_USART10EN   (UINT32_C(1) << 7)

USART10 clock enable.

Definition at line 1651 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_USART1EN

#define MCCI_STM32H7_REG_RCC_APB2ENR_USART1EN   (UINT32_C(1) << 4)

USART1 clock enable.

Definition at line 1654 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2ENR_USART6EN

#define MCCI_STM32H7_REG_RCC_APB2ENR_USART6EN   (UINT32_C(1) << 5)

USART6 clock enable.

Definition at line 1653 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR

#define MCCI_STM32H7_REG_RCC_APB2LPENR   (MCCI_STM32H7_REG_RCC + 0x178)

APB2 sleep clock.

Definition at line 733 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_DFSDM1LPEN

#define MCCI_STM32H7_REG_RCC_APB2LPENR_DFSDM1LPEN   (UINT32_C(1) << 30)

DFSDM1 clock enable.

Definition at line 1823 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_RSV14

#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV14   (UINT32_C(3) << 14)

reserved, don't change

Definition at line 1833 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_RSV19

#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV19   (UINT32_C(1) << 19)

reserved, don't change

Definition at line 1829 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_RSV2

#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV2   (UINT32_C(3) << 2)

reserved, don't change

Definition at line 1841 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_RSV21

#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV21   (UINT32_C(1) << 21)

reserved, don't change

Definition at line 1827 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_RSV24

#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV24   (UINT32_C(0x3F) << 24)

reserved, don't change

Definition at line 1824 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_RSV31

#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV31   (UINT32_C(1) << 31)

reserved, don't change

Definition at line 1822 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_RSV8

#define MCCI_STM32H7_REG_RCC_APB2LPENR_RSV8   (UINT32_C(0xF) << 8)

reserved, don't change

Definition at line 1836 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_SAI1LPEN

#define MCCI_STM32H7_REG_RCC_APB2LPENR_SAI1LPEN   (UINT32_C(1) << 22)

SAI1 clock enable.

Definition at line 1826 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_SAI2LPEN

#define MCCI_STM32H7_REG_RCC_APB2LPENR_SAI2LPEN   (UINT32_C(1) << 23)

SAI2 clock enable.

Definition at line 1825 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_SPI1LPEN

#define MCCI_STM32H7_REG_RCC_APB2LPENR_SPI1LPEN   (UINT32_C(1) << 12)

SPI1 clock enable.

Definition at line 1835 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_SPI4LPEN

#define MCCI_STM32H7_REG_RCC_APB2LPENR_SPI4LPEN   (UINT32_C(1) << 13)

SPI4 clock enable.

Definition at line 1834 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_SPI5LPEN

#define MCCI_STM32H7_REG_RCC_APB2LPENR_SPI5LPEN   (UINT32_C(1) << 20)

SPI5 clock enable.

Definition at line 1828 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_TIM15LPEN

#define MCCI_STM32H7_REG_RCC_APB2LPENR_TIM15LPEN   (UINT32_C(1) << 16)

TIM15 clock enable.

Definition at line 1832 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_TIM16LPEN

#define MCCI_STM32H7_REG_RCC_APB2LPENR_TIM16LPEN   (UINT32_C(1) << 17)

TIM16 clock enable.

Definition at line 1831 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_TIM17LPEN

#define MCCI_STM32H7_REG_RCC_APB2LPENR_TIM17LPEN   (UINT32_C(1) << 18)

TIM17 clock enable.

Definition at line 1830 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_TIM1LPEN

#define MCCI_STM32H7_REG_RCC_APB2LPENR_TIM1LPEN   (UINT32_C(1) << 0)

TIM1 clock enable.

Definition at line 1843 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_TIM8LPEN

#define MCCI_STM32H7_REG_RCC_APB2LPENR_TIM8LPEN   (UINT32_C(1) << 1)

TIM8 clock enable.

Definition at line 1842 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_UART9LPEN

#define MCCI_STM32H7_REG_RCC_APB2LPENR_UART9LPEN   (UINT32_C(1) << 6)

UART9 clock enable.

Definition at line 1838 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_USART10LPEN

#define MCCI_STM32H7_REG_RCC_APB2LPENR_USART10LPEN   (UINT32_C(1) << 7)

USART10 clock enable.

Definition at line 1837 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_USART1LPEN

#define MCCI_STM32H7_REG_RCC_APB2LPENR_USART1LPEN   (UINT32_C(1) << 4)

USART1 clock enable.

Definition at line 1840 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2LPENR_USART6LPEN

#define MCCI_STM32H7_REG_RCC_APB2LPENR_USART6LPEN   (UINT32_C(1) << 5)

USART6 clock enable.

Definition at line 1839 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR

#define MCCI_STM32H7_REG_RCC_APB2RSTR   (MCCI_STM32H7_REG_RCC + 0x98)

APB2 peripheral reset.

Definition at line 712 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_DFSDM1RST

#define MCCI_STM32H7_REG_RCC_APB2RSTR_DFSDM1RST   (UINT32_C(1) << 30)

DFSDM1 reset.

Definition at line 1386 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_RSV14

#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV14   (UINT32_C(3) << 14)

reserved, don't change

Definition at line 1396 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_RSV19

#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV19   (UINT32_C(1) << 19)

reserved, don't change

Definition at line 1392 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_RSV2

#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV2   (UINT32_C(3) << 2)

reserved, don't change

Definition at line 1404 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_RSV21

#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV21   (UINT32_C(1) << 21)

reserved, don't change

Definition at line 1390 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_RSV24

#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV24   (UINT32_C(0x3F) << 24)

reserved, don't change

Definition at line 1387 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_RSV31

#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV31   (UINT32_C(1) << 31)

reserved, don't change

Definition at line 1385 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_RSV8

#define MCCI_STM32H7_REG_RCC_APB2RSTR_RSV8   (UINT32_C(0xF) << 8)

reserved, don't change

Definition at line 1399 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_SAI1RST

#define MCCI_STM32H7_REG_RCC_APB2RSTR_SAI1RST   (UINT32_C(1) << 22)

SAI1 reset.

Definition at line 1389 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_SAI2RST

#define MCCI_STM32H7_REG_RCC_APB2RSTR_SAI2RST   (UINT32_C(1) << 23)

SAI2 reset.

Definition at line 1388 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_SPI1RST

#define MCCI_STM32H7_REG_RCC_APB2RSTR_SPI1RST   (UINT32_C(1) << 12)

SPI1 reset.

Definition at line 1398 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_SPI4RST

#define MCCI_STM32H7_REG_RCC_APB2RSTR_SPI4RST   (UINT32_C(1) << 13)

SPI4 reset.

Definition at line 1397 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_SPI5RST

#define MCCI_STM32H7_REG_RCC_APB2RSTR_SPI5RST   (UINT32_C(1) << 20)

SPI5 reset.

Definition at line 1391 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_TIM15RST

#define MCCI_STM32H7_REG_RCC_APB2RSTR_TIM15RST   (UINT32_C(1) << 16)

TIM15 reset.

Definition at line 1395 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_TIM16RST

#define MCCI_STM32H7_REG_RCC_APB2RSTR_TIM16RST   (UINT32_C(1) << 17)

TIM16 reset.

Definition at line 1394 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_TIM17RST

#define MCCI_STM32H7_REG_RCC_APB2RSTR_TIM17RST   (UINT32_C(1) << 18)

TIM17 reset.

Definition at line 1393 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_TIM1RST

#define MCCI_STM32H7_REG_RCC_APB2RSTR_TIM1RST   (UINT32_C(1) << 0)

TIM1 reset.

Definition at line 1406 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_TIM8RST

#define MCCI_STM32H7_REG_RCC_APB2RSTR_TIM8RST   (UINT32_C(1) << 1)

TIM8 reset.

Definition at line 1405 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_UART9RST

#define MCCI_STM32H7_REG_RCC_APB2RSTR_UART9RST   (UINT32_C(1) << 6)

UART9 reset.

Definition at line 1401 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_USART10RST

#define MCCI_STM32H7_REG_RCC_APB2RSTR_USART10RST   (UINT32_C(1) << 7)

USART10 reset.

Definition at line 1400 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_USART1RST

#define MCCI_STM32H7_REG_RCC_APB2RSTR_USART1RST   (UINT32_C(1) << 4)

USART1 reset.

Definition at line 1403 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB2RSTR_USART6RST

#define MCCI_STM32H7_REG_RCC_APB2RSTR_USART6RST   (UINT32_C(1) << 5)

USART6 reset.

Definition at line 1402 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB3ENR

#define MCCI_STM32H7_REG_RCC_APB3ENR   (MCCI_STM32H7_REG_RCC + 0x144)

APB3 clock.

Definition at line 721 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB3ENR_LTDCEN

#define MCCI_STM32H7_REG_RCC_APB3ENR_LTDCEN   (UINT32_C(1) << 25)

Definition at line 1586 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB3ENR_RSV0

#define MCCI_STM32H7_REG_RCC_APB3ENR_RSV0   (UINT32_C(7) << 0)

Definition at line 1587 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB3ENR_RSV4

#define MCCI_STM32H7_REG_RCC_APB3ENR_RSV4   (UINT32_C(3) << 4)

Definition at line 1585 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB3ENR_RSV7

#define MCCI_STM32H7_REG_RCC_APB3ENR_RSV7   UINT32_C(0xFFFFFF80)

Definition at line 1583 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB3ENR_WWDGEN

#define MCCI_STM32H7_REG_RCC_APB3ENR_WWDGEN   (UINT32_C(1) << 26)

Definition at line 1584 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB3LPENR

#define MCCI_STM32H7_REG_RCC_APB3LPENR   (MCCI_STM32H7_REG_RCC + 0x16C)

APB3 sleep clock.

Definition at line 730 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB3LPENR_LTDCLPEN

#define MCCI_STM32H7_REG_RCC_APB3LPENR_LTDCLPEN   (UINT32_C(1) << 25)

Definition at line 1772 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB3LPENR_RSV0

#define MCCI_STM32H7_REG_RCC_APB3LPENR_RSV0   (UINT32_C(7) << 0)

Definition at line 1773 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB3LPENR_RSV4

#define MCCI_STM32H7_REG_RCC_APB3LPENR_RSV4   (UINT32_C(3) << 4)

Definition at line 1771 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB3LPENR_RSV7

#define MCCI_STM32H7_REG_RCC_APB3LPENR_RSV7   UINT32_C(0xFFFFFF80)

Definition at line 1769 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB3LPENR_WWDGLPEN

#define MCCI_STM32H7_REG_RCC_APB3LPENR_WWDGLPEN   (UINT32_C(1) << 26)

Definition at line 1770 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB3RSTR

#define MCCI_STM32H7_REG_RCC_APB3RSTR   (MCCI_STM32H7_REG_RCC + 0x8C)

APB3 peripheral reset.

Definition at line 709 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB3RSTR_LTDCRST

#define MCCI_STM32H7_REG_RCC_APB3RSTR_LTDCRST   (UINT32_C(1) << 3)

LTDCRST block reset.

Definition at line 1335 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB3RSTR_RSV0

#define MCCI_STM32H7_REG_RCC_APB3RSTR_RSV0   (UINT32_C(7) << 0)

reserved, don't change

Definition at line 1336 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB3RSTR_RSV4

#define MCCI_STM32H7_REG_RCC_APB3RSTR_RSV4   UINT32_C(0xFFFFFFF0)

reserved, don't change

Definition at line 1334 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR

#define MCCI_STM32H7_REG_RCC_APB4ENR   (MCCI_STM32H7_REG_RCC + 0x154)

APB4 clock.

Definition at line 725 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR_COMP12EN

#define MCCI_STM32H7_REG_RCC_APB4ENR_COMP12EN   (UINT32_C(1) << 14)

Definition at line 1668 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR_DAC2EN

#define MCCI_STM32H7_REG_RCC_APB4ENR_DAC2EN   (UINT32_C(1) << 13)

Definition at line 1669 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR_DFSDM2EN

#define MCCI_STM32H7_REG_RCC_APB4ENR_DFSDM2EN   (UINT32_C(1) << 27)

Definition at line 1663 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR_DTSEN

#define MCCI_STM32H7_REG_RCC_APB4ENR_DTSEN   (UINT32_C(1) << 26)

Definition at line 1664 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR_I2C4EN

#define MCCI_STM32H7_REG_RCC_APB4ENR_I2C4EN   (UINT32_C(1) << 7)

Definition at line 1674 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR_LPTIM2EN

#define MCCI_STM32H7_REG_RCC_APB4ENR_LPTIM2EN   (UINT32_C(1) << 9)

Definition at line 1672 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR_LPTIM3EN

#define MCCI_STM32H7_REG_RCC_APB4ENR_LPTIM3EN   (UINT32_C(1) << 10)

Definition at line 1671 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR_LPUART1EN

#define MCCI_STM32H7_REG_RCC_APB4ENR_LPUART1EN   (UINT32_C(1) << 3)

Definition at line 1678 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR_RSV0

#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV0   (UINT32_C(1) << 0)

Definition at line 1681 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR_RSV11

#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV11   (UINT32_C(3) << 11)

Definition at line 1670 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR_RSV17

#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV17   (UINT32_C(0x1FF) << 17)

Definition at line 1665 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR_RSV2

#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV2   (UINT32_C(1) << 2)

Definition at line 1679 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR_RSV28

#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV28   (UINT32_C(0xF) << 28)

Definition at line 1662 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR_RSV4

#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV4   (UINT32_C(1) << 4)

Definition at line 1677 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR_RSV6

#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV6   (UINT32_C(1) << 6)

Definition at line 1675 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR_RSV8

#define MCCI_STM32H7_REG_RCC_APB4ENR_RSV8   (UINT32_C(1) << 8)

Definition at line 1673 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR_RTCAPBEN

#define MCCI_STM32H7_REG_RCC_APB4ENR_RTCAPBEN   (UINT32_C(1) << 16)

Definition at line 1666 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR_SPI6EN

#define MCCI_STM32H7_REG_RCC_APB4ENR_SPI6EN   (UINT32_C(1) << 5)

Definition at line 1676 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR_SYSCFGEN

#define MCCI_STM32H7_REG_RCC_APB4ENR_SYSCFGEN   (UINT32_C(1) << 1)

Definition at line 1680 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4ENR_VREFEN

#define MCCI_STM32H7_REG_RCC_APB4ENR_VREFEN   (UINT32_C(1) << 15)

Definition at line 1667 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR

#define MCCI_STM32H7_REG_RCC_APB4LPENR   (MCCI_STM32H7_REG_RCC + 0x17C)

APB4 sleep clock.

Definition at line 734 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR_COMP12LPEN

#define MCCI_STM32H7_REG_RCC_APB4LPENR_COMP12LPEN   (UINT32_C(1) << 14)

Definition at line 1854 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR_DAC2LPEN

#define MCCI_STM32H7_REG_RCC_APB4LPENR_DAC2LPEN   (UINT32_C(1) << 13)

Definition at line 1855 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR_DFSDM2LPEN

#define MCCI_STM32H7_REG_RCC_APB4LPENR_DFSDM2LPEN   (UINT32_C(1) << 27)

Definition at line 1849 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR_DTSLPEN

#define MCCI_STM32H7_REG_RCC_APB4LPENR_DTSLPEN   (UINT32_C(1) << 26)

Definition at line 1850 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR_I2C4LPEN

#define MCCI_STM32H7_REG_RCC_APB4LPENR_I2C4LPEN   (UINT32_C(1) << 7)

Definition at line 1860 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR_LPTIM2LPEN

#define MCCI_STM32H7_REG_RCC_APB4LPENR_LPTIM2LPEN   (UINT32_C(1) << 9)

Definition at line 1858 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR_LPTIM3LPEN

#define MCCI_STM32H7_REG_RCC_APB4LPENR_LPTIM3LPEN   (UINT32_C(1) << 10)

Definition at line 1857 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR_LPUART1LPEN

#define MCCI_STM32H7_REG_RCC_APB4LPENR_LPUART1LPEN   (UINT32_C(1) << 3)

Definition at line 1864 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR_RSV0

#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV0   (UINT32_C(1) << 0)

Definition at line 1867 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR_RSV11

#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV11   (UINT32_C(3) << 11)

Definition at line 1856 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR_RSV17

#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV17   (UINT32_C(0x1FF) << 17)

Definition at line 1851 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR_RSV2

#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV2   (UINT32_C(1) << 2)

Definition at line 1865 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR_RSV28

#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV28   (UINT32_C(0xF) << 28)

Definition at line 1848 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR_RSV4

#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV4   (UINT32_C(1) << 4)

Definition at line 1863 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR_RSV6

#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV6   (UINT32_C(1) << 6)

Definition at line 1861 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR_RSV8

#define MCCI_STM32H7_REG_RCC_APB4LPENR_RSV8   (UINT32_C(1) << 8)

Definition at line 1859 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR_RTCAPBLPEN

#define MCCI_STM32H7_REG_RCC_APB4LPENR_RTCAPBLPEN   (UINT32_C(1) << 16)

Definition at line 1852 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR_SPI6LPEN

#define MCCI_STM32H7_REG_RCC_APB4LPENR_SPI6LPEN   (UINT32_C(1) << 5)

Definition at line 1862 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR_SYSCFGLPEN

#define MCCI_STM32H7_REG_RCC_APB4LPENR_SYSCFGLPEN   (UINT32_C(1) << 1)

Definition at line 1866 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4LPENR_VREFLPEN

#define MCCI_STM32H7_REG_RCC_APB4LPENR_VREFLPEN   (UINT32_C(1) << 15)

Definition at line 1853 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4RSTR

#define MCCI_STM32H7_REG_RCC_APB4RSTR   (MCCI_STM32H7_REG_RCC + 0x9C)

APB4 peripheral reset.

Definition at line 713 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4RSTR_COMP12RST

#define MCCI_STM32H7_REG_RCC_APB4RSTR_COMP12RST   (UINT32_C(1) << 14)

Definition at line 1416 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4RSTR_DAC2RST

#define MCCI_STM32H7_REG_RCC_APB4RSTR_DAC2RST   (UINT32_C(1) << 13)

Definition at line 1417 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4RSTR_DFSDM2RST

#define MCCI_STM32H7_REG_RCC_APB4RSTR_DFSDM2RST   (UINT32_C(1) << 27)

Definition at line 1412 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4RSTR_DTSRST

#define MCCI_STM32H7_REG_RCC_APB4RSTR_DTSRST   (UINT32_C(1) << 26)

Definition at line 1413 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4RSTR_I2C4RST

#define MCCI_STM32H7_REG_RCC_APB4RSTR_I2C4RST   (UINT32_C(1) << 7)

Definition at line 1422 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4RSTR_LPTIM2RST

#define MCCI_STM32H7_REG_RCC_APB4RSTR_LPTIM2RST   (UINT32_C(1) << 9)

Definition at line 1420 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4RSTR_LPTIM3RST

#define MCCI_STM32H7_REG_RCC_APB4RSTR_LPTIM3RST   (UINT32_C(1) << 10)

Definition at line 1419 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4RSTR_LPUART1RST

#define MCCI_STM32H7_REG_RCC_APB4RSTR_LPUART1RST   (UINT32_C(1) << 3)

Definition at line 1426 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4RSTR_RSV0

#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV0   (UINT32_C(1) << 0)

Definition at line 1429 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4RSTR_RSV11

#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV11   (UINT32_C(3) << 11)

Definition at line 1418 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4RSTR_RSV16

#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV16   (UINT32_C(0x3FF) << 16)

Definition at line 1414 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4RSTR_RSV2

#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV2   (UINT32_C(1) << 2)

Definition at line 1427 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4RSTR_RSV28

#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV28   (UINT32_C(0xF) << 28)

Definition at line 1411 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4RSTR_RSV4

#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV4   (UINT32_C(1) << 4)

Definition at line 1425 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4RSTR_RSV6

#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV6   (UINT32_C(1) << 6)

Definition at line 1423 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4RSTR_RSV8

#define MCCI_STM32H7_REG_RCC_APB4RSTR_RSV8   (UINT32_C(1) << 8)

Definition at line 1421 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4RSTR_SPI6RST

#define MCCI_STM32H7_REG_RCC_APB4RSTR_SPI6RST   (UINT32_C(1) << 5)

Definition at line 1424 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4RSTR_SYSCFGRST

#define MCCI_STM32H7_REG_RCC_APB4RSTR_SYSCFGRST   (UINT32_C(1) << 1)

Definition at line 1428 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_APB4RSTR_VREFRST

#define MCCI_STM32H7_REG_RCC_APB4RSTR_VREFRST   (UINT32_C(1) << 15)

Definition at line 1415 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR

#define MCCI_STM32H7_REG_RCC_BDCR   (MCCI_STM32H7_REG_RCC + 0x70)

Backup domain control.

Definition at line 703 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR_LSEBYP

#define MCCI_STM32H7_REG_RCC_BDCR_LSEBYP   (UINT32_C(1) << 2)

Definition at line 1250 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR_LSECSSD

#define MCCI_STM32H7_REG_RCC_BDCR_LSECSSD   (UINT32_C(1) << 6)

Definition at line 1243 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR_LSECSSON

#define MCCI_STM32H7_REG_RCC_BDCR_LSECSSON   (UINT32_C(1) << 5)

Definition at line 1244 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR_LSEDRV

#define MCCI_STM32H7_REG_RCC_BDCR_LSEDRV   (UINT32_C(3) << 3)

Definition at line 1245 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR_LSEDRV_HIEST

#define MCCI_STM32H7_REG_RCC_BDCR_LSEDRV_HIEST   (UINT32_C(3) << 3)

Definition at line 1249 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR_LSEDRV_LOWEST

#define MCCI_STM32H7_REG_RCC_BDCR_LSEDRV_LOWEST   (UINT32_C(0) << 3)

Definition at line 1246 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR_LSEDRV_MEDHI

#define MCCI_STM32H7_REG_RCC_BDCR_LSEDRV_MEDHI   (UINT32_C(2) << 3)

Definition at line 1248 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR_LSEDRV_MEDLOW

#define MCCI_STM32H7_REG_RCC_BDCR_LSEDRV_MEDLOW   (UINT32_C(1) << 3)

Definition at line 1247 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR_LSEEXT

#define MCCI_STM32H7_REG_RCC_BDCR_LSEEXT   (UINT32_C(1) << 7)

Definition at line 1242 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR_LSEON

#define MCCI_STM32H7_REG_RCC_BDCR_LSEON   (UINT32_C(1) << 0)

Definition at line 1252 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR_LSERDY

#define MCCI_STM32H7_REG_RCC_BDCR_LSERDY   (UINT32_C(1) << 1)

Definition at line 1251 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR_RSV10

#define MCCI_STM32H7_REG_RCC_BDCR_RSV10   (UINT32_C(0x1F) << 10)

Definition at line 1236 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR_RSV17

#define MCCI_STM32H7_REG_RCC_BDCR_RSV17   UINT32_C(0xFFFE0000)

Definition at line 1233 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR_RTCEN

#define MCCI_STM32H7_REG_RCC_BDCR_RTCEN   (UINT32_C(1) << 15)

Definition at line 1235 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR_RTCSEL

#define MCCI_STM32H7_REG_RCC_BDCR_RTCSEL   (UINT32_C(3) << 8)

Definition at line 1237 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR_RTCSEL_HSE

#define MCCI_STM32H7_REG_RCC_BDCR_RTCSEL_HSE   (UINT32_C(3) << 8)

Definition at line 1241 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR_RTCSEL_LSE

#define MCCI_STM32H7_REG_RCC_BDCR_RTCSEL_LSE   (UINT32_C(1) << 8)

Definition at line 1239 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR_RTCSEL_LSI

#define MCCI_STM32H7_REG_RCC_BDCR_RTCSEL_LSI   (UINT32_C(2) << 8)

Definition at line 1240 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR_RTCSEL_NO

#define MCCI_STM32H7_REG_RCC_BDCR_RTCSEL_NO   (UINT32_C(0) << 8)

Definition at line 1238 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_BDCR_VSWRST

#define MCCI_STM32H7_REG_RCC_BDCR_VSWRST   (UINT32_C(1) << 16)

Definition at line 1234 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R

#define MCCI_STM32H7_REG_RCC_CDCCIP1R   (MCCI_STM32H7_REG_RCC + 0x50)

CPU domain kernel clock configuration.

Definition at line 697 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_DFSDM1SEL

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_DFSDM1SEL   (UINT32_C(1) << 24)

Definition at line 1044 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_FDCANSEL

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_FDCANSEL   (UINT32_C(3) << 28)

Definition at line 1039 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_FDCANSEL_HSE

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_FDCANSEL_HSE   (UINT32_C(0) << 28)

Definition at line 1040 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_FDCANSEL_PLL1

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_FDCANSEL_PLL1   (UINT32_C(1) << 28)

Definition at line 1041 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_FDCANSEL_PLL2

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_FDCANSEL_PLL2   (UINT32_C(2) << 28)

Definition at line 1042 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV15

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV15   (UINT32_C(1) << 15)

Definition at line 1059 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV19

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV19   (UINT32_C(1) << 19)

Definition at line 1051 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV22

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV22   (UINT32_C(3) << 22)

Definition at line 1045 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV25

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV25   (UINT32_C(7) << 25)

Definition at line 1043 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV3

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV3   (UINT32_C(7) << 3)

Definition at line 1080 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV30

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_RSV30   (UINT32_C(1) << 30)

Definition at line 1038 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL   (UINT32_C(7) << 0)

Definition at line 1081 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL_I2S

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL_I2S   (UINT32_C(3) << 0)

Definition at line 1085 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL_PER

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL_PER   (UINT32_C(4) << 0)

Definition at line 1086 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL_PLL1

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL_PLL1   (UINT32_C(0) << 0)

Definition at line 1082 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL_PLL2

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL_PLL2   (UINT32_C(1) << 0)

Definition at line 1083 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL_PLL3

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI1SEL_PLL3   (UINT32_C(2) << 0)

Definition at line 1084 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL   (UINT32_C(7) << 6)

Definition at line 1073 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_I2S

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_I2S   (UINT32_C(3) << 6)

Definition at line 1077 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_PER

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_PER   (UINT32_C(4) << 6)

Definition at line 1078 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_PLL1

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_PLL1   (UINT32_C(0) << 6)

Definition at line 1074 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_PLL2

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_PLL2   (UINT32_C(1) << 6)

Definition at line 1075 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_PLL3

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_PLL3   (UINT32_C(2) << 6)

Definition at line 1076 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_SPDIFRX

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2ASEL_SPDIFRX   (UINT32_C(5) << 6)

Definition at line 1079 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL   (UINT32_C(7) << 9)

Definition at line 1066 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_I2S

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_I2S   (UINT32_C(3) << 9)

Definition at line 1070 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_PER

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_PER   (UINT32_C(4) << 9)

Definition at line 1071 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_PLL1

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_PLL1   (UINT32_C(0) << 9)

Definition at line 1067 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_PLL2

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_PLL2   (UINT32_C(1) << 9)

Definition at line 1068 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_PLL3

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_PLL3   (UINT32_C(2) << 9)

Definition at line 1069 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_SPDIFRX

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SAI2BSEL_SPDIFRX   (UINT32_C(5) << 9)

Definition at line 1072 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SPDIFRXSEL

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPDIFRXSEL   (UINT32_C(3) << 20)

Definition at line 1046 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SPDIFRXSEL_HSI

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPDIFRXSEL_HSI   (UINT32_C(3) << 20)

Definition at line 1050 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SPDIFRXSEL_PLL1

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPDIFRXSEL_PLL1   (UINT32_C(0) << 20)

Definition at line 1047 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SPDIFRXSEL_PLL2

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPDIFRXSEL_PLL2   (UINT32_C(1) << 20)

Definition at line 1048 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SPDIFRXSEL_PLL3

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPDIFRXSEL_PLL3   (UINT32_C(2) << 20)

Definition at line 1049 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL   (UINT32_C(7) << 12)

Definition at line 1060 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL_I2S

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL_I2S   (UINT32_C(3) << 12)

Definition at line 1064 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL_PER

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL_PER   (UINT32_C(4) << 12)

Definition at line 1065 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL_PLL1

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL_PLL1   (UINT32_C(0) << 12)

Definition at line 1061 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL_PLL2

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL_PLL2   (UINT32_C(1) << 12)

Definition at line 1062 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL_PLL3

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI123SEL_PLL3   (UINT32_C(2) << 12)

Definition at line 1063 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL   (UINT32_C(7) << 16)

Definition at line 1052 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_CSI

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_CSI   (UINT32_C(4) << 16)

Definition at line 1057 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_HSE

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_HSE   (UINT32_C(5) << 16)

Definition at line 1058 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_HSI

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_HSI   (UINT32_C(3) << 16)

Definition at line 1056 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_PCLK2

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_PCLK2   (UINT32_C(0) << 16)

Definition at line 1053 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_PLL2

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_PLL2   (UINT32_C(1) << 16)

Definition at line 1054 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_PLL3

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SPI45SEL_PLL3   (UINT32_C(2) << 16)

Definition at line 1055 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP1R_SWPMISEL

#define MCCI_STM32H7_REG_RCC_CDCCIP1R_SWPMISEL   (UINT32_C(1) << 31)

Definition at line 1037 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R

#define MCCI_STM32H7_REG_RCC_CDCCIP2R   (MCCI_STM32H7_REG_RCC + 0x54)

CPU domain kernel clock configuration.

Definition at line 698 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_CECSEL

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_CECSEL   (UINT32_C(3) << 22)

Definition at line 1100 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_CECSEL_CSI

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_CECSEL_CSI   (UINT32_C(2) << 22)

Definition at line 1103 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_CECSEL_LSE

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_CECSEL_LSE   (UINT32_C(0) << 22)

Definition at line 1101 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_CECSEL_LSI

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_CECSEL_LSI   (UINT32_C(1) << 22)

Definition at line 1102 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_I2C123SEL

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_I2C123SEL   (UINT32_C(7) << 12)

Definition at line 1110 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_I2C123SEL_CSI

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_I2C123SEL_CSI   (UINT32_C(3) << 12)

Definition at line 1114 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_I2C123SEL_HSI

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_I2C123SEL_HSI   (UINT32_C(2) << 12)

Definition at line 1113 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_I2C123SEL_PCLK1

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_I2C123SEL_PCLK1   (UINT32_C(0) << 12)

Definition at line 1111 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_I2C123SEL_PLL3

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_I2C123SEL_PLL3   (UINT32_C(1) << 12)

Definition at line 1112 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL   (UINT32_C(7) << 28)

Definition at line 1092 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_LSE

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_LSE   (UINT32_C(3) << 28)

Definition at line 1096 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_LSI

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_LSI   (UINT32_C(4) << 28)

Definition at line 1097 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_PCLK1

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_PCLK1   (UINT32_C(0) << 28)

Definition at line 1093 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_PER

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_PER   (UINT32_C(5) << 28)

Definition at line 1098 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_PLL2

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_PLL2   (UINT32_C(1) << 28)

Definition at line 1094 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_PLL3

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_LPTIM1SEL_PLL3   (UINT32_C(2) << 28)

Definition at line 1095 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_RNGSEL

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RNGSEL   (UINT32_C(3) << 8)

Definition at line 1116 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_RNGSEL_HSI48

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RNGSEL_HSI48   (UINT32_C(0) << 8)

Definition at line 1117 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_RNGSEL_LSE

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RNGSEL_LSE   (UINT32_C(2) << 8)

Definition at line 1119 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_RNGSEL_LSI

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RNGSEL_LSI   (UINT32_C(3) << 8)

Definition at line 1120 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_RNGSEL_PLL1

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RNGSEL_PLL1   (UINT32_C(1) << 8)

Definition at line 1118 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_RSV10

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RSV10   (UINT32_C(3) << 10)

Definition at line 1115 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_RSV14

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RSV14   (UINT32_C(0x3F) << 14)

Definition at line 1109 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_RSV24

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RSV24   (UINT32_C(0xF) << 24)

Definition at line 1099 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_RSV31

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RSV31   (UINT32_C(1) << 31)

Definition at line 1091 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_RSV6

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_RSV6   (UINT32_C(3) << 6)

Definition at line 1121 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL   (UINT32_C(7) << 3)

Definition at line 1122 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_CSI

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_CSI   (UINT32_C(4) << 3)

Definition at line 1127 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_HSI

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_HSI   (UINT32_C(3) << 3)

Definition at line 1126 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_LSE

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_LSE   (UINT32_C(5) << 3)

Definition at line 1128 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_PCLK2

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_PCLK2   (UINT32_C(0) << 3)

Definition at line 1123 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_PLL2

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_PLL2   (UINT32_C(1) << 3)

Definition at line 1124 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_PLL3

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART16910SEL_PLL3   (UINT32_C(2) << 3)

Definition at line 1125 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL   (UINT32_C(7) << 0)

Definition at line 1129 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_CSI

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_CSI   (UINT32_C(4) << 0)

Definition at line 1134 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_HSI

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_HSI   (UINT32_C(3) << 0)

Definition at line 1133 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_LSE

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_LSE   (UINT32_C(5) << 0)

Definition at line 1135 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_PCLK1

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_PCLK1   (UINT32_C(0) << 0)

Definition at line 1130 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_PLL2

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_PLL2   (UINT32_C(1) << 0)

Definition at line 1131 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_PLL3

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USART234578SEL_PLL3   (UINT32_C(2) << 0)

Definition at line 1132 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_USBSEL

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USBSEL   (UINT32_C(3) << 20)

Definition at line 1104 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_USBSEL_DIS

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USBSEL_DIS   (UINT32_C(0) << 20)

Definition at line 1105 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_USBSEL_HSI48

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USBSEL_HSI48   (UINT32_C(3) << 20)

Definition at line 1108 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_USBSEL_PLL1

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USBSEL_PLL1   (UINT32_C(1) << 20)

Definition at line 1106 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIP2R_USBSEL_PLL3

#define MCCI_STM32H7_REG_RCC_CDCCIP2R_USBSEL_PLL3   (UINT32_C(2) << 20)

Definition at line 1107 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIPR

#define MCCI_STM32H7_REG_RCC_CDCCIPR   (MCCI_STM32H7_REG_RCC + 0x4C)

CPU domain kernel clock configuration.

Definition at line 696 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIPR_CKPERSEL

#define MCCI_STM32H7_REG_RCC_CDCCIPR_CKPERSEL   (UINT32_C(3) << 28)

Definition at line 1015 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIPR_CKPERSEL_CSI

#define MCCI_STM32H7_REG_RCC_CDCCIPR_CKPERSEL_CSI   (UINT32_C(1) << 28)

Definition at line 1017 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIPR_CKPERSEL_HSE

#define MCCI_STM32H7_REG_RCC_CDCCIPR_CKPERSEL_HSE   (UINT32_C(2) << 28)

Definition at line 1018 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIPR_CKPERSEL_HSI

#define MCCI_STM32H7_REG_RCC_CDCCIPR_CKPERSEL_HSI   (UINT32_C(0) << 28)

Definition at line 1016 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIPR_FMCSEL

#define MCCI_STM32H7_REG_RCC_CDCCIPR_FMCSEL   (UINT32_C(3) << 0)

Definition at line 1028 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIPR_FMCSEL_HCLK3

#define MCCI_STM32H7_REG_RCC_CDCCIPR_FMCSEL_HCLK3   (UINT32_C(0) << 0)

Definition at line 1029 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIPR_FMCSEL_PER

#define MCCI_STM32H7_REG_RCC_CDCCIPR_FMCSEL_PER   (UINT32_C(3) << 0)

Definition at line 1032 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIPR_FMCSEL_PLL1

#define MCCI_STM32H7_REG_RCC_CDCCIPR_FMCSEL_PLL1   (UINT32_C(1) << 0)

Definition at line 1030 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIPR_FMCSEL_PLL2

#define MCCI_STM32H7_REG_RCC_CDCCIPR_FMCSEL_PLL2   (UINT32_C(2) << 0)

Definition at line 1031 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIPR_OCTOSPISEL

#define MCCI_STM32H7_REG_RCC_CDCCIPR_OCTOSPISEL   (UINT32_C(3) << 4)

Definition at line 1022 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIPR_OCTOSPISEL_HCLK3

#define MCCI_STM32H7_REG_RCC_CDCCIPR_OCTOSPISEL_HCLK3   (UINT32_C(0) << 4)

Definition at line 1023 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIPR_OCTOSPISEL_PER

#define MCCI_STM32H7_REG_RCC_CDCCIPR_OCTOSPISEL_PER   (UINT32_C(3) << 4)

Definition at line 1026 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIPR_OCTOSPISEL_PLL1

#define MCCI_STM32H7_REG_RCC_CDCCIPR_OCTOSPISEL_PLL1   (UINT32_C(1) << 4)

Definition at line 1024 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIPR_OCTOSPISEL_PLL2

#define MCCI_STM32H7_REG_RCC_CDCCIPR_OCTOSPISEL_PLL2   (UINT32_C(2) << 4)

Definition at line 1025 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIPR_RSV0

#define MCCI_STM32H7_REG_RCC_CDCCIPR_RSV0   (UINT32_C(3) << 2)

Definition at line 1027 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIPR_RSV17

#define MCCI_STM32H7_REG_RCC_CDCCIPR_RSV17   UINT32_C(0x0FFE0000)

Definition at line 1019 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIPR_RSV30

#define MCCI_STM32H7_REG_RCC_CDCCIPR_RSV30   (UINT32_C(3) << 30)

Definition at line 1014 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIPR_RSV6

#define MCCI_STM32H7_REG_RCC_CDCCIPR_RSV6   (UINT32_C(0x3F) << 6)

Definition at line 1021 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCCIPR_SDMMCSEL

#define MCCI_STM32H7_REG_RCC_CDCCIPR_SDMMCSEL   (UINT32_C(1) << 16)

Definition at line 1020 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1

#define MCCI_STM32H7_REG_RCC_CDCFGR1   (MCCI_STM32H7_REG_RCC + 0x14)

CPU domain clock configuration.

Definition at line 685 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE

#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE   (UINT32_C(0xF) << 8)

Definition at line 838 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_1

#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_1   (UINT32_C(0) << 8)

Definition at line 839 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_128

#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_128   (UINT32_C(0xD) << 8)

Definition at line 845 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_16

#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_16   (UINT32_C(0xB) << 8)

Definition at line 843 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_2

#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_2   (UINT32_C(0x8) << 8)

Definition at line 840 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_256

#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_256   (UINT32_C(0xE) << 8)

Definition at line 846 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_4

#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_4   (UINT32_C(0x9) << 8)

Definition at line 841 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_5

#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_5   (UINT32_C(0xA) << 8)

Definition at line 842 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_512

#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_512   (UINT32_C(0xF) << 8)

Definition at line 847 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_64

#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDCPRE_64   (UINT32_C(0xC) << 8)

Definition at line 844 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE

#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE   (UINT32_C(7) << 4)

Definition at line 849 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE_1

#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE_1   (UINT32_C(0) << 4)

Definition at line 850 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE_16

#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE_16   (UINT32_C(7) << 4)

Definition at line 854 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE_2

#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE_2   (UINT32_C(4) << 4)

Definition at line 851 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE_3

#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE_3   (UINT32_C(5) << 4)

Definition at line 852 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE_8

#define MCCI_STM32H7_REG_RCC_CDCFGR1_CDPPRE_8   (UINT32_C(6) << 4)

Definition at line 853 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE

#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE   (UINT32_C(0xF) << 0)

Definition at line 855 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_1

#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_1   (UINT32_C(0) << 0)

Definition at line 856 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_128

#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_128   (UINT32_C(0xD) << 0)

Definition at line 862 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_16

#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_16   (UINT32_C(0xB) << 0)

Definition at line 860 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_2

#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_2   (UINT32_C(0x8) << 0)

Definition at line 857 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_256

#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_256   (UINT32_C(0xE) << 0)

Definition at line 863 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_4

#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_4   (UINT32_C(0x9) << 0)

Definition at line 858 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_512

#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_512   (UINT32_C(0xF) << 0)

Definition at line 864 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_64

#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_64   (UINT32_C(0xC) << 0)

Definition at line 861 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_8

#define MCCI_STM32H7_REG_RCC_CDCFGR1_HPRE_8   (UINT32_C(0xA) << 0)

Definition at line 859 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_RSV12

#define MCCI_STM32H7_REG_RCC_CDCFGR1_RSV12   UINT32_C(0xFFFFF000)

Definition at line 837 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR1_RSV7

#define MCCI_STM32H7_REG_RCC_CDCFGR1_RSV7   (UINT32_C(1) << 7)

Definition at line 848 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR2

#define MCCI_STM32H7_REG_RCC_CDCFGR2   (MCCI_STM32H7_REG_RCC + 0x18)

CPU domain clock configuration.

Definition at line 686 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1

#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1   (UINT32_C(7) << 4)

Definition at line 877 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1_1

#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1_1   (UINT32_C(0) << 4)

Definition at line 878 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1_16

#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1_16   (UINT32_C(7) << 4)

Definition at line 882 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1_2

#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1_2   (UINT32_C(4) << 4)

Definition at line 879 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1_3

#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1_3   (UINT32_C(5) << 4)

Definition at line 880 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1_8

#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE1_8   (UINT32_C(6) << 4)

Definition at line 881 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2

#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2   (UINT32_C(7) << 8)

Definition at line 870 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2_1

#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2_1   (UINT32_C(0) << 8)

Definition at line 871 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2_16

#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2_16   (UINT32_C(7) << 8)

Definition at line 875 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2_2

#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2_2   (UINT32_C(4) << 8)

Definition at line 872 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2_3

#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2_3   (UINT32_C(5) << 8)

Definition at line 873 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2_8

#define MCCI_STM32H7_REG_RCC_CDCFGR2_CDPPRE2_8   (UINT32_C(6) << 8)

Definition at line 874 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR2_RSV0

#define MCCI_STM32H7_REG_RCC_CDCFGR2_RSV0   (UINT32_C(0xF) << 0)

Definition at line 883 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR2_RSV11

#define MCCI_STM32H7_REG_RCC_CDCFGR2_RSV11   UINT32_C(0xFFFFF800)

Definition at line 869 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CDCFGR2_RSV7

#define MCCI_STM32H7_REG_RCC_CDCFGR2_RSV7   (UINT32_C(1) << 7)

Definition at line 876 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR

#define MCCI_STM32H7_REG_RCC_CFGR   (MCCI_STM32H7_REG_RCC + 0x10)

Clock configuration.

Definition at line 684 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_MCO1PRE

#define MCCI_STM32H7_REG_RCC_CFGR_MCO1PRE   (UINT32_C(0xF) << 18)

Definition at line 812 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_MCO1PRE_DIS

#define MCCI_STM32H7_REG_RCC_CFGR_MCO1PRE_DIS   (UINT32_C(0) << 18)

Definition at line 813 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_MCO1PRE_N

#define MCCI_STM32H7_REG_RCC_CFGR_MCO1PRE_N (   n)    ((n) << 18)

Definition at line 814 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL

#define MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL   (UINT32_C(7) << 22)

Definition at line 806 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL_HSE

#define MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL_HSE   (UINT32_C(2) << 22)

Definition at line 809 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL_HSI

#define MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL_HSI   (UINT32_C(0) << 22)

Definition at line 807 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL_HSI48

#define MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL_HSI48   (UINT32_C(4) << 22)

Definition at line 811 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL_LSE

#define MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL_LSE   (UINT32_C(1) << 22)

Definition at line 808 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL_PLL1

#define MCCI_STM32H7_REG_RCC_CFGR_MCO1SEL_PLL1   (UINT32_C(3) << 22)

Definition at line 810 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_MCO2PRE

#define MCCI_STM32H7_REG_RCC_CFGR_MCO2PRE   (UINT32_C(0xF) << 25)

Definition at line 803 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_MCO2PRE_DIS

#define MCCI_STM32H7_REG_RCC_CFGR_MCO2PRE_DIS   (UINT32_C(0) << 25)

Definition at line 804 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_MCO2PRE_N

#define MCCI_STM32H7_REG_RCC_CFGR_MCO2PRE_N (   n)    ((n) << 25)

Definition at line 805 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL

#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL   (UINT32_C(7) << 29)

Definition at line 796 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_CSI

#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_CSI   (UINT32_C(4) << 29)

Definition at line 801 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_HSE

#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_HSE   (UINT32_C(2) << 29)

Definition at line 799 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_LSI

#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_LSI   (UINT32_C(5) << 29)

Definition at line 802 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_PLL1

#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_PLL1   (UINT32_C(3) << 29)

Definition at line 800 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_PLL2

#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_PLL2   (UINT32_C(1) << 29)

Definition at line 798 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_SYS

#define MCCI_STM32H7_REG_RCC_CFGR_MCO2SEL_SYS   (UINT32_C(0) << 29)

Definition at line 797 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_RSV14

#define MCCI_STM32H7_REG_RCC_CFGR_RSV14   (UINT32_C(1) << 14)

Definition at line 817 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_RSV16

#define MCCI_STM32H7_REG_RCC_CFGR_RSV16   (UINT32_C(3) << 16)

Definition at line 815 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_RTCPRE

#define MCCI_STM32H7_REG_RCC_CFGR_RTCPRE   (UINT32_C(0x3F) << 8)

Definition at line 818 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_RTCPRE_DIS

#define MCCI_STM32H7_REG_RCC_CFGR_RTCPRE_DIS   (UINT32_C(0) << 8)

Definition at line 819 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_RTCPRE_N

#define MCCI_STM32H7_REG_RCC_CFGR_RTCPRE_N (   n)    ((n) << 8)

Definition at line 820 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_STOPKERWUCK

#define MCCI_STM32H7_REG_RCC_CFGR_STOPKERWUCK   (UINT32_C(1) << 7)

Definition at line 821 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_STOPWUCK

#define MCCI_STM32H7_REG_RCC_CFGR_STOPWUCK   (UINT32_C(1) << 6)

Definition at line 822 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_SW

#define MCCI_STM32H7_REG_RCC_CFGR_SW   (UINT32_C(3) << 0)

Definition at line 828 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_SW_CSI

#define MCCI_STM32H7_REG_RCC_CFGR_SW_CSI   (UINT32_C(1) << 0)

Definition at line 830 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_SW_HSE

#define MCCI_STM32H7_REG_RCC_CFGR_SW_HSE   (UINT32_C(2) << 0)

Definition at line 831 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_SW_HSI

#define MCCI_STM32H7_REG_RCC_CFGR_SW_HSI   (UINT32_C(0) << 0)

Definition at line 829 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_SW_PLL1

#define MCCI_STM32H7_REG_RCC_CFGR_SW_PLL1   (UINT32_C(3) << 0)

Definition at line 832 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_SWS

#define MCCI_STM32H7_REG_RCC_CFGR_SWS   (UINT32_C(7) << 3)

Definition at line 823 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_SWS_CSI

#define MCCI_STM32H7_REG_RCC_CFGR_SWS_CSI   (UINT32_C(1) << 3)

Definition at line 825 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_SWS_HSE

#define MCCI_STM32H7_REG_RCC_CFGR_SWS_HSE   (UINT32_C(2) << 3)

Definition at line 826 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_SWS_HSI

#define MCCI_STM32H7_REG_RCC_CFGR_SWS_HSI   (UINT32_C(0) << 3)

Definition at line 824 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_SWS_PLL1

#define MCCI_STM32H7_REG_RCC_CFGR_SWS_PLL1   (UINT32_C(3) << 3)

Definition at line 827 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CFGR_TIMPRE

#define MCCI_STM32H7_REG_RCC_CFGR_TIMPRE   (UINT32_C(1) << 15)

Definition at line 816 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CICR

#define MCCI_STM32H7_REG_RCC_CICR   (MCCI_STM32H7_REG_RCC + 0x68)

clock source interrupt clear

Definition at line 702 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CICR_CSIRDYC

#define MCCI_STM32H7_REG_RCC_CICR_CSIRDYC   (UINT32_C(1) << 4)

Definition at line 1224 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CICR_HSECSSC

#define MCCI_STM32H7_REG_RCC_CICR_HSECSSC   (UINT32_C(1) << 10)

Definition at line 1218 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CICR_HSERDYC

#define MCCI_STM32H7_REG_RCC_CICR_HSERDYC   (UINT32_C(1) << 3)

Definition at line 1225 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CICR_HSI48RDYC

#define MCCI_STM32H7_REG_RCC_CICR_HSI48RDYC   (UINT32_C(1) << 5)

Definition at line 1223 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CICR_HSIRDYC

#define MCCI_STM32H7_REG_RCC_CICR_HSIRDYC   (UINT32_C(1) << 2)

Definition at line 1226 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CICR_LSECSSC

#define MCCI_STM32H7_REG_RCC_CICR_LSECSSC   (UINT32_C(1) << 9)

Definition at line 1219 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CICR_LSERDYC

#define MCCI_STM32H7_REG_RCC_CICR_LSERDYC   (UINT32_C(1) << 1)

Definition at line 1227 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CICR_LSIRDYC

#define MCCI_STM32H7_REG_RCC_CICR_LSIRDYC   (UINT32_C(1) << 0)

Definition at line 1228 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CICR_PLL1RDYC

#define MCCI_STM32H7_REG_RCC_CICR_PLL1RDYC   (UINT32_C(1) << 6)

Definition at line 1222 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CICR_PLL2RDYC

#define MCCI_STM32H7_REG_RCC_CICR_PLL2RDYC   (UINT32_C(1) << 7)

Definition at line 1221 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CICR_PLL3RDYC

#define MCCI_STM32H7_REG_RCC_CICR_PLL3RDYC   (UINT32_C(1) << 8)

Definition at line 1220 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CICR_RSV11

#define MCCI_STM32H7_REG_RCC_CICR_RSV11   UINT32_C(0xFFFFF800)

Definition at line 1217 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIER

#define MCCI_STM32H7_REG_RCC_CIER   (MCCI_STM32H7_REG_RCC + 0x60)

clock source interrupt enable

Definition at line 700 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIER_CSIRDYIE

#define MCCI_STM32H7_REG_RCC_CIER_CSIRDYIE   (UINT32_C(1) << 4)

Definition at line 1192 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIER_HSERDYIE

#define MCCI_STM32H7_REG_RCC_CIER_HSERDYIE   (UINT32_C(1) << 3)

Definition at line 1193 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIER_HSI48RDYIE

#define MCCI_STM32H7_REG_RCC_CIER_HSI48RDYIE   (UINT32_C(1) << 5)

Definition at line 1191 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIER_HSIRDYIE

#define MCCI_STM32H7_REG_RCC_CIER_HSIRDYIE   (UINT32_C(1) << 2)

Definition at line 1194 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIER_LSECSSIE

#define MCCI_STM32H7_REG_RCC_CIER_LSECSSIE   (UINT32_C(1) << 9)

Definition at line 1187 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIER_LSERDYIE

#define MCCI_STM32H7_REG_RCC_CIER_LSERDYIE   (UINT32_C(1) << 1)

Definition at line 1195 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIER_LSIRDYIE

#define MCCI_STM32H7_REG_RCC_CIER_LSIRDYIE   (UINT32_C(1) << 0)

Definition at line 1196 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIER_PLL1RDYIE

#define MCCI_STM32H7_REG_RCC_CIER_PLL1RDYIE   (UINT32_C(1) << 6)

Definition at line 1190 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIER_PLL2RDYIE

#define MCCI_STM32H7_REG_RCC_CIER_PLL2RDYIE   (UINT32_C(1) << 7)

Definition at line 1189 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIER_PLL3RDYIE

#define MCCI_STM32H7_REG_RCC_CIER_PLL3RDYIE   (UINT32_C(1) << 8)

Definition at line 1188 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIER_RSV10

#define MCCI_STM32H7_REG_RCC_CIER_RSV10   UINT32_C(0xFFFFFC00)

Definition at line 1186 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIFR

#define MCCI_STM32H7_REG_RCC_CIFR   (MCCI_STM32H7_REG_RCC + 0x64)

clock source interrupt flag

Definition at line 701 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIFR_CSIRDYF

#define MCCI_STM32H7_REG_RCC_CIFR_CSIRDYF   (UINT32_C(1) << 4)

Definition at line 1208 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIFR_HSECSSF

#define MCCI_STM32H7_REG_RCC_CIFR_HSECSSF   (UINT32_C(1) << 10)

Definition at line 1202 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIFR_HSERDYF

#define MCCI_STM32H7_REG_RCC_CIFR_HSERDYF   (UINT32_C(1) << 3)

Definition at line 1209 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIFR_HSI48RDYF

#define MCCI_STM32H7_REG_RCC_CIFR_HSI48RDYF   (UINT32_C(1) << 5)

Definition at line 1207 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIFR_HSIRDYF

#define MCCI_STM32H7_REG_RCC_CIFR_HSIRDYF   (UINT32_C(1) << 2)

Definition at line 1210 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIFR_LSECSSF

#define MCCI_STM32H7_REG_RCC_CIFR_LSECSSF   (UINT32_C(1) << 9)

Definition at line 1203 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIFR_LSERDYF

#define MCCI_STM32H7_REG_RCC_CIFR_LSERDYF   (UINT32_C(1) << 1)

Definition at line 1211 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIFR_LSIRDYF

#define MCCI_STM32H7_REG_RCC_CIFR_LSIRDYF   (UINT32_C(1) << 0)

Definition at line 1212 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIFR_PLL1RDYF

#define MCCI_STM32H7_REG_RCC_CIFR_PLL1RDYF   (UINT32_C(1) << 6)

Definition at line 1206 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIFR_PLL2RDYF

#define MCCI_STM32H7_REG_RCC_CIFR_PLL2RDYF   (UINT32_C(1) << 7)

Definition at line 1205 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIFR_PLL3RDYF

#define MCCI_STM32H7_REG_RCC_CIFR_PLL3RDYF   (UINT32_C(1) << 8)

Definition at line 1204 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CIFR_RSV11

#define MCCI_STM32H7_REG_RCC_CIFR_RSV11   UINT32_C(0xFFFFF800)

Definition at line 1201 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR

#define MCCI_STM32H7_REG_RCC_CKGAENR   (MCCI_STM32H7_REG_RCC + 0xB0)

AXI clocks gating enable.

Definition at line 715 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_AHB12CKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_AHB12CKG   (UINT32_C(1) << 8)

Definition at line 1473 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_AHB34CKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_AHB34CKG   (UINT32_C(1) << 9)

Definition at line 1472 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_AHBCKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_AHBCKG   (UINT32_C(1) << 1)

Definition at line 1480 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_AXICKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_AXICKG   (UINT32_C(1) << 0)

Definition at line 1481 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_AXIRAM1CKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_AXIRAM1CKG   (UINT32_C(1) << 14)

Definition at line 1467 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_AXIRAM2CKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_AXIRAM2CKG   (UINT32_C(1) << 15)

Definition at line 1466 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_AXIRAM3CKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_AXIRAM3CKG   (UINT32_C(1) << 16)

Definition at line 1465 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_CPUCKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_CPUCKG   (UINT32_C(1) << 2)

Definition at line 1479 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_DMA2DCKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_DMA2DCKG   (UINT32_C(1) << 5)

Definition at line 1476 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_ECCRAMCKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_ECCRAMCKG   (UINT32_C(1) << 29)

Definition at line 1462 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_EXTICKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_EXTICKG   (UINT32_C(1) << 30)

Definition at line 1461 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_FLIFTCKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_FLIFTCKG   (UINT32_C(1) << 10)

Definition at line 1471 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_FMCCKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_FMCCKG   (UINT32_C(1) << 12)

Definition at line 1469 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_GFXMMUMCKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_GFXMMUMCKG   (UINT32_C(1) << 7)

Definition at line 1474 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_GFXMMUSCKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_GFXMMUSCKG   (UINT32_C(1) << 17)

Definition at line 1464 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_JTAGCKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_JTAGCKG   (UINT32_C(1) << 31)

Definition at line 1460 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_LTDCCKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_LTDCCKG   (UINT32_C(1) << 6)

Definition at line 1475 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_MDMACKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_MDMACKG   (UINT32_C(1) << 4)

Definition at line 1477 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_OCTOSPI1CKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_OCTOSPI1CKG   (UINT32_C(1) << 13)

Definition at line 1468 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_OCTOSPI2CKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_OCTOSPI2CKG   (UINT32_C(1) << 11)

Definition at line 1470 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_RSV18

#define MCCI_STM32H7_REG_RCC_CKGAENR_RSV18   UINT32_C(0x1FFC0000)

Definition at line 1463 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CKGAENR_SDMMCCKG

#define MCCI_STM32H7_REG_RCC_CKGAENR_SDMMCCKG   (UINT32_C(1) << 3)

Definition at line 1478 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR

#define MCCI_STM32H7_REG_RCC_CR   (MCCI_STM32H7_REG_RCC + 0x00)

source control

Definition at line 680 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_CDCKRDY

#define MCCI_STM32H7_REG_RCC_CR_CDCKRDY   (UINT32_C(1) << 15)

Definition at line 752 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_CPUCKRDY

#define MCCI_STM32H7_REG_RCC_CR_CPUCKRDY   (UINT32_C(1) << 14)

Definition at line 753 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_CSIKERON

#define MCCI_STM32H7_REG_RCC_CR_CSIKERON   (UINT32_C(1) << 9)

Definition at line 757 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_CSION

#define MCCI_STM32H7_REG_RCC_CR_CSION   (UINT32_C(1) << 7)

Definition at line 759 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_CSIRDY

#define MCCI_STM32H7_REG_RCC_CR_CSIRDY   (UINT32_C(1) << 8)

Definition at line 758 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_HSEBYP

#define MCCI_STM32H7_REG_RCC_CR_HSEBYP   (UINT32_C(1) << 18)

Definition at line 749 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_HSECSSON

#define MCCI_STM32H7_REG_RCC_CR_HSECSSON   (UINT32_C(1) << 19)

Definition at line 748 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_HSEEXT

#define MCCI_STM32H7_REG_RCC_CR_HSEEXT   (UINT32_C(1) << 20)

Definition at line 747 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_HSEON

#define MCCI_STM32H7_REG_RCC_CR_HSEON   (UINT32_C(1) << 16)

Definition at line 751 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_HSERDY

#define MCCI_STM32H7_REG_RCC_CR_HSERDY   (UINT32_C(1) << 17)

Definition at line 750 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_HSI48ON

#define MCCI_STM32H7_REG_RCC_CR_HSI48ON   (UINT32_C(1) << 12)

Definition at line 755 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_HSI48RDY

#define MCCI_STM32H7_REG_RCC_CR_HSI48RDY   (UINT32_C(1) << 13)

Definition at line 754 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_HSIDIV

#define MCCI_STM32H7_REG_RCC_CR_HSIDIV   (UINT32_C(3) << 3)

Definition at line 762 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_HSIDIV_1

#define MCCI_STM32H7_REG_RCC_CR_HSIDIV_1   (UINT32_C(0) << 3)

Definition at line 763 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_HSIDIV_2

#define MCCI_STM32H7_REG_RCC_CR_HSIDIV_2   (UINT32_C(1) << 3)

Definition at line 764 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_HSIDIV_3

#define MCCI_STM32H7_REG_RCC_CR_HSIDIV_3   (UINT32_C(2) << 3)

Definition at line 765 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_HSIDIV_8

#define MCCI_STM32H7_REG_RCC_CR_HSIDIV_8   (UINT32_C(3) << 3)

Definition at line 766 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_HSIDIVF

#define MCCI_STM32H7_REG_RCC_CR_HSIDIVF   (UINT32_C(1) << 5)

Definition at line 761 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_HSIKERON

#define MCCI_STM32H7_REG_RCC_CR_HSIKERON   (UINT32_C(1) << 1)

Definition at line 768 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_HSION

#define MCCI_STM32H7_REG_RCC_CR_HSION   (UINT32_C(1) << 0)

Definition at line 769 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_HSIRDY

#define MCCI_STM32H7_REG_RCC_CR_HSIRDY   (UINT32_C(1) << 2)

Definition at line 767 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_PLL1ON

#define MCCI_STM32H7_REG_RCC_CR_PLL1ON   (UINT32_C(1) << 24)

Definition at line 745 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_PLL1RDY

#define MCCI_STM32H7_REG_RCC_CR_PLL1RDY   (UINT32_C(1) << 25)

Definition at line 744 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_PLL2ON

#define MCCI_STM32H7_REG_RCC_CR_PLL2ON   (UINT32_C(1) << 26)

Definition at line 743 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_PLL2RDY

#define MCCI_STM32H7_REG_RCC_CR_PLL2RDY   (UINT32_C(1) << 27)

Definition at line 742 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_PLL3ON

#define MCCI_STM32H7_REG_RCC_CR_PLL3ON   (UINT32_C(1) << 28)

Definition at line 741 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_PLL3RDY

#define MCCI_STM32H7_REG_RCC_CR_PLL3RDY   (UINT32_C(1) << 29)

Definition at line 740 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_RSV10

#define MCCI_STM32H7_REG_RCC_CR_RSV10   (UINT32_C(3) << 10)

Definition at line 756 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_RSV21

#define MCCI_STM32H7_REG_RCC_CR_RSV21   (UINT32_C(7) << 21)

Definition at line 746 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_RSV30

#define MCCI_STM32H7_REG_RCC_CR_RSV30   (UINT32_C(3) << 30)

Definition at line 739 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CR_RSV6

#define MCCI_STM32H7_REG_RCC_CR_RSV6   (UINT32_C(1) << 6)

Definition at line 760 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CRRCR

#define MCCI_STM32H7_REG_RCC_CRRCR   (MCCI_STM32H7_REG_RCC + 0x08)

Clock recovery RC.

Definition at line 682 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CRRCR_HSI48CAL

#define MCCI_STM32H7_REG_RCC_CRRCR_HSI48CAL   (UINT32_C(0x3FF) << 0)

Definition at line 783 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CRRCR_RSV10

#define MCCI_STM32H7_REG_RCC_CRRCR_RSV10   UINT32_C(0xFFFFFC00)

Definition at line 782 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CSICFGR

#define MCCI_STM32H7_REG_RCC_CSICFGR   (MCCI_STM32H7_REG_RCC + 0x0C)

CSI calibration.

Definition at line 683 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CSICFGR_CSICAL

#define MCCI_STM32H7_REG_RCC_CSICFGR_CSICAL   (UINT32_C(0xFF) << 0)

Definition at line 791 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CSICFGR_CSITRIM

#define MCCI_STM32H7_REG_RCC_CSICFGR_CSITRIM   (UINT32_C(0x3F) << 24)

Definition at line 789 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CSICFGR_RSV30

#define MCCI_STM32H7_REG_RCC_CSICFGR_RSV30   (UINT32_C(3) << 30)

Definition at line 788 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CSICFGR_RSV8

#define MCCI_STM32H7_REG_RCC_CSICFGR_RSV8   (UINT32_C(0xFFFF) << 8)

Definition at line 790 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CSR

#define MCCI_STM32H7_REG_RCC_CSR   (MCCI_STM32H7_REG_RCC + 0x74)

clock control and status

Definition at line 704 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CSR_LSION

#define MCCI_STM32H7_REG_RCC_CSR_LSION   (UINT32_C(1) << 0)

Definition at line 1259 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CSR_LSIRDY

#define MCCI_STM32H7_REG_RCC_CSR_LSIRDY   (UINT32_C(1) << 1)

Definition at line 1258 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_CSR_RSV2

#define MCCI_STM32H7_REG_RCC_CSR_RSV2   UINT32_C(0xFFFFFFFC)

Definition at line 1257 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_HSICFGR

#define MCCI_STM32H7_REG_RCC_HSICFGR   (MCCI_STM32H7_REG_RCC + 0x04)

HSI calibration.

Definition at line 681 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_HSICFGR_HSICAL

#define MCCI_STM32H7_REG_RCC_HSICFGR_HSICAL   (UINT32_C(0xFFF) << 0)

Definition at line 777 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_HSICFGR_HSITRIM

#define MCCI_STM32H7_REG_RCC_HSICFGR_HSITRIM   (UINT32_C(0x7F) << 24)

Definition at line 775 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_HSICFGR_RSV12

#define MCCI_STM32H7_REG_RCC_HSICFGR_RSV12   (UINT32_C(0xFFF) << 12)

Definition at line 776 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_HSICFGR_RSV31

#define MCCI_STM32H7_REG_RCC_HSICFGR_RSV31   (UINT32_C(1) << 31)

Definition at line 774 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL1DIVR

#define MCCI_STM32H7_REG_RCC_PLL1DIVR   (MCCI_STM32H7_REG_RCC + 0x30)

PLL1 dividers configuration.

Definition at line 690 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVN

#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVN   (UINT32_C(0x1FF) << 0)

Definition at line 956 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVN_N

#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVN_N (   n)    ((n) << 0)

Definition at line 957 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVP

#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVP   (UINT32_C(0x7F) << 9)

Definition at line 954 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVP_N

#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVP_N (   n)    ((n) << 9)

Definition at line 955 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVQ

#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVQ   (UINT32_C(0x7F) << 16)

Definition at line 952 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVQ_N

#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVQ_N (   n)    ((n) << 16)

Definition at line 953 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVR

#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVR   (UINT32_C(0x7F) << 24)

Definition at line 949 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVR_N

#define MCCI_STM32H7_REG_RCC_PLL1DIVR_DIVR_N (   n)    ((n) << 24)

Definition at line 950 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL1DIVR_RSV23

#define MCCI_STM32H7_REG_RCC_PLL1DIVR_RSV23   (UINT32_C(1) << 23)

Definition at line 951 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL1DIVR_RSV31

#define MCCI_STM32H7_REG_RCC_PLL1DIVR_RSV31   (UINT32_C(1) << 31)

Definition at line 948 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL1FRACR

#define MCCI_STM32H7_REG_RCC_PLL1FRACR   (MCCI_STM32H7_REG_RCC + 0x34)

PLL1 fractional divider.

Definition at line 691 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL1FRACR_FRACN

#define MCCI_STM32H7_REG_RCC_PLL1FRACR_FRACN   (UINT32_C(0x1FFF) << 3)

Definition at line 963 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL1FRACR_FRACN_N

#define MCCI_STM32H7_REG_RCC_PLL1FRACR_FRACN_N (   n)    ((n) << 3)

Definition at line 964 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL1FRACR_RSV0

#define MCCI_STM32H7_REG_RCC_PLL1FRACR_RSV0   (UINT32_C(7) << 0)

Definition at line 965 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL1FRACR_RSV16

#define MCCI_STM32H7_REG_RCC_PLL1FRACR_RSV16   UINT32_C(0xFFFF0000)

Definition at line 962 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL2DIVR

#define MCCI_STM32H7_REG_RCC_PLL2DIVR   (MCCI_STM32H7_REG_RCC + 0x38)

PLL2 dividers configuration.

Definition at line 692 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVN

#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVN   (UINT32_C(0x1FF) << 0)

Definition at line 978 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVN_N

#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVN_N (   n)    ((n) << 0)

Definition at line 979 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVP

#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVP   (UINT32_C(0x7F) << 9)

Definition at line 976 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVP_N

#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVP_N (   n)    ((n) << 9)

Definition at line 977 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVQ

#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVQ   (UINT32_C(0x7F) << 16)

Definition at line 974 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVQ_N

#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVQ_N (   n)    ((n) << 16)

Definition at line 975 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVR

#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVR   (UINT32_C(0x7F) << 24)

Definition at line 971 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVR_N

#define MCCI_STM32H7_REG_RCC_PLL2DIVR_DIVR_N (   n)    ((n) << 24)

Definition at line 972 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL2DIVR_RSV23

#define MCCI_STM32H7_REG_RCC_PLL2DIVR_RSV23   (UINT32_C(1) << 23)

Definition at line 973 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL2DIVR_RSV31

#define MCCI_STM32H7_REG_RCC_PLL2DIVR_RSV31   (UINT32_C(1) << 31)

Definition at line 970 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL2FRACR

#define MCCI_STM32H7_REG_RCC_PLL2FRACR   (MCCI_STM32H7_REG_RCC + 0x3C)

PLL2 fractional divider.

Definition at line 693 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL2FRACR_FRACN

#define MCCI_STM32H7_REG_RCC_PLL2FRACR_FRACN   (UINT32_C(0x1FFF) << 3)

Definition at line 985 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL2FRACR_FRACN_N

#define MCCI_STM32H7_REG_RCC_PLL2FRACR_FRACN_N (   n)    ((n) << 3)

Definition at line 986 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL2FRACR_RSV0

#define MCCI_STM32H7_REG_RCC_PLL2FRACR_RSV0   (UINT32_C(7) << 0)

Definition at line 987 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL2FRACR_RSV16

#define MCCI_STM32H7_REG_RCC_PLL2FRACR_RSV16   UINT32_C(0xFFFF0000)

Definition at line 984 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL3DIVR

#define MCCI_STM32H7_REG_RCC_PLL3DIVR   (MCCI_STM32H7_REG_RCC + 0x40)

PLL3 dividers configuration.

Definition at line 694 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVN

#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVN   (UINT32_C(0x1FF) << 0)

Definition at line 1000 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVN_N

#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVN_N (   n)    ((n) << 0)

Definition at line 1001 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVP

#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVP   (UINT32_C(0x7F) << 9)

Definition at line 998 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVP_N

#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVP_N (   n)    ((n) << 9)

Definition at line 999 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVQ

#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVQ   (UINT32_C(0x7F) << 16)

Definition at line 996 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVQ_N

#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVQ_N (   n)    ((n) << 16)

Definition at line 997 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVR

#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVR   (UINT32_C(0x7F) << 24)

Definition at line 993 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVR_N

#define MCCI_STM32H7_REG_RCC_PLL3DIVR_DIVR_N (   n)    ((n) << 24)

Definition at line 994 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL3DIVR_RSV23

#define MCCI_STM32H7_REG_RCC_PLL3DIVR_RSV23   (UINT32_C(1) << 23)

Definition at line 995 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL3DIVR_RSV31

#define MCCI_STM32H7_REG_RCC_PLL3DIVR_RSV31   (UINT32_C(1) << 31)

Definition at line 992 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL3FRACR

#define MCCI_STM32H7_REG_RCC_PLL3FRACR   (MCCI_STM32H7_REG_RCC + 0x44)

PLL4 fractional divider.

Definition at line 695 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL3FRACR_FRACN

#define MCCI_STM32H7_REG_RCC_PLL3FRACR_FRACN   (UINT32_C(0x1FFF) << 3)

Definition at line 1007 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL3FRACR_FRACN_N

#define MCCI_STM32H7_REG_RCC_PLL3FRACR_FRACN_N (   n)    ((n) << 3)

Definition at line 1008 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL3FRACR_RSV0

#define MCCI_STM32H7_REG_RCC_PLL3FRACR_RSV0   (UINT32_C(7) << 0)

Definition at line 1009 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLL3FRACR_RSV16

#define MCCI_STM32H7_REG_RCC_PLL3FRACR_RSV16   UINT32_C(0xFFFF0000)

Definition at line 1006 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR

#define MCCI_STM32H7_REG_RCC_PLLCFGR   (MCCI_STM32H7_REG_RCC + 0x2C)

PLLs configuration.

Definition at line 689 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_DIVP1EN

#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVP1EN   (UINT32_C(1) << 16)

Definition at line 930 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_DIVP2EN

#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVP2EN   (UINT32_C(1) << 19)

Definition at line 927 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_DIVP3EN

#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVP3EN   (UINT32_C(1) << 22)

Definition at line 924 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_DIVQ1EN

#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVQ1EN   (UINT32_C(1) << 17)

Definition at line 929 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_DIVQ2EN

#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVQ2EN   (UINT32_C(1) << 20)

Definition at line 926 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_DIVQ3EN

#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVQ3EN   (UINT32_C(1) << 23)

Definition at line 923 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_DIVR1EN

#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVR1EN   (UINT32_C(1) << 18)

Definition at line 928 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_DIVR2EN

#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVR2EN   (UINT32_C(1) << 21)

Definition at line 925 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_DIVR3EN

#define MCCI_STM32H7_REG_RCC_PLLCFGR_DIVR3EN   (UINT32_C(1) << 24)

Definition at line 922 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_PLL1FRACEN

#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL1FRACEN   (UINT32_C(1) << 0)

Definition at line 943 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_PLL1RGE

#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL1RGE   (UINT32_C(3) << 2)

Definition at line 940 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_PLL1RGE_N

#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL1RGE_N (   n)    ((n) << 2)

Definition at line 941 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_PLL1VCOSEL

#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL1VCOSEL   (UINT32_C(1) << 1)

Definition at line 942 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_PLL2FRACEN

#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL2FRACEN   (UINT32_C(1) << 4)

Definition at line 939 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_PLL2RGE

#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL2RGE   (UINT32_C(3) << 6)

Definition at line 936 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_PLL2RGE_N

#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL2RGE_N (   n)    ((n) << 6)

Definition at line 937 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_PLL2VCOSEL

#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL2VCOSEL   (UINT32_C(1) << 5)

Definition at line 938 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_PLL3FRACEN

#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL3FRACEN   (UINT32_C(1) << 8)

Definition at line 935 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_PLL3RGE

#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL3RGE   (UINT32_C(3) << 10)

Definition at line 932 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_PLL3RGE_N

#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL3RGE_N (   n)    ((n) << 10)

Definition at line 933 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_PLL3VCOSEL

#define MCCI_STM32H7_REG_RCC_PLLCFGR_PLL3VCOSEL   (UINT32_C(1) << 9)

Definition at line 934 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_RSV12

#define MCCI_STM32H7_REG_RCC_PLLCFGR_RSV12   (UINT32_C(0xF) << 12)

Definition at line 931 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCFGR_RSV25

#define MCCI_STM32H7_REG_RCC_PLLCFGR_RSV25   (UINT32_C(0x7F) << 25)

Definition at line 921 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCKSELR

#define MCCI_STM32H7_REG_RCC_PLLCKSELR   (MCCI_STM32H7_REG_RCC + 0x28)

PLLs clock source selection.

Definition at line 688 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM1

#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM1   (UINT32_C(0x3F) << 14)

Definition at line 909 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM1_DIS

#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM1_DIS   (UINT32_C(0x3F) << 14)

Definition at line 910 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM1_N

#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM1_N (   n)    ((n) << 14)

Definition at line 911 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM2

#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM2   (UINT32_C(0x3F) << 12)

Definition at line 905 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM2_DIS

#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM2_DIS   (UINT32_C(0x3F) << 12)

Definition at line 906 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM2_N

#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM2_N (   n)    ((n) << 12)

Definition at line 907 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM3

#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM3   (UINT32_C(0x3F) << 20)

Definition at line 901 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM3_DIS

#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM3_DIS   (UINT32_C(0x3F) << 20)

Definition at line 902 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM3_N

#define MCCI_STM32H7_REG_RCC_PLLCKSELR_DIVM3_N (   n)    ((n) << 20)

Definition at line 903 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCKSELR_PLLSRC

#define MCCI_STM32H7_REG_RCC_PLLCKSELR_PLLSRC   (UINT32_C(3) << 0)

Definition at line 913 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCKSELR_PLLSRC_CSI

#define MCCI_STM32H7_REG_RCC_PLLCKSELR_PLLSRC_CSI   (UINT32_C(1) << 0)

Definition at line 915 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCKSELR_PLLSRC_HSE

#define MCCI_STM32H7_REG_RCC_PLLCKSELR_PLLSRC_HSE   (UINT32_C(2) << 0)

Definition at line 916 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCKSELR_PLLSRC_HSI

#define MCCI_STM32H7_REG_RCC_PLLCKSELR_PLLSRC_HSI   (UINT32_C(0) << 0)

Definition at line 914 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCKSELR_RSV10

#define MCCI_STM32H7_REG_RCC_PLLCKSELR_RSV10   (UINT32_C(3) << 10)

Definition at line 908 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCKSELR_RSV18

#define MCCI_STM32H7_REG_RCC_PLLCKSELR_RSV18   (UINT32_C(3) << 18)

Definition at line 904 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCKSELR_RSV2

#define MCCI_STM32H7_REG_RCC_PLLCKSELR_RSV2   (UINT32_C(3) << 2)

Definition at line 912 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_PLLCKSELR_RSV26

#define MCCI_STM32H7_REG_RCC_PLLCKSELR_RSV26   (UINT32_C(0x3F) << 26)

Definition at line 900 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_RSR

#define MCCI_STM32H7_REG_RCC_RSR   (MCCI_STM32H7_REG_RCC + 0x130)

reset status

Definition at line 716 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_RSR_BORRSTF

#define MCCI_STM32H7_REG_RCC_RSR_BORRSTF   (UINT32_C(1) << 21)

Definition at line 1496 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_RSR_CDRSTF

#define MCCI_STM32H7_REG_RCC_RSR_CDRSTF   (UINT32_C(1) << 19)

Definition at line 1498 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_RSR_IWDGRSTF

#define MCCI_STM32H7_REG_RCC_RSR_IWDGRSTF   (UINT32_C(1) << 26)

Definition at line 1491 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_RSR_LPWRRSTF

#define MCCI_STM32H7_REG_RCC_RSR_LPWRRSTF   (UINT32_C(1) << 30)

Definition at line 1487 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_RSR_PINRSTF

#define MCCI_STM32H7_REG_RCC_RSR_PINRSTF   (UINT32_C(1) << 22)

Definition at line 1495 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_RSR_PORRSTF

#define MCCI_STM32H7_REG_RCC_RSR_PORRSTF   (UINT32_C(1) << 23)

Definition at line 1494 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_RSR_RMVF

#define MCCI_STM32H7_REG_RCC_RSR_RMVF   (UINT32_C(1) << 16)

Definition at line 1500 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_RSR_RSV0

#define MCCI_STM32H7_REG_RCC_RSR_RSV0   UINT32_C(0x0000FFFF)

Definition at line 1501 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_RSR_RSV18

#define MCCI_STM32H7_REG_RCC_RSR_RSV18   (UINT32_C(3) << 18)

Definition at line 1499 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_RSR_RSV20

#define MCCI_STM32H7_REG_RCC_RSR_RSV20   (UINT32_C(1) << 20)

Definition at line 1497 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_RSR_RSV25

#define MCCI_STM32H7_REG_RCC_RSR_RSV25   (UINT32_C(1) << 25)

Definition at line 1492 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_RSR_RSV27

#define MCCI_STM32H7_REG_RCC_RSR_RSV27   (UINT32_C(1) << 27)

Definition at line 1490 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_RSR_RSV29

#define MCCI_STM32H7_REG_RCC_RSR_RSV29   (UINT32_C(1) << 29)

Definition at line 1488 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_RSR_RSV31

#define MCCI_STM32H7_REG_RCC_RSR_RSV31   (UINT32_C(1) << 31)

Definition at line 1486 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_RSR_SFTRSTF

#define MCCI_STM32H7_REG_RCC_RSR_SFTRSTF   (UINT32_C(1) << 24)

Definition at line 1493 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_RSR_WWDGRSTF

#define MCCI_STM32H7_REG_RCC_RSR_WWDGRSTF   (UINT32_C(1) << 28)

Definition at line 1489 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR

#define MCCI_STM32H7_REG_RCC_SRDAMR   (MCCI_STM32H7_REG_RCC + 0xA8)

SmartRun domain Autonomous mode.

Definition at line 714 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_BDMA2AMEN

#define MCCI_STM32H7_REG_RCC_SRDAMR_BDMA2AMEN   (UINT32_C(1) << 0)

Definition at line 1455 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_BKPRAMAMEN

#define MCCI_STM32H7_REG_RCC_SRDAMR_BKPRAMAMEN   (UINT32_C(1) << 28)

Definition at line 1436 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_COMP12AMEN

#define MCCI_STM32H7_REG_RCC_SRDAMR_COMP12AMEN   (UINT32_C(1) << 14)

Definition at line 1442 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_DAC2AMEN

#define MCCI_STM32H7_REG_RCC_SRDAMR_DAC2AMEN   (UINT32_C(1) << 13)

Definition at line 1443 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_DFSDM2AMEN

#define MCCI_STM32H7_REG_RCC_SRDAMR_DFSDM2AMEN   (UINT32_C(1) << 27)

Definition at line 1437 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_DTSAMEN

#define MCCI_STM32H7_REG_RCC_SRDAMR_DTSAMEN   (UINT32_C(1) << 26)

Definition at line 1438 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_GPIOAMEN

#define MCCI_STM32H7_REG_RCC_SRDAMR_GPIOAMEN   (UINT32_C(1) << 1)

Definition at line 1454 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_I2C4AMEN

#define MCCI_STM32H7_REG_RCC_SRDAMR_I2C4AMEN   (UINT32_C(1) << 7)

Definition at line 1448 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_LPTIM2AMEN

#define MCCI_STM32H7_REG_RCC_SRDAMR_LPTIM2AMEN   (UINT32_C(1) << 9)

Definition at line 1446 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_LPTIM3AMEN

#define MCCI_STM32H7_REG_RCC_SRDAMR_LPTIM3AMEN   (UINT32_C(1) << 10)

Definition at line 1445 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_LPUART1AMEN

#define MCCI_STM32H7_REG_RCC_SRDAMR_LPUART1AMEN   (UINT32_C(1) << 3)

Definition at line 1452 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_RSV11

#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV11   (UINT32_C(3) << 11)

Definition at line 1444 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_RSV17

#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV17   (UINT32_C(0x1FF) << 17)

Definition at line 1439 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_RSV2

#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV2   (UINT32_C(1) << 2)

Definition at line 1453 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_RSV25

#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV25   (UINT32_C(3) << 30)

Definition at line 1434 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_RSV4

#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV4   (UINT32_C(1) << 4)

Definition at line 1451 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_RSV6

#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV6   (UINT32_C(1) << 6)

Definition at line 1449 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_RSV8

#define MCCI_STM32H7_REG_RCC_SRDAMR_RSV8   (UINT32_C(7) << 8)

Definition at line 1447 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_RTCAMEN

#define MCCI_STM32H7_REG_RCC_SRDAMR_RTCAMEN   (UINT32_C(1) << 16)

Definition at line 1440 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_SPI6AMEN

#define MCCI_STM32H7_REG_RCC_SRDAMR_SPI6AMEN   (UINT32_C(1) << 5)

Definition at line 1450 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_SRDSRAMAMEN

#define MCCI_STM32H7_REG_RCC_SRDAMR_SRDSRAMAMEN   (UINT32_C(1) << 29)

Definition at line 1435 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDAMR_VREFAMEN

#define MCCI_STM32H7_REG_RCC_SRDAMR_VREFAMEN   (UINT32_C(1) << 15)

Definition at line 1441 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR

#define MCCI_STM32H7_REG_RCC_SRDCCIPR   (MCCI_STM32H7_REG_RCC + 0x58)

SmartRun domain kernel clock configuration.

Definition at line 699 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_ADCSEL

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_ADCSEL   (UINT32_C(3) << 16)

Definition at line 1151 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_ADCSEL_PER

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_ADCSEL_PER   (UINT32_C(2) << 16)

Definition at line 1154 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_ADCSEL_PLL2

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_ADCSEL_PLL2   (UINT32_C(0) << 16)

Definition at line 1152 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_ADCSEL_PLL3

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_ADCSEL_PLL3   (UINT32_C(1) << 16)

Definition at line 1153 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_DFSDM2SEL

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_DFSDM2SEL   (UINT32_C(1) << 27)

Definition at line 1149 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_I2C4SEL

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_I2C4SEL   (UINT32_C(3) << 8)

Definition at line 1169 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_I2C4SEL_CSI

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_I2C4SEL_CSI   (UINT32_C(3) << 8)

Definition at line 1173 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_I2C4SEL_HSI

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_I2C4SEL_HSI   (UINT32_C(2) << 8)

Definition at line 1172 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_I2C4SEL_PCLK4

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_I2C4SEL_PCLK4   (UINT32_C(0) << 8)

Definition at line 1170 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_I2C4SEL_PLL3

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_I2C4SEL_PLL3   (UINT32_C(1) << 8)

Definition at line 1171 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL   (UINT32_C(7) << 10)

Definition at line 1162 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_LSE

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_LSE   (UINT32_C(3) << 10)

Definition at line 1166 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_LSI

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_LSI   (UINT32_C(4) << 10)

Definition at line 1167 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_PCLK4

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_PCLK4   (UINT32_C(0) << 10)

Definition at line 1163 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_PER

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_PER   (UINT32_C(5) << 10)

Definition at line 1168 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_PLL2

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_PLL2   (UINT32_C(1) << 10)

Definition at line 1164 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_PLL3

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM2SEL_PLL3   (UINT32_C(2) << 10)

Definition at line 1165 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL   (UINT32_C(7) << 13)

Definition at line 1155 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_LSE

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_LSE   (UINT32_C(3) << 13)

Definition at line 1159 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_LSI

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_LSI   (UINT32_C(4) << 13)

Definition at line 1160 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_PCLK4

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_PCLK4   (UINT32_C(0) << 13)

Definition at line 1156 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_PER

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_PER   (UINT32_C(5) << 13)

Definition at line 1161 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_PLL2

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_PLL2   (UINT32_C(1) << 13)

Definition at line 1157 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_PLL3

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPTIM3SEL_PLL3   (UINT32_C(2) << 13)

Definition at line 1158 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL   (UINT32_C(7) << 0)

Definition at line 1175 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_CSI

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_CSI   (UINT32_C(4) << 0)

Definition at line 1180 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_HSI

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_HSI   (UINT32_C(3) << 0)

Definition at line 1179 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_LSE

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_LSE   (UINT32_C(5) << 0)

Definition at line 1181 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_PCLK4

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_PCLK4   (UINT32_C(0) << 0)

Definition at line 1176 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_PLL2

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_PLL2   (UINT32_C(1) << 0)

Definition at line 1177 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_PLL3

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_LPUART1SEL_PLL3   (UINT32_C(2) << 0)

Definition at line 1178 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_RSV18

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_RSV18   (UINT32_C(0x1FF) << 18)

Definition at line 1150 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_RSV3

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_RSV3   (UINT32_C(0x1F) << 3)

Definition at line 1174 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_RSV31

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_RSV31   (UINT32_C(1) << 31)

Definition at line 1140 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL   (UINT32_C(7) << 28)

Definition at line 1141 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_CSI

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_CSI   (UINT32_C(4) << 28)

Definition at line 1146 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_HSE

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_HSE   (UINT32_C(5) << 28)

Definition at line 1147 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_HSI

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_HSI   (UINT32_C(3) << 28)

Definition at line 1145 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_I2S

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_I2S   (UINT32_C(6) << 28)

Definition at line 1148 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_PCLK4

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_PCLK4   (UINT32_C(0) << 28)

Definition at line 1142 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_PLL2

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_PLL2   (UINT32_C(1) << 28)

Definition at line 1143 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_PLL3

#define MCCI_STM32H7_REG_RCC_SRDCCIPR_SPI6SEL_PLL3   (UINT32_C(2) << 28)

Definition at line 1144 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCFGR

#define MCCI_STM32H7_REG_RCC_SRDCFGR   (MCCI_STM32H7_REG_RCC + 0x20)

SmartRun domain clock configuration.

Definition at line 687 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCFGR_RSV0

#define MCCI_STM32H7_REG_RCC_SRDCFGR_RSV0   (UINT32_C(0xF) << 0)

Definition at line 895 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCFGR_RSV7

#define MCCI_STM32H7_REG_RCC_SRDCFGR_RSV7   UINT32_C(0xFFFFFF80)

Definition at line 888 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE

#define MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE   (UINT32_C(7) << 4)

Definition at line 889 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE_1

#define MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE_1   (UINT32_C(0) << 4)

Definition at line 890 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE_16

#define MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE_16   (UINT32_C(7) << 4)

Definition at line 894 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE_2

#define MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE_2   (UINT32_C(4) << 4)

Definition at line 891 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE_3

#define MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE_3   (UINT32_C(5) << 4)

Definition at line 892 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE_8

#define MCCI_STM32H7_REG_RCC_SRDCFGR_SRDPPRE_8   (UINT32_C(6) << 4)

Definition at line 893 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RNG

#define MCCI_STM32H7_REG_RNG   UINT32_C(0x48021800)

Section 38.7: RNG register map (1K)

Definition at line 126 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_RTC

#define MCCI_STM32H7_REG_RTC   UINT32_C(0x58004000)

Section 50.6: RTC register map (1K)

Definition at line 160 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_SAI1

#define MCCI_STM32H7_REG_SAI1   UINT32_C(0x40015800)

Section 56.6: SAI register map (1K)

Definition at line 112 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_SAI2

#define MCCI_STM32H7_REG_SAI2   UINT32_C(0x40015C00)

Section 56.6: SAI register map (1K)

Definition at line 113 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_SDMMC1

#define MCCI_STM32H7_REG_SDMMC1   UINT32_C(0x52007000)

Section 60.10: SDMMC register map (4K)

Definition at line 140 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_SDMMC2

#define MCCI_STM32H7_REG_SDMMC2   UINT32_C(0x48022400)

Section 60.10: SDMMC register map (1K)

Definition at line 127 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_SPDIFRX1

#define MCCI_STM32H7_REG_SPDIFRX1   UINT32_C(0x40004000)

Section 57.5: SPDIFRX interface register map (1K)

Definition at line 79 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_SPI1

#define MCCI_STM32H7_REG_SPI1   UINT32_C(0x40013000)

Section 55.11: SPI register map (1K)

Definition at line 105 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_SPI2

#define MCCI_STM32H7_REG_SPI2   UINT32_C(0x40003800)

Section 55.11: SPI register map (1K)

Definition at line 77 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_SPI3

#define MCCI_STM32H7_REG_SPI3   UINT32_C(0x40003C00)

Section 55.11: SPI register map (1K)

Definition at line 78 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_SPI4

#define MCCI_STM32H7_REG_SPI4   UINT32_C(0x40013400)

Section 55.11: SPI register map (1K)

Definition at line 107 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_SPI5

#define MCCI_STM32H7_REG_SPI5   UINT32_C(0x40015000)

Section 55.11: SPI register map (1K)

Definition at line 111 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_SPI6

#define MCCI_STM32H7_REG_SPI6   UINT32_C(0x58001400)

Section 55.11: SPI register map (1K)

Definition at line 152 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_SWPMI

#define MCCI_STM32H7_REG_SWPMI   UINT32_C(0x40008800)

Section 58.6: SWPMI register map (1K)

Definition at line 92 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_SYSCFG

#define MCCI_STM32H7_REG_SYSCFG   UINT32_C(0x58000400)

Section 12.4: SYSCFG register map (1K)

Definition at line 150 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_TAMP

#define MCCI_STM32H7_REG_TAMP   UINT32_C(0x58004400)

Section 51.6: TAMP register map (1K)

Definition at line 161 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_TIMER1

#define MCCI_STM32H7_REG_TIMER1   UINT32_C(0x40010000)

Section 42.4: TIMx register map (1K)

Definition at line 99 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_TIMER12

#define MCCI_STM32H7_REG_TIMER12   UINT32_C(0x40001800)

Section 43.4: TIM6/7 register map (1K)

Definition at line 73 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_TIMER13

#define MCCI_STM32H7_REG_TIMER13   UINT32_C(0x40001C00)

Section 43.4: TIM6/7 register map (1K)

Definition at line 74 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_TIMER14

#define MCCI_STM32H7_REG_TIMER14   UINT32_C(0x40002000)

Section 43.4: TIM6/7 register map (1K)

Definition at line 75 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_TIMER15

#define MCCI_STM32H7_REG_TIMER15   UINT32_C(0x40014000)

Section 45.5: TIMx register map (1K)

Definition at line 108 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_TIMER16

#define MCCI_STM32H7_REG_TIMER16   UINT32_C(0x40014400)

Section 45.5: TIMx register map (1K)

Definition at line 109 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_TIMER17

#define MCCI_STM32H7_REG_TIMER17   UINT32_C(0x40014800)

Section 45.5: TIMx register map (1K)

Definition at line 110 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_TIMER2

#define MCCI_STM32H7_REG_TIMER2   UINT32_C(0x40000000)

Section 43.4: TIMx register map (1K)

Definition at line 67 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_TIMER3

#define MCCI_STM32H7_REG_TIMER3   UINT32_C(0x40000400)

Section 43.4: TIMx register map (1K)

Definition at line 68 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_TIMER4

#define MCCI_STM32H7_REG_TIMER4   UINT32_C(0x40000800)

Section 43.4: TIMx register map (1K)

Definition at line 69 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_TIMER5

#define MCCI_STM32H7_REG_TIMER5   UINT32_C(0x40000C00)

Section 43.4: TIMx register map (1K)

Definition at line 70 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_TIMER6

#define MCCI_STM32H7_REG_TIMER6   UINT32_C(0x40001000)

Section 46.4: TIM6/7 register map (1K)

Definition at line 71 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_TIMER7

#define MCCI_STM32H7_REG_TIMER7   UINT32_C(0x40001400)

Section 46.4: TIM6/7 register map (1K)

Definition at line 72 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_TIMER8

#define MCCI_STM32H7_REG_TIMER8   UINT32_C(0x40010400)

Section 42.4: TIMx register map (1K)

Definition at line 100 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_TT_FDCAN

#define MCCI_STM32H7_REG_TT_FDCAN   UINT32_C(0x4000A000)

Section 61.5: FDCAN register map (1K)

Definition at line 95 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_UART4

#define MCCI_STM32H7_REG_UART4   UINT32_C(0x40004C00)

Section 53.7: USART register map (1K)

Definition at line 82 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_UART5

#define MCCI_STM32H7_REG_UART5   UINT32_C(0x40005000)

Section 53.7: USART register map (1K)

Definition at line 83 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_UART7

#define MCCI_STM32H7_REG_UART7   UINT32_C(0x40007800)

Section 53.7: USART register map (1K)

Definition at line 89 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_UART8

#define MCCI_STM32H7_REG_UART8   UINT32_C(0x40007C00)

Section 53.7: USART register map (1K)

Definition at line 90 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_UART9

#define MCCI_STM32H7_REG_UART9   UINT32_C(0x40011800)

Section 53.7: USART register map (1K)

Definition at line 103 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_USART1

#define MCCI_STM32H7_REG_USART1   UINT32_C(0x40011000)

Section 53.7: USART register map (1K)

Definition at line 101 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_USART10

#define MCCI_STM32H7_REG_USART10   UINT32_C(0x40011C00)

Section 53.7: USART register map (1K)

Definition at line 104 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_USART2

#define MCCI_STM32H7_REG_USART2   UINT32_C(0x40004400)

Section 53.7: USART register map (1K)

Definition at line 80 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_USART3

#define MCCI_STM32H7_REG_USART3   UINT32_C(0x40004800)

Section 53.7: USART register map (1K)

Definition at line 81 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_USART6

#define MCCI_STM32H7_REG_USART6   UINT32_C(0x40011400)

Section 53.7: USART register map (1K)

Definition at line 102 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_VREF

#define MCCI_STM32H7_REG_VREF   UINT32_C(0x58003C00)

Section 30.3: VREF register map (1K)

Definition at line 159 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_REG_WWDG

#define MCCI_STM32H7_REG_WWDG   UINT32_C(0x50003000)

Section 48.4: WWDG register map (4K)

Definition at line 131 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1

#define MCCI_STM32H7_SPI_CFG1   UINT32_C(0x08)

offset to SPI configuration register 1

Definition at line 2019 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_CRCEN

#define MCCI_STM32H7_SPI_CFG1_CRCEN   (UINT32_C(1) << 22)

hardware CRC computation enable

Definition at line 2068 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_CRCSIZE

#define MCCI_STM32H7_SPI_CFG1_CRCSIZE   (UINT32_C(0x1F) << 16)

length of CRC frame to be transacted and compared

Definition at line 2070 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_CRCSIZE_N

#define MCCI_STM32H7_SPI_CFG1_CRCSIZE_N (   n)    ((n) << 16)

n+1 bits

Definition at line 2071 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_DSIZE

#define MCCI_STM32H7_SPI_CFG1_DSIZE   (UINT32_C(0x1F) << 0)

number of bits in at single SPI data frame

Definition at line 2085 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_DSIZE_N

#define MCCI_STM32H7_SPI_CFG1_DSIZE_N (   n)    ((n) << 0)

n+1 bits

Definition at line 2086 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_FTHLV

#define MCCI_STM32H7_SPI_CFG1_FTHLV   (UINT32_C(0xF) << 5)

FIFO threshold level.

Definition at line 2083 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_FTHLV_N

#define MCCI_STM32H7_SPI_CFG1_FTHLV_N (   n)    ((n) << 5)

n+1 data

Definition at line 2084 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_MBR

#define MCCI_STM32H7_SPI_CFG1_MBR   (UINT32_C(7) << 28)

master baud rate

Definition at line 2058 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_MBR_128

#define MCCI_STM32H7_SPI_CFG1_MBR_128   (UINT32_C(6) << 28)

SPI master clock/128.

Definition at line 2065 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_MBR_16

#define MCCI_STM32H7_SPI_CFG1_MBR_16   (UINT32_C(3) << 28)

SPI master clock/16.

Definition at line 2062 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_MBR_2

#define MCCI_STM32H7_SPI_CFG1_MBR_2   (UINT32_C(0) << 28)

SPI master clock/2.

Definition at line 2059 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_MBR_256

#define MCCI_STM32H7_SPI_CFG1_MBR_256   (UINT32_C(7) << 28)

SPI master clock/256.

Definition at line 2066 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_MBR_32

#define MCCI_STM32H7_SPI_CFG1_MBR_32   (UINT32_C(4) << 28)

SPI master clock/32.

Definition at line 2063 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_MBR_4

#define MCCI_STM32H7_SPI_CFG1_MBR_4   (UINT32_C(1) << 28)

SPI master clock/4.

Definition at line 2060 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_MBR_64

#define MCCI_STM32H7_SPI_CFG1_MBR_64   (UINT32_C(5) << 28)

SPI master clock/64.

Definition at line 2064 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_MBR_8

#define MCCI_STM32H7_SPI_CFG1_MBR_8   (UINT32_C(2) << 28)

SPI master clock/8.

Definition at line 2061 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_RSV13

#define MCCI_STM32H7_SPI_CFG1_RSV13   (UINT32_C(1) << 13)

reserved, don't change

Definition at line 2074 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_RSV21

#define MCCI_STM32H7_SPI_CFG1_RSV21   (UINT32_C(1) << 21)

reserved, don't change

Definition at line 2069 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_RSV23

#define MCCI_STM32H7_SPI_CFG1_RSV23   (UINT32_C(0x1F) << 23)

reserved, don't change

Definition at line 2067 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_RSV31

#define MCCI_STM32H7_SPI_CFG1_RSV31   (UINT32_C(1) << 31)

reserved, don't change

Definition at line 2057 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_RXDMAEN

#define MCCI_STM32H7_SPI_CFG1_RXDMAEN   (UINT32_C(1) << 14)

Rx DMA stream enable.

Definition at line 2073 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_TXDMAEN

#define MCCI_STM32H7_SPI_CFG1_TXDMAEN   (UINT32_C(1) << 15)

Tx DMA stream enable.

Definition at line 2072 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_UDRCFG

#define MCCI_STM32H7_SPI_CFG1_UDRCFG   (UINT32_C(3) << 9)

behavior of slave transmitter at underrun condition

Definition at line 2079 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_UDRCFG_CONST

#define MCCI_STM32H7_SPI_CFG1_UDRCFG_CONST   (UINT32_C(0) << 9)

slave sends a constant pattern defined by the user at SPI_UDRDR register

Definition at line 2080 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_UDRCFG_RX

#define MCCI_STM32H7_SPI_CFG1_UDRCFG_RX   (UINT32_C(1) << 9)

slave repeats lastly received data frame from master

Definition at line 2081 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_UDRCFG_TX

#define MCCI_STM32H7_SPI_CFG1_UDRCFG_TX   (UINT32_C(2) << 9)

slave repeats its lastly transmitted data frame

Definition at line 2082 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_UDRDET

#define MCCI_STM32H7_SPI_CFG1_UDRDET   (UINT32_C(3) << 11)

detection of underrun condition at slave transmitter

Definition at line 2075 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_UDRDET_BEGIN

#define MCCI_STM32H7_SPI_CFG1_UDRDET_BEGIN   (UINT32_C(0) << 11)

underrun is detected at begin of data frame

Definition at line 2076 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_UDRDET_BEGIN_SS

#define MCCI_STM32H7_SPI_CFG1_UDRDET_BEGIN_SS   (UINT32_C(2) << 11)

underrun is detected at begin of active SS signal

Definition at line 2078 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG1_UDRDET_END

#define MCCI_STM32H7_SPI_CFG1_UDRDET_END   (UINT32_C(1) << 11)

underrun is detected at end of data frame

Definition at line 2077 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2

#define MCCI_STM32H7_SPI_CFG2   UINT32_C(0x0C)

offset to SPI configuration register 2

Definition at line 2020 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_AFCNTR

#define MCCI_STM32H7_SPI_CFG2_AFCNTR   (UINT32_C(1) << 31)

alternate function GPIOs control

Definition at line 2091 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_COMM

#define MCCI_STM32H7_SPI_CFG2_COMM   (UINT32_C(3) << 17)

SPI communication mode.

Definition at line 2102 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_COMM_FULL_DUPLEX

#define MCCI_STM32H7_SPI_CFG2_COMM_FULL_DUPLEX   (UINT32_C(0) << 17)

full-duplex

Definition at line 2103 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_COMM_HALF_DUPLEX

#define MCCI_STM32H7_SPI_CFG2_COMM_HALF_DUPLEX   (UINT32_C(3) << 17)

half-duplex

Definition at line 2106 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_COMM_SIMPLEX_RX

#define MCCI_STM32H7_SPI_CFG2_COMM_SIMPLEX_RX   (UINT32_C(2) << 17)

simplex receiver

Definition at line 2105 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_COMM_SIMPLEX_TX

#define MCCI_STM32H7_SPI_CFG2_COMM_SIMPLEX_TX   (UINT32_C(1) << 17)

simplex transmitter

Definition at line 2104 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_CPHA

#define MCCI_STM32H7_SPI_CFG2_CPHA   (UINT32_C(1) << 24)

clock phase

Definition at line 2098 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_CPOL

#define MCCI_STM32H7_SPI_CFG2_CPOL   (UINT32_C(1) << 25)

clock polarity

Definition at line 2097 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_IOSWP

#define MCCI_STM32H7_SPI_CFG2_IOSWP   (UINT32_C(1) << 15)

swap functionality of MISO and MOSI pins

Definition at line 2108 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_LSBFRST

#define MCCI_STM32H7_SPI_CFG2_LSBFRST   (UINT32_C(1) << 23)

data frame format

Definition at line 2099 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_MASTER

#define MCCI_STM32H7_SPI_CFG2_MASTER   (UINT32_C(1) << 22)

SPI master.

Definition at line 2100 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_MIDI

#define MCCI_STM32H7_SPI_CFG2_MIDI   (UINT32_C(15) << 4)

master Inter-Data Idleness

Definition at line 2110 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_MIDI_N

#define MCCI_STM32H7_SPI_CFG2_MIDI_N (   n)    ((n) << 4)

n clock cycle period delay

Definition at line 2111 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_MSSI

#define MCCI_STM32H7_SPI_CFG2_MSSI   (UINT32_C(15) << 0)

master SS idleness

Definition at line 2112 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_MSSI_N

#define MCCI_STM32H7_SPI_CFG2_MSSI_N (   n)    ((n) << 0)

n clock cycle period delay added

Definition at line 2113 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_RSV16

#define MCCI_STM32H7_SPI_CFG2_RSV16   (UINT32_C(1) << 16)

reserved, don't change

Definition at line 2107 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_RSV27

#define MCCI_STM32H7_SPI_CFG2_RSV27   (UINT32_C(1) << 27)

reserved, don't change

Definition at line 2095 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_RSV8

#define MCCI_STM32H7_SPI_CFG2_RSV8   (UINT32_C(0x7F) << 8)

reserved, don't change

Definition at line 2109 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_SP

#define MCCI_STM32H7_SPI_CFG2_SP   (UINT32_C(7) << 19)

Serial protocol.

Definition at line 2101 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_SSIOP

#define MCCI_STM32H7_SPI_CFG2_SSIOP   (UINT32_C(1) << 28)

SS input/output polarity.

Definition at line 2094 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_SSM

#define MCCI_STM32H7_SPI_CFG2_SSM   (UINT32_C(1) << 26)

software management of SS signal input

Definition at line 2096 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_SSOE

#define MCCI_STM32H7_SPI_CFG2_SSOE   (UINT32_C(1) << 29)

SS output enable.

Definition at line 2093 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CFG2_SSOM

#define MCCI_STM32H7_SPI_CFG2_SSOM   (UINT32_C(1) << 30)

SS output management in master mode.

Definition at line 2092 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CR1

#define MCCI_STM32H7_SPI_CR1   UINT32_C(0x00)

offset to SPI control register 1

Definition at line 2017 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CR1_CRC33_17

#define MCCI_STM32H7_SPI_CR1_CRC33_17   (UINT32_C(1) << 13)

32-bit CRC polynomial configuration

Definition at line 2039 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CR1_CSTART

#define MCCI_STM32H7_SPI_CR1_CSTART   (UINT32_C(1) << 9)

master transfer start

Definition at line 2043 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CR1_CSUSP

#define MCCI_STM32H7_SPI_CR1_CSUSP   (UINT32_C(1) << 10)

master suspend request

Definition at line 2042 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CR1_HDDIR

#define MCCI_STM32H7_SPI_CR1_HDDIR   (UINT32_C(1) << 11)

Rx/Tx direction at Half-duplex mode.

Definition at line 2041 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CR1_IOLOCK

#define MCCI_STM32H7_SPI_CR1_IOLOCK   (UINT32_C(1) << 16)

locking the AF configuration of associated IOs

Definition at line 2036 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CR1_MASRX

#define MCCI_STM32H7_SPI_CR1_MASRX   (UINT32_C(1) << 8)

master automatic SUSP in Receive mode

Definition at line 2044 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CR1_RCRCINI

#define MCCI_STM32H7_SPI_CR1_RCRCINI   (UINT32_C(1) << 14)

CRC calculation initialization pattern control for receiver.

Definition at line 2038 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CR1_RSV1

#define MCCI_STM32H7_SPI_CR1_RSV1   (UINT32_C(0x7F) << 1)

reserved, don't change

Definition at line 2045 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CR1_RSV17

#define MCCI_STM32H7_SPI_CR1_RSV17   UINT32_C(0xFFFE0000)

reserved, don't change

Definition at line 2035 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CR1_SPE

#define MCCI_STM32H7_SPI_CR1_SPE   (UINT32_C(1) << 0)

serial peripheral enable

Definition at line 2046 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CR1_SSI

#define MCCI_STM32H7_SPI_CR1_SSI   (UINT32_C(1) << 12)

internal SS signal input level

Definition at line 2040 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CR1_TCRCINI

#define MCCI_STM32H7_SPI_CR1_TCRCINI   (UINT32_C(1) << 15)

CRC calculation initialization pattern control for transmitter.

Definition at line 2037 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CR2

#define MCCI_STM32H7_SPI_CR2   UINT32_C(0x04)

offset to SPI control register 2

Definition at line 2018 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CR2_TSER

#define MCCI_STM32H7_SPI_CR2_TSER   UINT32_C(0xFFFF0000)

number of data transfer extension to be reload into TSIZE

Definition at line 2051 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CR2_TSIZE

#define MCCI_STM32H7_SPI_CR2_TSIZE   UINT32_C(0x0000FFFF)

number of data at current transfer

Definition at line 2052 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_CRCPOLY

#define MCCI_STM32H7_SPI_CRCPOLY   UINT32_C(0x40)

offset to SPI CRC polynomial

Definition at line 2026 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR

#define MCCI_STM32H7_SPI_I2SCFGR   UINT32_C(0x50)

offset to SPI I2S config register

Definition at line 2030 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_CHLEN

#define MCCI_STM32H7_SPI_I2SCFGR_CHLEN   (UINT32_C(1) << 10)

channel length

Definition at line 2180 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_CKPOL

#define MCCI_STM32H7_SPI_I2SCFGR_CKPOL   (UINT32_C(1) << 11)

serial audio clock polarity

Definition at line 2179 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_DATFMT

#define MCCI_STM32H7_SPI_I2SCFGR_DATFMT   (UINT32_C(1) << 14)

data format

Definition at line 2176 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_DATLEN

#define MCCI_STM32H7_SPI_I2SCFGR_DATLEN   (UINT32_C(3) << 8)

data length to be transferred

Definition at line 2181 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_DATLEN_16

#define MCCI_STM32H7_SPI_I2SCFGR_DATLEN_16   (UINT32_C(0) << 8)

16 bit

Definition at line 2182 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_DATLEN_24

#define MCCI_STM32H7_SPI_I2SCFGR_DATLEN_24   (UINT32_C(1) << 8)

24 bit

Definition at line 2183 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_DATLEN_32

#define MCCI_STM32H7_SPI_I2SCFGR_DATLEN_32   (UINT32_C(2) << 8)

32 bit

Definition at line 2184 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_FIXCH

#define MCCI_STM32H7_SPI_I2SCFGR_FIXCH   (UINT32_C(1) << 12)

fixed channel length in slave

Definition at line 2178 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_I2SCFG

#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG   (UINT32_C(7) << 1)

I2S configuration mode.

Definition at line 2192 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_MFD

#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_MFD   (UINT32_C(5) << 1)

master - full duplex

Definition at line 2198 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_MRX

#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_MRX   (UINT32_C(3) << 1)

master - receive

Definition at line 2196 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_MTX

#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_MTX   (UINT32_C(2) << 1)

master - transmit

Definition at line 2195 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_SFD

#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_SFD   (UINT32_C(4) << 1)

slave - full duplex

Definition at line 2197 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_SRX

#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_SRX   (UINT32_C(1) << 1)

slave - receive

Definition at line 2194 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_STX

#define MCCI_STM32H7_SPI_I2SCFGR_I2SCFG_STX   (UINT32_C(0) << 1)

slave - transmit

Definition at line 2193 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_I2SDIV

#define MCCI_STM32H7_SPI_I2SCFGR_I2SDIV   (UINT32_C(0xFF) << 16)

I2S linear prescaler.

Definition at line 2173 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_I2SDIV_N

#define MCCI_STM32H7_SPI_I2SCFGR_I2SDIV_N (   n)    ((n) << 16)

Definition at line 2174 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_I2SMOD

#define MCCI_STM32H7_SPI_I2SCFGR_I2SMOD   (UINT32_C(1) << 0)

I2S mode selection.

Definition at line 2199 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_I2SSTD

#define MCCI_STM32H7_SPI_I2SCFGR_I2SSTD   (UINT32_C(3) << 4)

I2S standard selection.

Definition at line 2187 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_I2SSTD_LSB

#define MCCI_STM32H7_SPI_I2SCFGR_I2SSTD_LSB   (UINT32_C(2) << 4)

LSB justified standard.

Definition at line 2190 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_I2SSTD_MSB

#define MCCI_STM32H7_SPI_I2SCFGR_I2SSTD_MSB   (UINT32_C(1) << 4)

MSB justified standard.

Definition at line 2189 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_I2SSTD_PCM

#define MCCI_STM32H7_SPI_I2SCFGR_I2SSTD_PCM   (UINT32_C(3) << 4)

PCM standard.

Definition at line 2191 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_I2SSTD_PHILIPS

#define MCCI_STM32H7_SPI_I2SCFGR_I2SSTD_PHILIPS   (UINT32_C(0) << 4)

I2S Philips standard.

Definition at line 2188 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_MCKOE

#define MCCI_STM32H7_SPI_I2SCFGR_MCKOE   (UINT32_C(1) << 25)

master clock output enable

Definition at line 2171 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_ODD

#define MCCI_STM32H7_SPI_I2SCFGR_ODD   (UINT32_C(1) << 24)

odd factor for the prescaler

Definition at line 2172 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_PCMSYNC

#define MCCI_STM32H7_SPI_I2SCFGR_PCMSYNC   (UINT32_C(1) << 7)

PCM frame synchronization.

Definition at line 2185 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_RSV15

#define MCCI_STM32H7_SPI_I2SCFGR_RSV15   (UINT32_C(1) << 15)

reserved (do not change)

Definition at line 2175 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_RSV26

#define MCCI_STM32H7_SPI_I2SCFGR_RSV26   (UINT32_C(0x3F) << 26)

reserved (do not change)

Definition at line 2170 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_RSV6

#define MCCI_STM32H7_SPI_I2SCFGR_RSV6   (UINT32_C(1) << 6)

reserved (do not change)

Definition at line 2186 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_I2SCFGR_WSINV

#define MCCI_STM32H7_SPI_I2SCFGR_WSINV   (UINT32_C(1) << 13)

Word select inversion.

Definition at line 2177 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IER

#define MCCI_STM32H7_SPI_IER   UINT32_C(0x10)

offset to SPI interrupt enable register

Definition at line 2021 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IER_CRCEIE

#define MCCI_STM32H7_SPI_IER_CRCEIE   (UINT32_C(1) << 7)

CRC error interrupt enable.

Definition at line 2122 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IER_DXPIE

#define MCCI_STM32H7_SPI_IER_DXPIE   (UINT32_C(1) << 2)

DXP interrupt enabled.

Definition at line 2127 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IER_EOTIE

#define MCCI_STM32H7_SPI_IER_EOTIE   (UINT32_C(1) << 3)

EOT, SUSP and TXC interrupt enable.

Definition at line 2126 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IER_MODFIE

#define MCCI_STM32H7_SPI_IER_MODFIE   (UINT32_C(1) << 9)

mode fault interrupt enable

Definition at line 2120 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IER_OVRIE

#define MCCI_STM32H7_SPI_IER_OVRIE   (UINT32_C(1) << 6)

OVR interrupt enable.

Definition at line 2123 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IER_RSV11

#define MCCI_STM32H7_SPI_IER_RSV11   UINT32_C(0xFFFFFF80)

reserved, don't change

Definition at line 2118 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IER_RXPIE

#define MCCI_STM32H7_SPI_IER_RXPIE   (UINT32_C(1) << 0)

RXP Interrupt Enable.

Definition at line 2129 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IER_TIFREIE

#define MCCI_STM32H7_SPI_IER_TIFREIE   (UINT32_C(1) << 8)

TIFRE interrupt enable.

Definition at line 2121 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IER_TSERFIE

#define MCCI_STM32H7_SPI_IER_TSERFIE   (UINT32_C(1) << 10)

additional number of transactions reload interrupt enable

Definition at line 2119 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IER_TXPIE

#define MCCI_STM32H7_SPI_IER_TXPIE   (UINT32_C(1) << 1)

TXP interrupt enable.

Definition at line 2128 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IER_TXTFIE

#define MCCI_STM32H7_SPI_IER_TXTFIE   (UINT32_C(1) << 4)

TXTFIE interrupt enable.

Definition at line 2125 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IER_UDRIE

#define MCCI_STM32H7_SPI_IER_UDRIE   (UINT32_C(1) << 5)

UDR interrupt enable.

Definition at line 2124 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IFCR

#define MCCI_STM32H7_SPI_IFCR   UINT32_C(0x18)

offset to SPI interrupt/status flags clear register

Definition at line 2023 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IFCR_CRCEC

#define MCCI_STM32H7_SPI_IFCR_CRCEC   (UINT32_C(1) << 7)

CRC error flag clear.

Definition at line 2160 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IFCR_EOTC

#define MCCI_STM32H7_SPI_IFCR_EOTC   (UINT32_C(1) << 3)

EOT, SUSP and TXC flag clear.

Definition at line 2164 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IFCR_MODFC

#define MCCI_STM32H7_SPI_IFCR_MODFC   (UINT32_C(1) << 9)

mode fault flag clear

Definition at line 2158 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IFCR_OVRC

#define MCCI_STM32H7_SPI_IFCR_OVRC   (UINT32_C(1) << 6)

OVR flag clear.

Definition at line 2161 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IFCR_RSV0

#define MCCI_STM32H7_SPI_IFCR_RSV0   (UINT32_C(7) << 0)

reserved, don't change

Definition at line 2165 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IFCR_RSV12

#define MCCI_STM32H7_SPI_IFCR_RSV12   UINT32_C(0xFFFFFF00)

reserved, don't change

Definition at line 2155 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IFCR_SUSPC

#define MCCI_STM32H7_SPI_IFCR_SUSPC   (UINT32_C(1) << 11)

SUSPend flag clear.

Definition at line 2156 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IFCR_TIFREC

#define MCCI_STM32H7_SPI_IFCR_TIFREC   (UINT32_C(1) << 8)

TIFRE flag clear.

Definition at line 2159 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IFCR_TSERFC

#define MCCI_STM32H7_SPI_IFCR_TSERFC   (UINT32_C(1) << 10)

additional number of transactions reload flag clear

Definition at line 2157 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IFCR_TXTFC

#define MCCI_STM32H7_SPI_IFCR_TXTFC   (UINT32_C(1) << 4)

TXTFC flag clear.

Definition at line 2163 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_IFCR_UDRC

#define MCCI_STM32H7_SPI_IFCR_UDRC   (UINT32_C(1) << 5)

UDR flag clear.

Definition at line 2162 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_RXCRC

#define MCCI_STM32H7_SPI_RXCRC   UINT32_C(0x48)

offset to SPI receive CRC

Definition at line 2028 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_RXDR

#define MCCI_STM32H7_SPI_RXDR   UINT32_C(0x30)

offset to SPI receive data register

Definition at line 2025 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_SR

#define MCCI_STM32H7_SPI_SR   UINT32_C(0x14)

offset to SPI status register

Definition at line 2022 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_SR_CRCE

#define MCCI_STM32H7_SPI_SR_CRCE   (UINT32_C(1) << 7)

CRC error.

Definition at line 2143 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_SR_CTSIZE

#define MCCI_STM32H7_SPI_SR_CTSIZE   UINT32_C(0xFFFF0000)

number of data frames remaining in current TSIZE session

Definition at line 2134 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_SR_DXP

#define MCCI_STM32H7_SPI_SR_DXP   (UINT32_C(1) << 2)

duplex packet

Definition at line 2148 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_SR_EOT

#define MCCI_STM32H7_SPI_SR_EOT   (UINT32_C(1) << 3)

end of transfer

Definition at line 2147 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_SR_MODF

#define MCCI_STM32H7_SPI_SR_MODF   (UINT32_C(1) << 9)

mode fault

Definition at line 2141 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_SR_OVR

#define MCCI_STM32H7_SPI_SR_OVR   (UINT32_C(1) << 6)

overrun

Definition at line 2144 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_SR_RXP

#define MCCI_STM32H7_SPI_SR_RXP   (UINT32_C(1) << 0)

Rx-packet available.

Definition at line 2150 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_SR_RXPLVL

#define MCCI_STM32H7_SPI_SR_RXPLVL   (UINT32_C(3) << 13)

RxFIFO packing leveL.

Definition at line 2136 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_SR_RXPLVL_N

#define MCCI_STM32H7_SPI_SR_RXPLVL_N (   n)    ((n) << 13)

n frame is available

Definition at line 2137 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_SR_RXWNE

#define MCCI_STM32H7_SPI_SR_RXWNE   (UINT32_C(1) << 15)

RxFIFO word not empty.

Definition at line 2135 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_SR_SUSP

#define MCCI_STM32H7_SPI_SR_SUSP   (UINT32_C(1) << 11)

suspension status

Definition at line 2139 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_SR_TIFRE

#define MCCI_STM32H7_SPI_SR_TIFRE   (UINT32_C(1) << 8)

TI frame format error.

Definition at line 2142 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_SR_TSERF

#define MCCI_STM32H7_SPI_SR_TSERF   (UINT32_C(1) << 10)

additional number of SPI data to be transacted was reload

Definition at line 2140 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_SR_TXC

#define MCCI_STM32H7_SPI_SR_TXC   (UINT32_C(1) << 12)

TxFIFO transmission complete.

Definition at line 2138 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_SR_TXP

#define MCCI_STM32H7_SPI_SR_TXP   (UINT32_C(1) << 1)

Tx-packet space available.

Definition at line 2149 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_SR_TXTF

#define MCCI_STM32H7_SPI_SR_TXTF   (UINT32_C(1) << 4)

transmission transfer filled

Definition at line 2146 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_SR_UDR

#define MCCI_STM32H7_SPI_SR_UDR   (UINT32_C(1) << 5)

underrun at slave transmission mode

Definition at line 2145 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_TXCRC

#define MCCI_STM32H7_SPI_TXCRC   UINT32_C(0x44)

offset to SPI transmit CRC

Definition at line 2027 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_TXDR

#define MCCI_STM32H7_SPI_TXDR   UINT32_C(0x20)

offset to SPI transmit data register

Definition at line 2024 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_SPI_UDRDR

#define MCCI_STM32H7_SPI_UDRDR   UINT32_C(0x4C)

offset to SPI underrun data CRC

Definition at line 2029 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF1

#define MCCI_STM32H7_TIM_AF1   UINT32_C(0x60)

offset to TIM Alternate function option register 1

Definition at line 2834 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF1_BKCMP1E

#define MCCI_STM32H7_TIM_AF1_BKCMP1E   (UINT32_C(1) << 1)

BRK COMP1 enable.

Definition at line 3007 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF1_BKCMP1P

#define MCCI_STM32H7_TIM_AF1_BKCMP1P   (UINT32_C(1) << 10)

BRK COMP1 input polarity.

Definition at line 3002 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF1_BKCMP2E

#define MCCI_STM32H7_TIM_AF1_BKCMP2E   (UINT32_C(1) << 2)

BRK COMP2 enable.

Definition at line 3006 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF1_BKCMP2P

#define MCCI_STM32H7_TIM_AF1_BKCMP2P   (UINT32_C(1) << 11)

BRK COMP2 input polarity.

Definition at line 3001 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF1_BKDF1BK2E

#define MCCI_STM32H7_TIM_AF1_BKDF1BK2E   (UINT32_C(1) << 8)

BRK dfsdm1_break[2] enable.

Definition at line 3004 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF1_BKINE

#define MCCI_STM32H7_TIM_AF1_BKINE   (UINT32_C(1) << 0)

BRK BKIN input enable.

Definition at line 3008 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF1_BKINP

#define MCCI_STM32H7_TIM_AF1_BKINP   (UINT32_C(1) << 9)

BRK BKIN input polarity.

Definition at line 3003 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF1_ETRSEL

#define MCCI_STM32H7_TIM_AF1_ETRSEL   (UINT32_C(0xF) << 14)

ETR source selection.

Definition at line 2998 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF1_ETRSEL_N

#define MCCI_STM32H7_TIM_AF1_ETRSEL_N (   n)    ((n) << 14)

Definition at line 2999 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF1_RSV12

#define MCCI_STM32H7_TIM_AF1_RSV12   (UINT32_C(3) << 12)

reserved, don't change

Definition at line 3000 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF1_RSV18

#define MCCI_STM32H7_TIM_AF1_RSV18   UINT32_C(0xFFFC0000)

reserved, don't change

Definition at line 2997 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF1_RSV3

#define MCCI_STM32H7_TIM_AF1_RSV3   (UINT32_C(0x1F) << 3)

reserved, don't change

Definition at line 3005 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF2

#define MCCI_STM32H7_TIM_AF2   UINT32_C(0x64)

offset to TIM Alternate function option register 2

Definition at line 2835 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF2_BKCMP1E

#define MCCI_STM32H7_TIM_AF2_BKCMP1E   (UINT32_C(1) << 1)

BRK COMP1 enable.

Definition at line 3020 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF2_BKCMP1P

#define MCCI_STM32H7_TIM_AF2_BKCMP1P   (UINT32_C(1) << 10)

BRK COMP1 input polarity.

Definition at line 3015 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF2_BKCMP2E

#define MCCI_STM32H7_TIM_AF2_BKCMP2E   (UINT32_C(1) << 2)

BRK COMP2 enable.

Definition at line 3019 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF2_BKCMP2P

#define MCCI_STM32H7_TIM_AF2_BKCMP2P   (UINT32_C(1) << 11)

BRK COMP2 input polarity.

Definition at line 3014 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF2_BKDF1BK2E

#define MCCI_STM32H7_TIM_AF2_BKDF1BK2E   (UINT32_C(1) << 8)

BRK dfsdm1_break[2] enable.

Definition at line 3017 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF2_BKINE

#define MCCI_STM32H7_TIM_AF2_BKINE   (UINT32_C(1) << 0)

BRK BKIN input enable.

Definition at line 3021 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF2_BKINP

#define MCCI_STM32H7_TIM_AF2_BKINP   (UINT32_C(1) << 9)

BRK BKIN input polarity.

Definition at line 3016 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF2_RSV12

#define MCCI_STM32H7_TIM_AF2_RSV12   UINT32_C(0xFFFFF000)

reserved, don't change

Definition at line 3013 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_AF2_RSV3

#define MCCI_STM32H7_TIM_AF2_RSV3   (UINT32_C(0x1F) << 3)

reserved, don't change

Definition at line 3018 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_ARR

#define MCCI_STM32H7_TIM_ARR   UINT32_C(0x2C)

offset to TIM auto-reload register

Definition at line 2822 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_ARR_ARR

#define MCCI_STM32H7_TIM_ARR_ARR   (UINT32_C(0xFFFF) << 0)

Auto-reload value.

Definition at line 2980 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_ARR_RSV16

#define MCCI_STM32H7_TIM_ARR_RSV16   UINT32_C(0xFFFF0000)

reserved, don't change

Definition at line 2979 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_BDTR

#define MCCI_STM32H7_TIM_BDTR   UINT32_C(0x44)

offset to TIM break and dead-time register

Definition at line 2828 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CCER

#define MCCI_STM32H7_TIM_CCER   UINT32_C(0x20)

offset to TIM capture/compare enable register

Definition at line 2819 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CCMR1

#define MCCI_STM32H7_TIM_CCMR1   UINT32_C(0x18)

offset to TIM capture/compare mode register 1

Definition at line 2817 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CCMR2

#define MCCI_STM32H7_TIM_CCMR2   UINT32_C(0x1C)

offset to TIM capture/compare mode register 2

Definition at line 2818 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CCMR3

#define MCCI_STM32H7_TIM_CCMR3   UINT32_C(0x54)

offset to TIM capture/compare mode register 3

Definition at line 2831 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CCR1

#define MCCI_STM32H7_TIM_CCR1   UINT32_C(0x34)

offset to TIM capture/compare register 1

Definition at line 2824 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CCR2

#define MCCI_STM32H7_TIM_CCR2   UINT32_C(0x38)

offset to TIM capture/compare register 2

Definition at line 2825 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CCR3

#define MCCI_STM32H7_TIM_CCR3   UINT32_C(0x3C)

offset to TIM capture/compare register 3

Definition at line 2826 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CCR4

#define MCCI_STM32H7_TIM_CCR4   UINT32_C(0x40)

offset to TIM capture/compare register 4

Definition at line 2827 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CCR5

#define MCCI_STM32H7_TIM_CCR5   UINT32_C(0x58)

offset to TIM capture/compare register 5

Definition at line 2832 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CCR6

#define MCCI_STM32H7_TIM_CCR6   UINT32_C(0x5C)

offset to TIM capture/compare register 6

Definition at line 2833 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CCR_CCR

#define MCCI_STM32H7_TIM_CCR_CCR   (UINT32_C(0xFFFF) << 0)

Capture/Compare value.

Definition at line 2992 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CCR_RSV16

#define MCCI_STM32H7_TIM_CCR_RSV16   UINT32_C(0xFFFF0000)

reserved, don't change

Definition at line 2991 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CNT

#define MCCI_STM32H7_TIM_CNT   UINT32_C(0x24)

offset to TIM counter register

Definition at line 2820 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CNT_CNT

#define MCCI_STM32H7_TIM_CNT_CNT   (UINT32_C(0xFFFF) << 0)

Counter value.

Definition at line 2968 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CNT_RSV16

#define MCCI_STM32H7_TIM_CNT_RSV16   UINT32_C(0x7FFF0000)

reserved, don't change

Definition at line 2967 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CNT_UIFCPY

#define MCCI_STM32H7_TIM_CNT_UIFCPY   (UINT32_C(1) << 8)

UIF copy.

Definition at line 2966 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR1

#define MCCI_STM32H7_TIM_CR1   UINT32_C(0x00)

offset to TIM control register 1

Definition at line 2811 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR1_ARPE

#define MCCI_STM32H7_TIM_CR1_ARPE   (UINT32_C(1) << 7)

Auto-reload preload enable.

Definition at line 2846 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR1_CEN

#define MCCI_STM32H7_TIM_CR1_CEN   (UINT32_C(1) << 0)

Counter enable.

Definition at line 2853 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR1_CKD

#define MCCI_STM32H7_TIM_CR1_CKD   (UINT32_C(0x3) << 8)

Clock division.

Definition at line 2844 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR1_CKD_N

#define MCCI_STM32H7_TIM_CR1_CKD_N (   n)    ((n) << 8)

Definition at line 2845 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR1_CMS

#define MCCI_STM32H7_TIM_CR1_CMS   (UINT32_C(0x3) << 5)

Center-aligned mode selection.

Definition at line 2847 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR1_CMS_N

#define MCCI_STM32H7_TIM_CR1_CMS_N (   n)    ((n) << 5)

Definition at line 2848 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR1_DIR

#define MCCI_STM32H7_TIM_CR1_DIR   (UINT32_C(1) << 4)

Direction.

Definition at line 2849 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR1_OPM

#define MCCI_STM32H7_TIM_CR1_OPM   (UINT32_C(1) << 3)

One pulse mode.

Definition at line 2850 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR1_RSV10

#define MCCI_STM32H7_TIM_CR1_RSV10   (UINT32_C(1) << 10)

reserved, don't change

Definition at line 2843 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR1_RSV12

#define MCCI_STM32H7_TIM_CR1_RSV12   UINT32_C(0xFFFFF000)

reserved, don't change

Definition at line 2841 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR1_UDIS

#define MCCI_STM32H7_TIM_CR1_UDIS   (UINT32_C(1) << 1)

Update disable.

Definition at line 2852 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR1_UIFREMAP

#define MCCI_STM32H7_TIM_CR1_UIFREMAP   (UINT32_C(1) << 11)

UIF status bit remapping.

Definition at line 2842 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR1_URS

#define MCCI_STM32H7_TIM_CR1_URS   (UINT32_C(1) << 2)

Update request source.

Definition at line 2851 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2

#define MCCI_STM32H7_TIM_CR2   UINT32_C(0x04)

offset to TIM control register 2

Definition at line 2812 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_CCDS

#define MCCI_STM32H7_TIM_CR2_CCDS   (UINT32_C(1) << 3)

Capture/compare DMA selection.

Definition at line 2876 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_CCPC

#define MCCI_STM32H7_TIM_CR2_CCPC   (UINT32_C(1) << 0)

Capture/compare preloaded control.

Definition at line 2879 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_CCUS

#define MCCI_STM32H7_TIM_CR2_CCUS   (UINT32_C(1) << 2)

Capture/compare control update selection.

Definition at line 2877 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_MMS

#define MCCI_STM32H7_TIM_CR2_MMS   (UINT32_C(0x7) << 4)

Master mode selection.

Definition at line 2874 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_MMS2

#define MCCI_STM32H7_TIM_CR2_MMS2   (UINT32_C(0xF) << 20)

Master mode selection 2.

Definition at line 2859 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_MMS2_N

#define MCCI_STM32H7_TIM_CR2_MMS2_N (   n)    ((n) << 20)

Definition at line 2860 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_MMS_N

#define MCCI_STM32H7_TIM_CR2_MMS_N (   n)    ((n) << 4)

Definition at line 2875 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_OIS1

#define MCCI_STM32H7_TIM_CR2_OIS1   (UINT32_C(1) << 8)

Output Idle state 1 (OC1 output)

Definition at line 2872 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_OIS1N

#define MCCI_STM32H7_TIM_CR2_OIS1N   (UINT32_C(1) << 9)

Output Idle state 1 (OC1N output)

Definition at line 2871 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_OIS2

#define MCCI_STM32H7_TIM_CR2_OIS2   (UINT32_C(1) << 10)

Output Idle state 2 (OC2 output)

Definition at line 2870 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_OIS2N

#define MCCI_STM32H7_TIM_CR2_OIS2N   (UINT32_C(1) << 11)

Output Idle state 2 (OC2N output)

Definition at line 2869 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_OIS3

#define MCCI_STM32H7_TIM_CR2_OIS3   (UINT32_C(1) << 12)

Output Idle state 3 (OC3 output)

Definition at line 2868 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_OIS3N

#define MCCI_STM32H7_TIM_CR2_OIS3N   (UINT32_C(1) << 13)

Output Idle state 3 (OC3N output)

Definition at line 2867 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_OIS4

#define MCCI_STM32H7_TIM_CR2_OIS4   (UINT32_C(1) << 14)

Output Idle state 4 (OC4 output)

Definition at line 2866 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_OIS5

#define MCCI_STM32H7_TIM_CR2_OIS5   (UINT32_C(1) << 16)

Output Idle state 5 (OC5 output)

Definition at line 2864 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_OIS6

#define MCCI_STM32H7_TIM_CR2_OIS6   (UINT32_C(1) << 18)

Output Idle state 6 (OC6 output)

Definition at line 2862 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_RSV1

#define MCCI_STM32H7_TIM_CR2_RSV1   (UINT32_C(1) << 1)

reserved, don't change

Definition at line 2878 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_RSV15

#define MCCI_STM32H7_TIM_CR2_RSV15   (UINT32_C(1) << 15)

reserved, don't change

Definition at line 2865 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_RSV17

#define MCCI_STM32H7_TIM_CR2_RSV17   (UINT32_C(1) << 17)

reserved, don't change

Definition at line 2863 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_RSV19

#define MCCI_STM32H7_TIM_CR2_RSV19   (UINT32_C(1) << 19)

reserved, don't change

Definition at line 2861 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_RSV24

#define MCCI_STM32H7_TIM_CR2_RSV24   UINT32_C(0xFF000000)

reserved, don't change

Definition at line 2858 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_CR2_TI1S

#define MCCI_STM32H7_TIM_CR2_TI1S   (UINT32_C(1) << 7)

TI1 selection.

Definition at line 2873 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_DCR

#define MCCI_STM32H7_TIM_DCR   UINT32_C(0x48)

offset to TIM DMA control register

Definition at line 2829 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_DIER

#define MCCI_STM32H7_TIM_DIER   UINT32_C(0x0C)

offset to TIM DMA/interrupt enable register

Definition at line 2814 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_DIER_BIE

#define MCCI_STM32H7_TIM_DIER_BIE   (UINT32_C(1) << 7)

Break interrupt enable.

Definition at line 2918 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_DIER_CC1DE

#define MCCI_STM32H7_TIM_DIER_CC1DE   (UINT32_C(1) << 9)

Capture/Compare 1 DMA request enable.

Definition at line 2916 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_DIER_CC1IE

#define MCCI_STM32H7_TIM_DIER_CC1IE   (UINT32_C(1) << 1)

Capture/Compare 1 interrupt enable.

Definition at line 2924 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_DIER_CC2DE

#define MCCI_STM32H7_TIM_DIER_CC2DE   (UINT32_C(1) << 10)

Capture/Compare 2 DMA request enable.

Definition at line 2915 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_DIER_CC2IE

#define MCCI_STM32H7_TIM_DIER_CC2IE   (UINT32_C(1) << 2)

Capture/Compare 2 interrupt enable.

Definition at line 2923 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_DIER_CC3DE

#define MCCI_STM32H7_TIM_DIER_CC3DE   (UINT32_C(1) << 11)

Capture/Compare 3 DMA request enable.

Definition at line 2914 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_DIER_CC3IE

#define MCCI_STM32H7_TIM_DIER_CC3IE   (UINT32_C(1) << 3)

Capture/Compare 3 interrupt enable.

Definition at line 2922 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_DIER_CC4DE

#define MCCI_STM32H7_TIM_DIER_CC4DE   (UINT32_C(1) << 12)

Capture/Compare 4 DMA request enable.

Definition at line 2913 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_DIER_CC4IE

#define MCCI_STM32H7_TIM_DIER_CC4IE   (UINT32_C(1) << 4)

Capture/Compare 4 interrupt enable.

Definition at line 2921 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_DIER_COMDE

#define MCCI_STM32H7_TIM_DIER_COMDE   (UINT32_C(1) << 13)

COM DMA request enable.

Definition at line 2912 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_DIER_COMIE

#define MCCI_STM32H7_TIM_DIER_COMIE   (UINT32_C(1) << 5)

COM interrupt enable.

Definition at line 2920 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_DIER_RSV15

#define MCCI_STM32H7_TIM_DIER_RSV15   UINT32_C(0xFFFF8000)

reserved, don't change

Definition at line 2910 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_DIER_TDE

#define MCCI_STM32H7_TIM_DIER_TDE   (UINT32_C(1) << 14)

Trigger DMA request enable.

Definition at line 2911 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_DIER_TIE

#define MCCI_STM32H7_TIM_DIER_TIE   (UINT32_C(1) << 6)

Trigger interrupt enable.

Definition at line 2919 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_DIER_UDE

#define MCCI_STM32H7_TIM_DIER_UDE   (UINT32_C(1) << 8)

Update DMA request enable.

Definition at line 2917 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_DIER_UIE

#define MCCI_STM32H7_TIM_DIER_UIE   (UINT32_C(1) << 0)

Update interrupt enable.

Definition at line 2925 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_DMAR

#define MCCI_STM32H7_TIM_DMAR   UINT32_C(0x4C)

offset to TIM DMA address register

Definition at line 2830 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_EGR

#define MCCI_STM32H7_TIM_EGR   UINT32_C(0x14)

offset to TIM event generation register

Definition at line 2816 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_EGR_B2G

#define MCCI_STM32H7_TIM_EGR_B2G   (UINT32_C(1) << 8)

Break 2 generation.

Definition at line 2953 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_EGR_BG

#define MCCI_STM32H7_TIM_EGR_BG   (UINT32_C(1) << 7)

Break generation.

Definition at line 2954 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_EGR_CC1G

#define MCCI_STM32H7_TIM_EGR_CC1G   (UINT32_C(1) << 1)

Capture/Compare 1 generation.

Definition at line 2960 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_EGR_CC2G

#define MCCI_STM32H7_TIM_EGR_CC2G   (UINT32_C(1) << 2)

Capture/Compare 2 generation.

Definition at line 2959 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_EGR_CC3G

#define MCCI_STM32H7_TIM_EGR_CC3G   (UINT32_C(1) << 3)

Capture/Compare 3 generation.

Definition at line 2958 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_EGR_CC4G

#define MCCI_STM32H7_TIM_EGR_CC4G   (UINT32_C(1) << 4)

Capture/Compare 4 generation.

Definition at line 2957 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_EGR_COMG

#define MCCI_STM32H7_TIM_EGR_COMG   (UINT32_C(1) << 5)

COM generation.

Definition at line 2956 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_EGR_RSV8

#define MCCI_STM32H7_TIM_EGR_RSV8   UINT32_C(0xFFFFFE00)

reserved, don't change

Definition at line 2952 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_EGR_TG

#define MCCI_STM32H7_TIM_EGR_TG   (UINT32_C(1) << 6)

Trigger generation.

Definition at line 2955 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_EGR_UG

#define MCCI_STM32H7_TIM_EGR_UG   (UINT32_C(1) << 0)

Update generation.

Definition at line 2961 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_PSC

#define MCCI_STM32H7_TIM_PSC   UINT32_C(0x28)

offset to TIM prescaler register

Definition at line 2821 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_PSC_PSC

#define MCCI_STM32H7_TIM_PSC_PSC   (UINT32_C(0xFFFF) << 0)

Prescaler value.

Definition at line 2974 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_PSC_RSV16

#define MCCI_STM32H7_TIM_PSC_RSV16   UINT32_C(0xFFFF0000)

reserved, don't change

Definition at line 2973 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_RCR

#define MCCI_STM32H7_TIM_RCR   UINT32_C(0x30)

offset to TIM repetition counter register

Definition at line 2823 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_RCR_REP

#define MCCI_STM32H7_TIM_RCR_REP   (UINT32_C(0xFFFF) << 0)

Repetition counter value.

Definition at line 2986 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_RCR_RSV16

#define MCCI_STM32H7_TIM_RCR_RSV16   UINT32_C(0xFFFF0000)

reserved, don't change

Definition at line 2985 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR

#define MCCI_STM32H7_TIM_SMCR   UINT32_C(0x08)

offset to TIM slave mode control register

Definition at line 2813 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_ECE

#define MCCI_STM32H7_TIM_SMCR_ECE   (UINT32_C(1) << 14)

External clock enable.

Definition at line 2890 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_ETF

#define MCCI_STM32H7_TIM_SMCR_ETF   (UINT32_C(0xF) << 8)

External trigger filter.

Definition at line 2893 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_ETF_N

#define MCCI_STM32H7_TIM_SMCR_ETF_N (   n)    ((n) << 8)

Definition at line 2894 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_ETP

#define MCCI_STM32H7_TIM_SMCR_ETP   (UINT32_C(1) << 15)

External trigger polarity.

Definition at line 2889 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_ETPS

#define MCCI_STM32H7_TIM_SMCR_ETPS   (UINT32_C(0x3) << 12)

External trigger prescaler.

Definition at line 2891 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_ETPS_N

#define MCCI_STM32H7_TIM_SMCR_ETPS_N (   n)    ((n) << 12)

Definition at line 2892 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_MSM

#define MCCI_STM32H7_TIM_SMCR_MSM   (UINT32_C(1) << 7)

Master/slave mode.

Definition at line 2895 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_RSV17

#define MCCI_STM32H7_TIM_SMCR_RSV17   (UINT32_C(7) << 17)

reserved, don't change

Definition at line 2887 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_RSV22

#define MCCI_STM32H7_TIM_SMCR_RSV22   UINT32_C(0xFFC00000)

reserved, don't change

Definition at line 2884 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_RSV3

#define MCCI_STM32H7_TIM_SMCR_RSV3   (UINT32_C(1) << 3)

reserved, don't change

Definition at line 2898 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_SMS

#define MCCI_STM32H7_TIM_SMCR_SMS   (MCCI_STM32H7_TIM_SMCR_SMS3 | MCCI_STM32H7_TIM_SMCR_SMS0)

Trigger selection.

Definition at line 2904 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_SMS0

#define MCCI_STM32H7_TIM_SMCR_SMS0   (UINT32_C(0x7) << 0)

Slave mode selection.

Definition at line 2899 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_SMS0_N

#define MCCI_STM32H7_TIM_SMCR_SMS0_N (   n)    ((n) << 0)

Definition at line 2900 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_SMS3

#define MCCI_STM32H7_TIM_SMCR_SMS3   (UINT32_C(1) << 16)

Slave mode selection.

Definition at line 2888 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_SMS_N

#define MCCI_STM32H7_TIM_SMCR_SMS_N (   n)    ((((n) >> 3) << 16) | MCCI_STM32H7_TIM_SMCR_SMS0_N((n) & UINT32_C(0x7)))

Definition at line 2905 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_TS

#define MCCI_STM32H7_TIM_SMCR_TS   (MCCI_STM32H7_TIM_SMCR_TS3 | MCCI_STM32H7_TIM_SMCR_TS0)

Trigger selection.

Definition at line 2902 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_TS0

#define MCCI_STM32H7_TIM_SMCR_TS0   (UINT32_C(0x7) << 4)

Trigger selection.

Definition at line 2896 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_TS0_N

#define MCCI_STM32H7_TIM_SMCR_TS0_N (   n)    ((n) << 4)

Definition at line 2897 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_TS3

#define MCCI_STM32H7_TIM_SMCR_TS3   (UINT32_C(0x3) << 20)

Trigger selection.

Definition at line 2885 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_TS3_N

#define MCCI_STM32H7_TIM_SMCR_TS3_N (   n)    ((n) << 20)

Definition at line 2886 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SMCR_TS_N

#define MCCI_STM32H7_TIM_SMCR_TS_N (   n)    (MCCI_STM32H7_TIM_SMCR_TS3_N((n) >> 3) | MCCI_STM32H7_TIM_SMCR_TS0_N((n) & UINT32_C(0x7)))

Definition at line 2903 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SR

#define MCCI_STM32H7_TIM_SR   UINT32_C(0x10)

offset to TIM status register

Definition at line 2815 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SR_B2IF

#define MCCI_STM32H7_TIM_SR_B2IF   (UINT32_C(1) << 8)

Break 2 interrupt flag.

Definition at line 2939 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SR_BIF

#define MCCI_STM32H7_TIM_SR_BIF   (UINT32_C(1) << 7)

Break interrupt flag.

Definition at line 2940 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SR_CC1IF

#define MCCI_STM32H7_TIM_SR_CC1IF   (UINT32_C(1) << 1)

Capture/Compare 1 interrupt flag.

Definition at line 2946 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SR_CC1OF

#define MCCI_STM32H7_TIM_SR_CC1OF   (UINT32_C(1) << 9)

Capture/Compare 1 overcapture flag.

Definition at line 2938 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SR_CC2IF

#define MCCI_STM32H7_TIM_SR_CC2IF   (UINT32_C(1) << 2)

Capture/Compare 2 interrupt flag.

Definition at line 2945 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SR_CC2OF

#define MCCI_STM32H7_TIM_SR_CC2OF   (UINT32_C(1) << 10)

Capture/Compare 2 overcapture flag.

Definition at line 2937 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SR_CC3IF

#define MCCI_STM32H7_TIM_SR_CC3IF   (UINT32_C(1) << 3)

Capture/Compare 3 interrupt flag.

Definition at line 2944 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SR_CC3OF

#define MCCI_STM32H7_TIM_SR_CC3OF   (UINT32_C(1) << 11)

Capture/Compare 3 overcapture flag.

Definition at line 2936 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SR_CC4IF

#define MCCI_STM32H7_TIM_SR_CC4IF   (UINT32_C(1) << 4)

Capture/Compare 4 interrupt flag.

Definition at line 2943 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SR_CC4OF

#define MCCI_STM32H7_TIM_SR_CC4OF   (UINT32_C(1) << 12)

Capture/Compare 4 overcapture flag.

Definition at line 2935 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SR_CC5IF

#define MCCI_STM32H7_TIM_SR_CC5IF   (UINT32_C(1) << 16)

Compare 5 interrupt flag.

Definition at line 2932 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SR_CC6IF

#define MCCI_STM32H7_TIM_SR_CC6IF   (UINT32_C(1) << 17)

Compare 6 interrupt flag.

Definition at line 2931 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SR_COMIF

#define MCCI_STM32H7_TIM_SR_COMIF   (UINT32_C(1) << 5)

COM interrupt flag.

Definition at line 2942 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SR_RSV14

#define MCCI_STM32H7_TIM_SR_RSV14   (UINT32_C(3) << 14)

reserved, don't change

Definition at line 2933 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SR_RSV18

#define MCCI_STM32H7_TIM_SR_RSV18   UINT32_C(0xFFFC0000)

reserved, don't change

Definition at line 2930 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SR_SBIF

#define MCCI_STM32H7_TIM_SR_SBIF   (UINT32_C(1) << 13)

System Break interrupt flag.

Definition at line 2934 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SR_TIF

#define MCCI_STM32H7_TIM_SR_TIF   (UINT32_C(1) << 6)

Trigger interrupt flag.

Definition at line 2941 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_SR_UIF

#define MCCI_STM32H7_TIM_SR_UIF   (UINT32_C(1) << 0)

Update interrupt flag.

Definition at line 2947 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_TISEL

#define MCCI_STM32H7_TIM_TISEL   UINT32_C(0x68)

offset to TIM timer input selection register

Definition at line 2836 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_TISEL_RSV12

#define MCCI_STM32H7_TIM_TISEL_RSV12   (UINT32_C(0xF) << 12)

reserved, don't change

Definition at line 3032 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_TISEL_RSV20

#define MCCI_STM32H7_TIM_TISEL_RSV20   (UINT32_C(0xF) << 20)

reserved, don't change

Definition at line 3029 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_TISEL_RSV28

#define MCCI_STM32H7_TIM_TISEL_RSV28   (UINT32_C(0xF) << 28)

reserved, don't change

Definition at line 3026 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_TISEL_RSV4

#define MCCI_STM32H7_TIM_TISEL_RSV4   (UINT32_C(0xF) << 4)

reserved, don't change

Definition at line 3035 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_TISEL_TI1SEL

#define MCCI_STM32H7_TIM_TISEL_TI1SEL   (UINT32_C(0xF) << 0)

selects TI1[0] to TI1[15] input

Definition at line 3036 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_TISEL_TI1SEL_N

#define MCCI_STM32H7_TIM_TISEL_TI1SEL_N (   n)    ((n) << 0)

Definition at line 3037 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_TISEL_TI2SEL

#define MCCI_STM32H7_TIM_TISEL_TI2SEL   (UINT32_C(0xF) << 8)

selects TI2[0] to TI2[15] input

Definition at line 3033 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_TISEL_TI2SEL_N

#define MCCI_STM32H7_TIM_TISEL_TI2SEL_N (   n)    ((n) << 8)

Definition at line 3034 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_TISEL_TI3SEL

#define MCCI_STM32H7_TIM_TISEL_TI3SEL   (UINT32_C(0xF) << 16)

selects TI3[0] to TI3[15] input

Definition at line 3030 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_TISEL_TI3SEL_N

#define MCCI_STM32H7_TIM_TISEL_TI3SEL_N (   n)    ((n) << 16)

Definition at line 3031 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_TISEL_TI4SEL

#define MCCI_STM32H7_TIM_TISEL_TI4SEL   (UINT32_C(0xF) << 24)

selects TI4[0] to TI4[15] input

Definition at line 3027 of file mcci_stm32h7xx.h.

◆ MCCI_STM32H7_TIM_TISEL_TI4SEL_N

#define MCCI_STM32H7_TIM_TISEL_TI4SEL_N (   n)    ((n) << 24)

Definition at line 3028 of file mcci_stm32h7xx.h.