#include "mcci_bootloader_bits.h"
#include <stdint.h>

Data Structures
union	Mcci_CortexAppEntry_t
	application entry object More...

struct	Mcci_CortexAppEntryContents_t
	application entry contents More...

union	Mcci_CortexM7Vectors_t
	Cortex M7 interrupt vector object. More...

struct	Mcci_CortexM7VectorsContents_t
	Cortex M7 interrupt vectors (low level view) More...

Macros
#define	_mcci_arm_cm7_h_ /* prevent multiple includes */

#define	MCCI_CM7_SCS_BASE UINT32_C(0xE000E000)

CPU Special function registers
#define	MCCI_CM7_SYSM_APSR UINT32_C(0x00)
	Flags from previous instructions.

#define	MCCI_CM7_SYSM_BASEPRI UINT32_C(0x11)
	base priority register

#define	MCCI_CM7_SYSM_BASEPRI_MAX UINT32_C(0x12)
	base priority max register

#define	MCCI_CM7_SYSM_CONTROL UINT32_C(0x14)
	control register

#define	MCCI_CM7_SYSM_EAPSR UINT32_C(0x02)
	Composite of EPSR and APSR.

#define	MCCI_CM7_SYSM_EPSR UINT32_C(0x06)
	Exception status register.

#define	MCCI_CM7_SYSM_FAULTMASK UINT32_C(0x13)
	register to raise priority to the HardFault level

#define	MCCI_CM7_SYSM_IAPSR UINT32_C(0x01)
	Composite of IPSR and APSR.

#define	MCCI_CM7_SYSM_IEPSR UINT32_C(0x07)
	Composite of IPSR and EPSR.

#define	MCCI_CM7_SYSM_IPSR UINT32_C(0x05)
	Interrupt status register.

#define	MCCI_CM7_SYSM_MSP UINT32_C(0x08)
	Main stack pointer.

#define	MCCI_CM7_SYSM_PRIMASK UINT32_C(0x10)
	priority mask register

#define	MCCI_CM7_SYSM_PSP UINT32_C(0x09)
	Process stack pointer.

#define	MCCI_CM7_SYSM_XPSR UINT32_C(0x03)
	Composite of EPSR, IPSR and APSR.

PRIMASK special register fields
#define	MCCI_CM7_SR_PRIMASK_DISABLE (UINT32_C(1) << 0)
	the bit to disable interrupts

BASEPRI special register fields
#define	MCCI_CM7_SR_BASEPRI_MASK (UINT32_C(0xFF) << 0)
	the base priority mask

#define	MCCI_CM7_SR_BASEPRI_VAL(n) ((n) << 0)
	the base priority value

FAULTMASK special register fields
#define	MCCI_CM7_SR_FAULTMASK_FM (UINT32_C(1) << 0)
	the fault mask

SCnSCB (System Controls not in SCB) registers
#define	MCCI_CM7_ACTLR UINT32_C(0xE000E008)

#define	MCCI_CM7_ICTR UINT32_C(0xE000E004)

SYSTICK registers
#define	MCCI_CM7_SYSTICK UINT32_C(0xE000E010)

#define	MCCI_CM7_SYSTICK_CALIB (MCCI_CM7_SYSTICK + 0xC)

#define	MCCI_CM7_SYSTICK_CSR (MCCI_CM7_SYSTICK + 0x0)

#define	MCCI_CM7_SYSTICK_CVR (MCCI_CM7_SYSTICK + 0x8)

#define	MCCI_CM7_SYSTICK_RVR (MCCI_CM7_SYSTICK + 0x4)

NVIC registers
#define	MCCI_CM7_NVIC UINT32_C(0xE000E100)

#define	MCCI_CM7_NVIC_IABR (MCCI_CM7_NVIC + 0x200)

#define	MCCI_CM7_NVIC_IABR0 (MCCI_CM7_NVIC + 0x200)

#define	MCCI_CM7_NVIC_IABR1 (MCCI_CM7_NVIC + 0x204)

#define	MCCI_CM7_NVIC_IABR2 (MCCI_CM7_NVIC + 0x208)

#define	MCCI_CM7_NVIC_IABR3 (MCCI_CM7_NVIC + 0x20C)

#define	MCCI_CM7_NVIC_IABR4 (MCCI_CM7_NVIC + 0x210)

#define	MCCI_CM7_NVIC_IABR5 (MCCI_CM7_NVIC + 0x214)

#define	MCCI_CM7_NVIC_IABR6 (MCCI_CM7_NVIC + 0x218)

#define	MCCI_CM7_NVIC_IABR7 (MCCI_CM7_NVIC + 0x21C)

#define	MCCI_CM7_NVIC_ICER (MCCI_CM7_NVIC + 0x080)

#define	MCCI_CM7_NVIC_ICER0 (MCCI_CM7_NVIC + 0x080)

#define	MCCI_CM7_NVIC_ICER1 (MCCI_CM7_NVIC + 0x084)

#define	MCCI_CM7_NVIC_ICER2 (MCCI_CM7_NVIC + 0x088)

#define	MCCI_CM7_NVIC_ICER3 (MCCI_CM7_NVIC + 0x08C)

#define	MCCI_CM7_NVIC_ICER4 (MCCI_CM7_NVIC + 0x090)

#define	MCCI_CM7_NVIC_ICER5 (MCCI_CM7_NVIC + 0x094)

#define	MCCI_CM7_NVIC_ICER6 (MCCI_CM7_NVIC + 0x098)

#define	MCCI_CM7_NVIC_ICER7 (MCCI_CM7_NVIC + 0x09C)

#define	MCCI_CM7_NVIC_ICPR (MCCI_CM7_NVIC + 0x180)

#define	MCCI_CM7_NVIC_ICPR0 (MCCI_CM7_NVIC + 0x180)

#define	MCCI_CM7_NVIC_ICPR1 (MCCI_CM7_NVIC + 0x184)

#define	MCCI_CM7_NVIC_ICPR2 (MCCI_CM7_NVIC + 0x188)

#define	MCCI_CM7_NVIC_ICPR3 (MCCI_CM7_NVIC + 0x18C)

#define	MCCI_CM7_NVIC_ICPR4 (MCCI_CM7_NVIC + 0x190)

#define	MCCI_CM7_NVIC_ICPR5 (MCCI_CM7_NVIC + 0x194)

#define	MCCI_CM7_NVIC_ICPR6 (MCCI_CM7_NVIC + 0x198)

#define	MCCI_CM7_NVIC_ICPR7 (MCCI_CM7_NVIC + 0x19C)

#define	MCCI_CM7_NVIC_IPR (MCCI_CM7_NVIC + 0x300)

#define	MCCI_CM7_NVIC_IPR0 (MCCI_CM7_NVIC + 0x300)

#define	MCCI_CM7_NVIC_IPR1 (MCCI_CM7_NVIC + 0x304)

#define	MCCI_CM7_NVIC_IPR10 (MCCI_CM7_NVIC + 0x328)

#define	MCCI_CM7_NVIC_IPR11 (MCCI_CM7_NVIC + 0x32C)

#define	MCCI_CM7_NVIC_IPR12 (MCCI_CM7_NVIC + 0x330)

#define	MCCI_CM7_NVIC_IPR13 (MCCI_CM7_NVIC + 0x334)

#define	MCCI_CM7_NVIC_IPR14 (MCCI_CM7_NVIC + 0x338)

#define	MCCI_CM7_NVIC_IPR15 (MCCI_CM7_NVIC + 0x33C)

#define	MCCI_CM7_NVIC_IPR16 (MCCI_CM7_NVIC + 0x340)

#define	MCCI_CM7_NVIC_IPR17 (MCCI_CM7_NVIC + 0x344)

#define	MCCI_CM7_NVIC_IPR18 (MCCI_CM7_NVIC + 0x348)

#define	MCCI_CM7_NVIC_IPR19 (MCCI_CM7_NVIC + 0x34C)

#define	MCCI_CM7_NVIC_IPR2 (MCCI_CM7_NVIC + 0x308)

#define	MCCI_CM7_NVIC_IPR20 (MCCI_CM7_NVIC + 0x350)

#define	MCCI_CM7_NVIC_IPR21 (MCCI_CM7_NVIC + 0x354)

#define	MCCI_CM7_NVIC_IPR22 (MCCI_CM7_NVIC + 0x358)

#define	MCCI_CM7_NVIC_IPR23 (MCCI_CM7_NVIC + 0x35C)

#define	MCCI_CM7_NVIC_IPR24 (MCCI_CM7_NVIC + 0x360)

#define	MCCI_CM7_NVIC_IPR25 (MCCI_CM7_NVIC + 0x364)

#define	MCCI_CM7_NVIC_IPR26 (MCCI_CM7_NVIC + 0x368)

#define	MCCI_CM7_NVIC_IPR27 (MCCI_CM7_NVIC + 0x36C)

#define	MCCI_CM7_NVIC_IPR28 (MCCI_CM7_NVIC + 0x370)

#define	MCCI_CM7_NVIC_IPR29 (MCCI_CM7_NVIC + 0x374)

#define	MCCI_CM7_NVIC_IPR3 (MCCI_CM7_NVIC + 0x30C)

#define	MCCI_CM7_NVIC_IPR30 (MCCI_CM7_NVIC + 0x378)

#define	MCCI_CM7_NVIC_IPR31 (MCCI_CM7_NVIC + 0x37C)

#define	MCCI_CM7_NVIC_IPR32 (MCCI_CM7_NVIC + 0x380)

#define	MCCI_CM7_NVIC_IPR33 (MCCI_CM7_NVIC + 0x384)

#define	MCCI_CM7_NVIC_IPR34 (MCCI_CM7_NVIC + 0x388)

#define	MCCI_CM7_NVIC_IPR35 (MCCI_CM7_NVIC + 0x38C)

#define	MCCI_CM7_NVIC_IPR36 (MCCI_CM7_NVIC + 0x390)

#define	MCCI_CM7_NVIC_IPR37 (MCCI_CM7_NVIC + 0x394)

#define	MCCI_CM7_NVIC_IPR38 (MCCI_CM7_NVIC + 0x398)

#define	MCCI_CM7_NVIC_IPR39 (MCCI_CM7_NVIC + 0x39C)

#define	MCCI_CM7_NVIC_IPR4 (MCCI_CM7_NVIC + 0x310)

#define	MCCI_CM7_NVIC_IPR40 (MCCI_CM7_NVIC + 0x3A0)

#define	MCCI_CM7_NVIC_IPR41 (MCCI_CM7_NVIC + 0x3A4)

#define	MCCI_CM7_NVIC_IPR42 (MCCI_CM7_NVIC + 0x3A8)

#define	MCCI_CM7_NVIC_IPR43 (MCCI_CM7_NVIC + 0x3AC)

#define	MCCI_CM7_NVIC_IPR44 (MCCI_CM7_NVIC + 0x3B0)

#define	MCCI_CM7_NVIC_IPR45 (MCCI_CM7_NVIC + 0x3B4)

#define	MCCI_CM7_NVIC_IPR46 (MCCI_CM7_NVIC + 0x3B8)

#define	MCCI_CM7_NVIC_IPR47 (MCCI_CM7_NVIC + 0x3BC)

#define	MCCI_CM7_NVIC_IPR48 (MCCI_CM7_NVIC + 0x3C0)

#define	MCCI_CM7_NVIC_IPR49 (MCCI_CM7_NVIC + 0x3C4)

#define	MCCI_CM7_NVIC_IPR5 (MCCI_CM7_NVIC + 0x314)

#define	MCCI_CM7_NVIC_IPR50 (MCCI_CM7_NVIC + 0x3C8)

#define	MCCI_CM7_NVIC_IPR51 (MCCI_CM7_NVIC + 0x3CC)

#define	MCCI_CM7_NVIC_IPR52 (MCCI_CM7_NVIC + 0x3D0)

#define	MCCI_CM7_NVIC_IPR53 (MCCI_CM7_NVIC + 0x3D4)

#define	MCCI_CM7_NVIC_IPR54 (MCCI_CM7_NVIC + 0x3D8)

#define	MCCI_CM7_NVIC_IPR55 (MCCI_CM7_NVIC + 0x3DC)

#define	MCCI_CM7_NVIC_IPR56 (MCCI_CM7_NVIC + 0x3E0)

#define	MCCI_CM7_NVIC_IPR57 (MCCI_CM7_NVIC + 0x3E4)

#define	MCCI_CM7_NVIC_IPR58 (MCCI_CM7_NVIC + 0x3E8)

#define	MCCI_CM7_NVIC_IPR59 (MCCI_CM7_NVIC + 0x3EC)

#define	MCCI_CM7_NVIC_IPR6 (MCCI_CM7_NVIC + 0x318)

#define	MCCI_CM7_NVIC_IPR7 (MCCI_CM7_NVIC + 0x31C)

#define	MCCI_CM7_NVIC_IPR8 (MCCI_CM7_NVIC + 0x320)

#define	MCCI_CM7_NVIC_IPR9 (MCCI_CM7_NVIC + 0x324)

#define	MCCI_CM7_NVIC_ISER (MCCI_CM7_NVIC + 0x000)

#define	MCCI_CM7_NVIC_ISER0 (MCCI_CM7_NVIC + 0x000)

#define	MCCI_CM7_NVIC_ISER1 (MCCI_CM7_NVIC + 0x004)

#define	MCCI_CM7_NVIC_ISER2 (MCCI_CM7_NVIC + 0x008)

#define	MCCI_CM7_NVIC_ISER3 (MCCI_CM7_NVIC + 0x00C)

#define	MCCI_CM7_NVIC_ISER4 (MCCI_CM7_NVIC + 0x010)

#define	MCCI_CM7_NVIC_ISER5 (MCCI_CM7_NVIC + 0x014)

#define	MCCI_CM7_NVIC_ISER6 (MCCI_CM7_NVIC + 0x018)

#define	MCCI_CM7_NVIC_ISER7 (MCCI_CM7_NVIC + 0x01C)

#define	MCCI_CM7_NVIC_ISPR (MCCI_CM7_NVIC + 0x100)

#define	MCCI_CM7_NVIC_ISPR0 (MCCI_CM7_NVIC + 0x100)

#define	MCCI_CM7_NVIC_ISPR1 (MCCI_CM7_NVIC + 0x104)

#define	MCCI_CM7_NVIC_ISPR2 (MCCI_CM7_NVIC + 0x108)

#define	MCCI_CM7_NVIC_ISPR3 (MCCI_CM7_NVIC + 0x10C)

#define	MCCI_CM7_NVIC_ISPR4 (MCCI_CM7_NVIC + 0x110)

#define	MCCI_CM7_NVIC_ISPR5 (MCCI_CM7_NVIC + 0x114)

#define	MCCI_CM7_NVIC_ISPR6 (MCCI_CM7_NVIC + 0x118)

#define	MCCI_CM7_NVIC_ISPR7 (MCCI_CM7_NVIC + 0x11C)

SCB registers
#define	MCCI_CM7_SCB UINT32_C(0xE000ED00)

#define	MCCI_CM7_SCB_ABFSR (MCCI_CM7_SCB + 0x2A8)

#define	MCCI_CM7_SCB_AHBPCR (MCCI_CM7_SCB + 0x298)

#define	MCCI_CM7_SCB_AHBSCR (MCCI_CM7_SCB + 0x2A0)

#define	MCCI_CM7_SCB_AIRCR (MCCI_CM7_SCB + 0x0C)

#define	MCCI_CM7_SCB_BFAR (MCCI_CM7_SCB + 0x38)

#define	MCCI_CM7_SCB_BPIALL (MCCI_CM7_SCB + 0x278)

#define	MCCI_CM7_SCB_CACR (MCCI_CM7_SCB + 0x29C)

#define	MCCI_CM7_SCB_CCR (MCCI_CM7_SCB + 0x14)

#define	MCCI_CM7_SCB_CCSIDR (MCCI_CM7_SCB + 0x80)

#define	MCCI_CM7_SCB_CFSR (MCCI_CM7_SCB + 0x28)

#define	MCCI_CM7_SCB_CID0 (MCCI_CM7_SCB + 0x2F0)

#define	MCCI_CM7_SCB_CID1 (MCCI_CM7_SCB + 0x2F4)

#define	MCCI_CM7_SCB_CID2 (MCCI_CM7_SCB + 0x2F8)

#define	MCCI_CM7_SCB_CID3 (MCCI_CM7_SCB + 0x2FC)

#define	MCCI_CM7_SCB_CLIDR (MCCI_CM7_SCB + 0x78)

#define	MCCI_CM7_SCB_CPACR (MCCI_CM7_SCB + 0x88)

#define	MCCI_CM7_SCB_CPUID (MCCI_CM7_SCB + 0x00)

#define	MCCI_CM7_SCB_CSSELR (MCCI_CM7_SCB + 0x84)

#define	MCCI_CM7_SCB_CTR (MCCI_CM7_SCB + 0x7C)

#define	MCCI_CM7_SCB_DCCIMVAC (MCCI_CM7_SCB + 0x270)

#define	MCCI_CM7_SCB_DCCISW (MCCI_CM7_SCB + 0x274)

#define	MCCI_CM7_SCB_DCCMVAC (MCCI_CM7_SCB + 0x268)

#define	MCCI_CM7_SCB_DCCMVAU (MCCI_CM7_SCB + 0x264)

#define	MCCI_CM7_SCB_DCCSW (MCCI_CM7_SCB + 0x26C)

#define	MCCI_CM7_SCB_DCIMVAC (MCCI_CM7_SCB + 0x25C)

#define	MCCI_CM7_SCB_DCISW (MCCI_CM7_SCB + 0x260)

#define	MCCI_CM7_SCB_DEBR0 (MCCI_CM7_SCB + 0x2B8)

#define	MCCI_CM7_SCB_DEBR1 (MCCI_CM7_SCB + 0x2BC)

#define	MCCI_CM7_SCB_DFSR (MCCI_CM7_SCB + 0x30)

#define	MCCI_CM7_SCB_DTCMCR (MCCI_CM7_SCB + 0x294)

#define	MCCI_CM7_SCB_HFSR (MCCI_CM7_SCB + 0x2C)

#define	MCCI_CM7_SCB_ICIALLU (MCCI_CM7_SCB + 0x250)

#define	MCCI_CM7_SCB_ICIMVAU (MCCI_CM7_SCB + 0x258)

#define	MCCI_CM7_SCB_ICSR (MCCI_CM7_SCB + 0x04)

#define	MCCI_CM7_SCB_ID_AFR0 (MCCI_CM7_SCB + 0x4C)

#define	MCCI_CM7_SCB_ID_DFR0 (MCCI_CM7_SCB + 0x48)

#define	MCCI_CM7_SCB_ID_ISAR0 (MCCI_CM7_SCB + 0x60)

#define	MCCI_CM7_SCB_ID_ISAR1 (MCCI_CM7_SCB + 0x64)

#define	MCCI_CM7_SCB_ID_ISAR2 (MCCI_CM7_SCB + 0x68)

#define	MCCI_CM7_SCB_ID_ISAR3 (MCCI_CM7_SCB + 0x6C)

#define	MCCI_CM7_SCB_ID_ISAR4 (MCCI_CM7_SCB + 0x70)

#define	MCCI_CM7_SCB_ID_MMFR0 (MCCI_CM7_SCB + 0x50)

#define	MCCI_CM7_SCB_ID_MMFR1 (MCCI_CM7_SCB + 0x54)

#define	MCCI_CM7_SCB_ID_MMFR2 (MCCI_CM7_SCB + 0x58)

#define	MCCI_CM7_SCB_ID_MMFR3 (MCCI_CM7_SCB + 0x5C)

#define	MCCI_CM7_SCB_ID_PFR0 (MCCI_CM7_SCB + 0x40)

#define	MCCI_CM7_SCB_ID_PFR1 (MCCI_CM7_SCB + 0x44)

#define	MCCI_CM7_SCB_IEBR0 (MCCI_CM7_SCB + 0x2B0)

#define	MCCI_CM7_SCB_IEBR1 (MCCI_CM7_SCB + 0x2B4)

#define	MCCI_CM7_SCB_ITCMCR (MCCI_CM7_SCB + 0x290)

#define	MCCI_CM7_SCB_MMFAR (MCCI_CM7_SCB + 0x34)

#define	MCCI_CM7_SCB_PID0 (MCCI_CM7_SCB + 0x2E0)

#define	MCCI_CM7_SCB_PID1 (MCCI_CM7_SCB + 0x2E4)

#define	MCCI_CM7_SCB_PID2 (MCCI_CM7_SCB + 0x2E8)

#define	MCCI_CM7_SCB_PID3 (MCCI_CM7_SCB + 0x2EC)

#define	MCCI_CM7_SCB_PID4 (MCCI_CM7_SCB + 0x2D0)

#define	MCCI_CM7_SCB_PID5 (MCCI_CM7_SCB + 0x2D4)

#define	MCCI_CM7_SCB_PID6 (MCCI_CM7_SCB + 0x2D8)

#define	MCCI_CM7_SCB_PID7 (MCCI_CM7_SCB + 0x2DC)

#define	MCCI_CM7_SCB_SCR (MCCI_CM7_SCB + 0x10)

#define	MCCI_CM7_SCB_SHCSR (MCCI_CM7_SCB + 0x24)

#define	MCCI_CM7_SCB_SHPR1 (MCCI_CM7_SCB + 0x18)

#define	MCCI_CM7_SCB_SHPR2 (MCCI_CM7_SCB + 0x1C)

#define	MCCI_CM7_SCB_SHPR3 (MCCI_CM7_SCB + 0x20)

#define	MCCI_CM7_SCB_STIR (MCCI_CM7_SCB + 0x200)

#define	MCCI_CM7_SCB_VTOR (MCCI_CM7_SCB + 0x08)

FPU registers
#define	MCCI_CM7_FPU UINT32_C(0xE000EF30)

#define	MCCI_CM7_FPU_FPCAR (MCCI_CM7_FPU + 0x08)

#define	MCCI_CM7_FPU_FPCCR (MCCI_CM7_FPU + 0x04)

#define	MCCI_CM7_FPU_FPDSCR (MCCI_CM7_FPU + 0x0C)

#define	MCCI_CM7_FPU_MVFR0 (MCCI_CM7_FPU + 0x10)

#define	MCCI_CM7_FPU_MVFR1 (MCCI_CM7_FPU + 0x14)

#define	MCCI_CM7_FPU_MVFR2 (MCCI_CM7_FPU + 0x18)

SYSTICK CSR bits
#define	MCCI_CM7_SYSTICK_CSR_CLKSOURCE (UINT32_C(1) << 2)
	use processor (not external) clock

#define	MCCI_CM7_SYSTICK_CSR_COUNTFLAG (UINT32_C(1) << 16)
	timer has counted to zero

#define	MCCI_CM7_SYSTICK_CSR_ENABLE (UINT32_C(1) << 0)
	enable counter

#define	MCCI_CM7_SYSTICK_CSR_RSV17 UINT32_C(0xFFFE0000)
	reserved

#define	MCCI_CM7_SYSTICK_CSR_RSV3 UINT32_C(0x0000FFF8)
	reserved

#define	MCCI_CM7_SYSTICK_CSR_TICKINT (UINT32_C(1) << 1)
	enable tick exception

SYSTICK RVR bits
#define	MCCI_CM7_SYSTICK_RVR_RELOAD UINT32_C(0x00FFFFFF)
	reload value

#define	MCCI_CM7_SYSTICK_RVR_RSV24 UINT32_C(0xFF000000)
	reserved, zero

SYSTICK CVR bits
#define	MCCI_CM7_SYSTICK_CVR_CURRENT UINT32_C(0x00FFFFFF)
	current value

#define	MCCI_CM7_SYSTICK_CVR_RSV24 UINT32_C(0xFF000000)
	reserved, read as zero

SYSTICK CALIB bits
#define	MCCI_CM7_SYSTICK_CALIB_NOREF (UINT32_C(1) << 31)
	reference clock is not implemented

#define	MCCI_CM7_SYSTICK_CALIB_RSV24 (UINT32_C(0x3F) << 24)
	reserved, zero

#define	MCCI_CM7_SYSTICK_CALIB_SKEW (UINT32_C(1) << 30)
	10ms cal value is inexact

#define	MCCI_CM7_SYSTICK_CALIB_TENMS UINT32_C(0x00FFFFFF)
	if non-zero, use this as reload value for 10ms ticks

SCB CPUID fields
#define	MCCI_CM7_SCB_CPUID_ARCHITECTURE (UINT32_C(0xF) << 16)
	Architecture code.

#define	MCCI_CM7_SCB_CPUID_IMPLEMENTER (UINT32_C(0xFF) << 24)
	Implementer code.

#define	MCCI_CM7_SCB_CPUID_PARTNO (UINT32_C(0xFFF) << 4)
	Part number.

#define	MCCI_CM7_SCB_CPUID_REVISION (UINT32_C(0xF) << 0)
	Revision.

#define	MCCI_CM7_SCB_CPUID_VARIANT (UINT32_C(0xF) << 20)
	Variant code.

SCB ICSR fields
#define	MCCI_CM7_SCB_ICSR_ISRPENDING (UINT32_C(1) << 22)

#define	MCCI_CM7_SCB_ICSR_ISRPREEMPT (UINT32_C(1) << 23)

#define	MCCI_CM7_SCB_ICSR_NMIPENDSET (UINT32_C(1) << 31)

#define	MCCI_CM7_SCB_ICSR_PENDSTCLR (UINT32_C(1) << 25)

#define	MCCI_CM7_SCB_ICSR_PENDSTSET (UINT32_C(1) << 26)

#define	MCCI_CM7_SCB_ICSR_PENDSVCLR (UINT32_C(1) << 27)

#define	MCCI_CM7_SCB_ICSR_PENDSVSET (UINT32_C(1) << 28)

#define	MCCI_CM7_SCB_ICSR_RETTOBASE (UINT32_C(1) << 11)

#define	MCCI_CM7_SCB_ICSR_RSV24 (UINT32_C(1) << 24)

#define	MCCI_CM7_SCB_ICSR_RSV29 (UINT32_C(3) << 29)

#define	MCCI_CM7_SCB_ICSR_VECTACTIVE (UINT32_C(0x1FF) << 0)

#define	MCCI_CM7_SCB_ICSR_VECTPENDING (UINT32_C(0x1FF) << 12)

SCB VTOR fields
#define	MCCI_CM7_SCB_VTOR_TBLOFF UINT32_C(0xFFFFFF80)

SCB AIRCR fields (Application Interrupt and Reset Control)
#define	MCCI_CM7_SCB_AIRCR_ENDIANNESS (UINT32_C(1) << 15)
	0=little, 1=big endian

#define	MCCI_CM7_SCB_AIRCR_PRIGROUP (UINT32_C(7) << 8)
	Priority grouping position.

#define	MCCI_CM7_SCB_AIRCR_PRIGROUP_N(n) ((n) << 8)

#define	MCCI_CM7_SCB_AIRCR_SYSRESETREQ (UINT32_C(1) << 2)
	System reset request.

#define	MCCI_CM7_SCB_AIRCR_VECTCLRACTIVE (UINT32_C(1) << 1)

#define	MCCI_CM7_SCB_AIRCR_VECTKEY (UINT32_C(0xFFFF) << 16)
	Vector key.

#define	MCCI_CM7_SCB_AIRCR_VECTKEY_VALUE (UINT32_C(0x05FA) << 16)
	Value to write to unlock register.

#define	MCCI_CM7_SCB_AIRCR_VECTRESET (UINT32_C(1) << 0)

SCB SCR fields
#define	MCCI_CM7_SCB_SCR_SEVONPEND (UINT32_C(1) << 4)

#define	MCCI_CM7_SCB_SCR_SLEEPDEEP (UINT32_C(1) << 2)

#define	MCCI_CM7_SCB_SCR_SLEEPONEXIT (UINT32_C(1) << 1)

SCB Configuration Control Register bits
#define	MCCI_CM7_SCB_CCR_BFHFNMIGN (UINT32_C(1) << 8)

#define	MCCI_CM7_SCB_CCR_BP (UINT32_C(1) << 18)

#define	MCCI_CM7_SCB_CCR_DC (UINT32_C(1) << 16)

#define	MCCI_CM7_SCB_CCR_DIV_0_TRP (UINT32_C(1) << 4)

#define	MCCI_CM7_SCB_CCR_IC (UINT32_C(1) << 17)

#define	MCCI_CM7_SCB_CCR_NONBASETHRDENA (UINT32_C(1) << 0)

#define	MCCI_CM7_SCB_CCR_STKALIGN (UINT32_C(1) << 9)

#define	MCCI_CM7_SCB_CCR_UNALIGN_TRP (UINT32_C(1) << 3)

#define	MCCI_CM7_SCB_CCR_USERSETMPEND (UINT32_C(1) << 1)

SCB System Handler Control and State Register bits
#define	MCCI_CM7_SCB_SHCSR_BUSFAULTACT (UINT32_C(1) << 1)

#define	MCCI_CM7_SCB_SHCSR_BUSFAULTENA (UINT32_C(1) << 17)

#define	MCCI_CM7_SCB_SHCSR_BUSFAULTPENDED (UINT32_C(1) << 14)

#define	MCCI_CM7_SCB_SHCSR_MEMFAULTACT (UINT32_C(1) << 0)

#define	MCCI_CM7_SCB_SHCSR_MEMFAULTENA (UINT32_C(1) << 16)

#define	MCCI_CM7_SCB_SHCSR_MEMFAULTPENDED (UINT32_C(1) << 13)

#define	MCCI_CM7_SCB_SHCSR_MONITORACT (UINT32_C(1) << 8)

#define	MCCI_CM7_SCB_SHCSR_PENDSVACT (UINT32_C(1) << 10)

#define	MCCI_CM7_SCB_SHCSR_SVCALLACT (UINT32_C(1) << 7)

#define	MCCI_CM7_SCB_SHCSR_SVCALLPENDED (UINT32_C(1) << 15)

#define	MCCI_CM7_SCB_SHCSR_SYSTICKACT (UINT32_C(1) << 11)

#define	MCCI_CM7_SCB_SHCSR_USGFAULTACT (UINT32_C(1) << 3)

#define	MCCI_CM7_SCB_SHCSR_USGFAULTENA (UINT32_C(1) << 18)

#define	MCCI_CM7_SCB_SHCSR_USGFAULTPENDED (UINT32_C(1) << 12)

Cortex-M Processor Exceptions Numbers
#define	MCCI_CM7_IRQ_BASE UINT32_C(256)
	Cortex-M Processor Exception Number Base.

#define	MCCI_CM7_IRQ_BusFault (MCCI_CM7_IRQ_BASE + UINT32_C(5))
	Cortex-M Bus Fault Interrupt.

#define	MCCI_CM7_IRQ_DebugMonitor (MCCI_CM7_IRQ_BASE + UINT32_C(12))
	Cortex-M Debug Monitor Interrupt.

#define	MCCI_CM7_IRQ_HardFault (MCCI_CM7_IRQ_BASE + UINT32_C(3))
	Cortex-M Hard Fault.

#define	MCCI_CM7_IRQ_MemoryManagement (MCCI_CM7_IRQ_BASE + UINT32_C(4))
	Cortex-M Memory Management Interrupt.

#define	MCCI_CM7_IRQ_NonMaskableInt (MCCI_CM7_IRQ_BASE + UINT32_C(2))
	Non Maskable Interrupt.

#define	MCCI_CM7_IRQ_PendSV (MCCI_CM7_IRQ_BASE + UINT32_C(14))
	Cortex-M Pend SV Interrupt.

#define	MCCI_CM7_IRQ_SVCall (MCCI_CM7_IRQ_BASE + UINT32_C(11))
	Cortex-M SV Call Interrupt.

#define	MCCI_CM7_IRQ_SysTick (MCCI_CM7_IRQ_BASE + UINT32_C(15))
	Cortex-M System Tick Interrupt.

#define	MCCI_CM7_IRQ_UsageFault (MCCI_CM7_IRQ_BASE + UINT32_C(6))
	Cortex-M Usage Fault Interrupt.

Functions
static uint32_t	McciArm_getReg (uint32_t reg)
	read a 32-bit value from a cm7 register

static uint32_t	McciArm_putReg (uint32_t reg, uint32_t val)
	write a 32-bit value to a cm7 register

static uint32_t	McciArm_putRegAndOr (uint32_t reg, uint32_t andVal, uint32_t orVal)
	and/or 32-bit values to a cm7 register

static uint32_t	McciArm_putRegClear (uint32_t reg, uint32_t clearVal)
	clear out 32-bit values to a cm7 register

static uint32_t	McciArm_putRegClearSet (uint32_t reg, uint32_t clearVal, uint32_t setVal)
	clear and set 32-bit values to a cm7 register

static uint32_t	McciArm_putRegMasked (uint32_t reg, uint32_t maskVal, uint32_t modVal)
	store to cm7 register under mask

static uint32_t	McciArm_putRegOr (uint32_t reg, uint32_t orVal)
	or 32-bit values to a cm7 register

SCB SHPR access
#define	MCCI_CM7_PRI_INDEX_BUS_FAULT UINT32_C(5)
	priority of BusFault

#define	MCCI_CM7_PRI_INDEX_DEBUG_MONITOR UINT32_C(12)
	priority of DebugMonitor

#define	MCCI_CM7_PRI_INDEX_MEM_MANAGE UINT32_C(4)
	priority of MemManage

#define	MCCI_CM7_PRI_INDEX_PENDSV UINT32_C(14)
	priority of PendSV

#define	MCCI_CM7_PRI_INDEX_SVC UINT32_C(11)
	priority of SVCall

#define	MCCI_CM7_PRI_INDEX_SYSTICK UINT32_C(15)
	priority of systick

#define	MCCI_CM7_PRI_INDEX_USAGE_FAULT UINT32_C(6)
	priority of UsageFault

#define	MCCI_CM7_SCB_SHPR_PRI (UINT32_C(7) << 5)
	priority bits within a byte

static uint32_t	McciCm7_SCB_SHPR_getMask (uint32_t handlerIndex)
	return byte mask for a given handler index

static uint32_t	McciCm7_SCB_SHPR_getRegister (uint32_t handlerIndex)
	return register for a given handler index

Macro Definition Documentation

◆ _mcci_arm_cm7_h_

#define _mcci_arm_cm7_h_ /* prevent multiple includes */

Definition at line 23 of file mcci_arm_cm7.h.

◆ MCCI_CM7_ACTLR

#define MCCI_CM7_ACTLR UINT32_C(0xE000E008)

Definition at line 90 of file mcci_arm_cm7.h.

◆ MCCI_CM7_FPU

#define MCCI_CM7_FPU UINT32_C(0xE000EF30)

Definition at line 286 of file mcci_arm_cm7.h.

◆ MCCI_CM7_FPU_FPCAR

#define MCCI_CM7_FPU_FPCAR (MCCI_CM7_FPU + 0x08)

Definition at line 288 of file mcci_arm_cm7.h.

◆ MCCI_CM7_FPU_FPCCR

#define MCCI_CM7_FPU_FPCCR (MCCI_CM7_FPU + 0x04)

Definition at line 287 of file mcci_arm_cm7.h.

◆ MCCI_CM7_FPU_FPDSCR

#define MCCI_CM7_FPU_FPDSCR (MCCI_CM7_FPU + 0x0C)

Definition at line 289 of file mcci_arm_cm7.h.

◆ MCCI_CM7_FPU_MVFR0

#define MCCI_CM7_FPU_MVFR0 (MCCI_CM7_FPU + 0x10)

Definition at line 290 of file mcci_arm_cm7.h.

◆ MCCI_CM7_FPU_MVFR1

#define MCCI_CM7_FPU_MVFR1 (MCCI_CM7_FPU + 0x14)

Definition at line 291 of file mcci_arm_cm7.h.

◆ MCCI_CM7_FPU_MVFR2

#define MCCI_CM7_FPU_MVFR2 (MCCI_CM7_FPU + 0x18)

Definition at line 292 of file mcci_arm_cm7.h.

◆ MCCI_CM7_ICTR

#define MCCI_CM7_ICTR UINT32_C(0xE000E004)

Definition at line 89 of file mcci_arm_cm7.h.

◆ MCCI_CM7_IRQ_BASE

#define MCCI_CM7_IRQ_BASE UINT32_C(256)

Cortex-M Processor Exception Number Base.

Definition at line 453 of file mcci_arm_cm7.h.

◆ MCCI_CM7_IRQ_BusFault

#define MCCI_CM7_IRQ_BusFault (MCCI_CM7_IRQ_BASE + UINT32_C(5))

Cortex-M Bus Fault Interrupt.

Definition at line 457 of file mcci_arm_cm7.h.

◆ MCCI_CM7_IRQ_DebugMonitor

#define MCCI_CM7_IRQ_DebugMonitor (MCCI_CM7_IRQ_BASE + UINT32_C(12))

Cortex-M Debug Monitor Interrupt.

Definition at line 460 of file mcci_arm_cm7.h.

◆ MCCI_CM7_IRQ_HardFault

#define MCCI_CM7_IRQ_HardFault (MCCI_CM7_IRQ_BASE + UINT32_C(3))

Cortex-M Hard Fault.

Definition at line 455 of file mcci_arm_cm7.h.

◆ MCCI_CM7_IRQ_MemoryManagement

#define MCCI_CM7_IRQ_MemoryManagement (MCCI_CM7_IRQ_BASE + UINT32_C(4))

Cortex-M Memory Management Interrupt.

Definition at line 456 of file mcci_arm_cm7.h.

◆ MCCI_CM7_IRQ_NonMaskableInt

#define MCCI_CM7_IRQ_NonMaskableInt (MCCI_CM7_IRQ_BASE + UINT32_C(2))

Non Maskable Interrupt.

Definition at line 454 of file mcci_arm_cm7.h.

◆ MCCI_CM7_IRQ_PendSV

#define MCCI_CM7_IRQ_PendSV (MCCI_CM7_IRQ_BASE + UINT32_C(14))

Cortex-M Pend SV Interrupt.

Definition at line 461 of file mcci_arm_cm7.h.

◆ MCCI_CM7_IRQ_SVCall

#define MCCI_CM7_IRQ_SVCall (MCCI_CM7_IRQ_BASE + UINT32_C(11))

Cortex-M SV Call Interrupt.

Definition at line 459 of file mcci_arm_cm7.h.

◆ MCCI_CM7_IRQ_SysTick

#define MCCI_CM7_IRQ_SysTick (MCCI_CM7_IRQ_BASE + UINT32_C(15))

Cortex-M System Tick Interrupt.

Definition at line 462 of file mcci_arm_cm7.h.

◆ MCCI_CM7_IRQ_UsageFault

#define MCCI_CM7_IRQ_UsageFault (MCCI_CM7_IRQ_BASE + UINT32_C(6))

Cortex-M Usage Fault Interrupt.

Definition at line 458 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC

#define MCCI_CM7_NVIC UINT32_C(0xE000E100)

Definition at line 104 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IABR

#define MCCI_CM7_NVIC_IABR (MCCI_CM7_NVIC + 0x200)

Definition at line 141 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IABR0

#define MCCI_CM7_NVIC_IABR0 (MCCI_CM7_NVIC + 0x200)

Definition at line 142 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IABR1

#define MCCI_CM7_NVIC_IABR1 (MCCI_CM7_NVIC + 0x204)

Definition at line 143 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IABR2

#define MCCI_CM7_NVIC_IABR2 (MCCI_CM7_NVIC + 0x208)

Definition at line 144 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IABR3

#define MCCI_CM7_NVIC_IABR3 (MCCI_CM7_NVIC + 0x20C)

Definition at line 145 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IABR4

#define MCCI_CM7_NVIC_IABR4 (MCCI_CM7_NVIC + 0x210)

Definition at line 146 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IABR5

#define MCCI_CM7_NVIC_IABR5 (MCCI_CM7_NVIC + 0x214)

Definition at line 147 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IABR6

#define MCCI_CM7_NVIC_IABR6 (MCCI_CM7_NVIC + 0x218)

Definition at line 148 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IABR7

#define MCCI_CM7_NVIC_IABR7 (MCCI_CM7_NVIC + 0x21C)

Definition at line 149 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ICER

#define MCCI_CM7_NVIC_ICER (MCCI_CM7_NVIC + 0x080)

Definition at line 114 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ICER0

#define MCCI_CM7_NVIC_ICER0 (MCCI_CM7_NVIC + 0x080)

Definition at line 115 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ICER1

#define MCCI_CM7_NVIC_ICER1 (MCCI_CM7_NVIC + 0x084)

Definition at line 116 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ICER2

#define MCCI_CM7_NVIC_ICER2 (MCCI_CM7_NVIC + 0x088)

Definition at line 117 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ICER3

#define MCCI_CM7_NVIC_ICER3 (MCCI_CM7_NVIC + 0x08C)

Definition at line 118 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ICER4

#define MCCI_CM7_NVIC_ICER4 (MCCI_CM7_NVIC + 0x090)

Definition at line 119 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ICER5

#define MCCI_CM7_NVIC_ICER5 (MCCI_CM7_NVIC + 0x094)

Definition at line 120 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ICER6

#define MCCI_CM7_NVIC_ICER6 (MCCI_CM7_NVIC + 0x098)

Definition at line 121 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ICER7

#define MCCI_CM7_NVIC_ICER7 (MCCI_CM7_NVIC + 0x09C)

Definition at line 122 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ICPR

#define MCCI_CM7_NVIC_ICPR (MCCI_CM7_NVIC + 0x180)

Definition at line 132 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ICPR0

#define MCCI_CM7_NVIC_ICPR0 (MCCI_CM7_NVIC + 0x180)

Definition at line 133 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ICPR1

#define MCCI_CM7_NVIC_ICPR1 (MCCI_CM7_NVIC + 0x184)

Definition at line 134 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ICPR2

#define MCCI_CM7_NVIC_ICPR2 (MCCI_CM7_NVIC + 0x188)

Definition at line 135 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ICPR3

#define MCCI_CM7_NVIC_ICPR3 (MCCI_CM7_NVIC + 0x18C)

Definition at line 136 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ICPR4

#define MCCI_CM7_NVIC_ICPR4 (MCCI_CM7_NVIC + 0x190)

Definition at line 137 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ICPR5

#define MCCI_CM7_NVIC_ICPR5 (MCCI_CM7_NVIC + 0x194)

Definition at line 138 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ICPR6

#define MCCI_CM7_NVIC_ICPR6 (MCCI_CM7_NVIC + 0x198)

Definition at line 139 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ICPR7

#define MCCI_CM7_NVIC_ICPR7 (MCCI_CM7_NVIC + 0x19C)

Definition at line 140 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR

#define MCCI_CM7_NVIC_IPR (MCCI_CM7_NVIC + 0x300)

Definition at line 150 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR0

#define MCCI_CM7_NVIC_IPR0 (MCCI_CM7_NVIC + 0x300)

Definition at line 151 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR1

#define MCCI_CM7_NVIC_IPR1 (MCCI_CM7_NVIC + 0x304)

Definition at line 152 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR10

#define MCCI_CM7_NVIC_IPR10 (MCCI_CM7_NVIC + 0x328)

Definition at line 161 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR11

#define MCCI_CM7_NVIC_IPR11 (MCCI_CM7_NVIC + 0x32C)

Definition at line 162 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR12

#define MCCI_CM7_NVIC_IPR12 (MCCI_CM7_NVIC + 0x330)

Definition at line 163 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR13

#define MCCI_CM7_NVIC_IPR13 (MCCI_CM7_NVIC + 0x334)

Definition at line 164 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR14

#define MCCI_CM7_NVIC_IPR14 (MCCI_CM7_NVIC + 0x338)

Definition at line 165 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR15

#define MCCI_CM7_NVIC_IPR15 (MCCI_CM7_NVIC + 0x33C)

Definition at line 166 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR16

#define MCCI_CM7_NVIC_IPR16 (MCCI_CM7_NVIC + 0x340)

Definition at line 167 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR17

#define MCCI_CM7_NVIC_IPR17 (MCCI_CM7_NVIC + 0x344)

Definition at line 168 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR18

#define MCCI_CM7_NVIC_IPR18 (MCCI_CM7_NVIC + 0x348)

Definition at line 169 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR19

#define MCCI_CM7_NVIC_IPR19 (MCCI_CM7_NVIC + 0x34C)

Definition at line 170 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR2

#define MCCI_CM7_NVIC_IPR2 (MCCI_CM7_NVIC + 0x308)

Definition at line 153 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR20

#define MCCI_CM7_NVIC_IPR20 (MCCI_CM7_NVIC + 0x350)

Definition at line 171 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR21

#define MCCI_CM7_NVIC_IPR21 (MCCI_CM7_NVIC + 0x354)

Definition at line 172 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR22

#define MCCI_CM7_NVIC_IPR22 (MCCI_CM7_NVIC + 0x358)

Definition at line 173 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR23

#define MCCI_CM7_NVIC_IPR23 (MCCI_CM7_NVIC + 0x35C)

Definition at line 174 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR24

#define MCCI_CM7_NVIC_IPR24 (MCCI_CM7_NVIC + 0x360)

Definition at line 175 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR25

#define MCCI_CM7_NVIC_IPR25 (MCCI_CM7_NVIC + 0x364)

Definition at line 176 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR26

#define MCCI_CM7_NVIC_IPR26 (MCCI_CM7_NVIC + 0x368)

Definition at line 177 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR27

#define MCCI_CM7_NVIC_IPR27 (MCCI_CM7_NVIC + 0x36C)

Definition at line 178 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR28

#define MCCI_CM7_NVIC_IPR28 (MCCI_CM7_NVIC + 0x370)

Definition at line 179 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR29

#define MCCI_CM7_NVIC_IPR29 (MCCI_CM7_NVIC + 0x374)

Definition at line 180 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR3

#define MCCI_CM7_NVIC_IPR3 (MCCI_CM7_NVIC + 0x30C)

Definition at line 154 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR30

#define MCCI_CM7_NVIC_IPR30 (MCCI_CM7_NVIC + 0x378)

Definition at line 181 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR31

#define MCCI_CM7_NVIC_IPR31 (MCCI_CM7_NVIC + 0x37C)

Definition at line 182 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR32

#define MCCI_CM7_NVIC_IPR32 (MCCI_CM7_NVIC + 0x380)

Definition at line 183 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR33

#define MCCI_CM7_NVIC_IPR33 (MCCI_CM7_NVIC + 0x384)

Definition at line 184 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR34

#define MCCI_CM7_NVIC_IPR34 (MCCI_CM7_NVIC + 0x388)

Definition at line 185 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR35

#define MCCI_CM7_NVIC_IPR35 (MCCI_CM7_NVIC + 0x38C)

Definition at line 186 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR36

#define MCCI_CM7_NVIC_IPR36 (MCCI_CM7_NVIC + 0x390)

Definition at line 187 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR37

#define MCCI_CM7_NVIC_IPR37 (MCCI_CM7_NVIC + 0x394)

Definition at line 188 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR38

#define MCCI_CM7_NVIC_IPR38 (MCCI_CM7_NVIC + 0x398)

Definition at line 189 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR39

#define MCCI_CM7_NVIC_IPR39 (MCCI_CM7_NVIC + 0x39C)

Definition at line 190 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR4

#define MCCI_CM7_NVIC_IPR4 (MCCI_CM7_NVIC + 0x310)

Definition at line 155 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR40

#define MCCI_CM7_NVIC_IPR40 (MCCI_CM7_NVIC + 0x3A0)

Definition at line 191 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR41

#define MCCI_CM7_NVIC_IPR41 (MCCI_CM7_NVIC + 0x3A4)

Definition at line 192 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR42

#define MCCI_CM7_NVIC_IPR42 (MCCI_CM7_NVIC + 0x3A8)

Definition at line 193 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR43

#define MCCI_CM7_NVIC_IPR43 (MCCI_CM7_NVIC + 0x3AC)

Definition at line 194 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR44

#define MCCI_CM7_NVIC_IPR44 (MCCI_CM7_NVIC + 0x3B0)

Definition at line 195 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR45

#define MCCI_CM7_NVIC_IPR45 (MCCI_CM7_NVIC + 0x3B4)

Definition at line 196 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR46

#define MCCI_CM7_NVIC_IPR46 (MCCI_CM7_NVIC + 0x3B8)

Definition at line 197 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR47

#define MCCI_CM7_NVIC_IPR47 (MCCI_CM7_NVIC + 0x3BC)

Definition at line 198 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR48

#define MCCI_CM7_NVIC_IPR48 (MCCI_CM7_NVIC + 0x3C0)

Definition at line 199 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR49

#define MCCI_CM7_NVIC_IPR49 (MCCI_CM7_NVIC + 0x3C4)

Definition at line 200 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR5

#define MCCI_CM7_NVIC_IPR5 (MCCI_CM7_NVIC + 0x314)

Definition at line 156 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR50

#define MCCI_CM7_NVIC_IPR50 (MCCI_CM7_NVIC + 0x3C8)

Definition at line 201 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR51

#define MCCI_CM7_NVIC_IPR51 (MCCI_CM7_NVIC + 0x3CC)

Definition at line 202 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR52

#define MCCI_CM7_NVIC_IPR52 (MCCI_CM7_NVIC + 0x3D0)

Definition at line 203 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR53

#define MCCI_CM7_NVIC_IPR53 (MCCI_CM7_NVIC + 0x3D4)

Definition at line 204 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR54

#define MCCI_CM7_NVIC_IPR54 (MCCI_CM7_NVIC + 0x3D8)

Definition at line 205 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR55

#define MCCI_CM7_NVIC_IPR55 (MCCI_CM7_NVIC + 0x3DC)

Definition at line 206 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR56

#define MCCI_CM7_NVIC_IPR56 (MCCI_CM7_NVIC + 0x3E0)

Definition at line 207 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR57

#define MCCI_CM7_NVIC_IPR57 (MCCI_CM7_NVIC + 0x3E4)

Definition at line 208 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR58

#define MCCI_CM7_NVIC_IPR58 (MCCI_CM7_NVIC + 0x3E8)

Definition at line 209 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR59

#define MCCI_CM7_NVIC_IPR59 (MCCI_CM7_NVIC + 0x3EC)

Definition at line 210 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR6

#define MCCI_CM7_NVIC_IPR6 (MCCI_CM7_NVIC + 0x318)

Definition at line 157 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR7

#define MCCI_CM7_NVIC_IPR7 (MCCI_CM7_NVIC + 0x31C)

Definition at line 158 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR8

#define MCCI_CM7_NVIC_IPR8 (MCCI_CM7_NVIC + 0x320)

Definition at line 159 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_IPR9

#define MCCI_CM7_NVIC_IPR9 (MCCI_CM7_NVIC + 0x324)

Definition at line 160 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ISER

#define MCCI_CM7_NVIC_ISER (MCCI_CM7_NVIC + 0x000)

Definition at line 105 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ISER0

#define MCCI_CM7_NVIC_ISER0 (MCCI_CM7_NVIC + 0x000)

Definition at line 106 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ISER1

#define MCCI_CM7_NVIC_ISER1 (MCCI_CM7_NVIC + 0x004)

Definition at line 107 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ISER2

#define MCCI_CM7_NVIC_ISER2 (MCCI_CM7_NVIC + 0x008)

Definition at line 108 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ISER3

#define MCCI_CM7_NVIC_ISER3 (MCCI_CM7_NVIC + 0x00C)

Definition at line 109 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ISER4

#define MCCI_CM7_NVIC_ISER4 (MCCI_CM7_NVIC + 0x010)

Definition at line 110 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ISER5

#define MCCI_CM7_NVIC_ISER5 (MCCI_CM7_NVIC + 0x014)

Definition at line 111 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ISER6

#define MCCI_CM7_NVIC_ISER6 (MCCI_CM7_NVIC + 0x018)

Definition at line 112 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ISER7

#define MCCI_CM7_NVIC_ISER7 (MCCI_CM7_NVIC + 0x01C)

Definition at line 113 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ISPR

#define MCCI_CM7_NVIC_ISPR (MCCI_CM7_NVIC + 0x100)

Definition at line 123 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ISPR0

#define MCCI_CM7_NVIC_ISPR0 (MCCI_CM7_NVIC + 0x100)

Definition at line 124 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ISPR1

#define MCCI_CM7_NVIC_ISPR1 (MCCI_CM7_NVIC + 0x104)

Definition at line 125 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ISPR2

#define MCCI_CM7_NVIC_ISPR2 (MCCI_CM7_NVIC + 0x108)

Definition at line 126 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ISPR3

#define MCCI_CM7_NVIC_ISPR3 (MCCI_CM7_NVIC + 0x10C)

Definition at line 127 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ISPR4

#define MCCI_CM7_NVIC_ISPR4 (MCCI_CM7_NVIC + 0x110)

Definition at line 128 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ISPR5

#define MCCI_CM7_NVIC_ISPR5 (MCCI_CM7_NVIC + 0x114)

Definition at line 129 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ISPR6

#define MCCI_CM7_NVIC_ISPR6 (MCCI_CM7_NVIC + 0x118)

Definition at line 130 of file mcci_arm_cm7.h.

◆ MCCI_CM7_NVIC_ISPR7

#define MCCI_CM7_NVIC_ISPR7 (MCCI_CM7_NVIC + 0x11C)

Definition at line 131 of file mcci_arm_cm7.h.

◆ MCCI_CM7_PRI_INDEX_BUS_FAULT

#define MCCI_CM7_PRI_INDEX_BUS_FAULT UINT32_C(5)

priority of BusFault

Definition at line 398 of file mcci_arm_cm7.h.

◆ MCCI_CM7_PRI_INDEX_DEBUG_MONITOR

#define MCCI_CM7_PRI_INDEX_DEBUG_MONITOR UINT32_C(12)

priority of DebugMonitor

Definition at line 401 of file mcci_arm_cm7.h.

◆ MCCI_CM7_PRI_INDEX_MEM_MANAGE

#define MCCI_CM7_PRI_INDEX_MEM_MANAGE UINT32_C(4)

priority of MemManage

Definition at line 397 of file mcci_arm_cm7.h.

◆ MCCI_CM7_PRI_INDEX_PENDSV

#define MCCI_CM7_PRI_INDEX_PENDSV UINT32_C(14)

priority of PendSV

Definition at line 402 of file mcci_arm_cm7.h.

◆ MCCI_CM7_PRI_INDEX_SVC

#define MCCI_CM7_PRI_INDEX_SVC UINT32_C(11)

priority of SVCall

Definition at line 400 of file mcci_arm_cm7.h.

◆ MCCI_CM7_PRI_INDEX_SYSTICK

#define MCCI_CM7_PRI_INDEX_SYSTICK UINT32_C(15)

priority of systick

Definition at line 403 of file mcci_arm_cm7.h.

◆ MCCI_CM7_PRI_INDEX_USAGE_FAULT

#define MCCI_CM7_PRI_INDEX_USAGE_FAULT UINT32_C(6)

priority of UsageFault

Definition at line 399 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB

#define MCCI_CM7_SCB UINT32_C(0xE000ED00)

Definition at line 215 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ABFSR

#define MCCI_CM7_SCB_ABFSR (MCCI_CM7_SCB + 0x2A8)

Definition at line 265 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_AHBPCR

#define MCCI_CM7_SCB_AHBPCR (MCCI_CM7_SCB + 0x298)

Definition at line 262 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_AHBSCR

#define MCCI_CM7_SCB_AHBSCR (MCCI_CM7_SCB + 0x2A0)

Definition at line 264 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_AIRCR

#define MCCI_CM7_SCB_AIRCR (MCCI_CM7_SCB + 0x0C)

Definition at line 219 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_AIRCR_ENDIANNESS

#define MCCI_CM7_SCB_AIRCR_ENDIANNESS (UINT32_C(1) << 15)

0=little, 1=big endian

Definition at line 365 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_AIRCR_PRIGROUP

#define MCCI_CM7_SCB_AIRCR_PRIGROUP (UINT32_C(7) << 8)

Priority grouping position.

Definition at line 366 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_AIRCR_PRIGROUP_N

#define MCCI_CM7_SCB_AIRCR_PRIGROUP_N ( n ) ((n) << 8)

Definition at line 367 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_AIRCR_SYSRESETREQ

#define MCCI_CM7_SCB_AIRCR_SYSRESETREQ (UINT32_C(1) << 2)

System reset request.

Definition at line 368 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_AIRCR_VECTCLRACTIVE

#define MCCI_CM7_SCB_AIRCR_VECTCLRACTIVE (UINT32_C(1) << 1)

Definition at line 369 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_AIRCR_VECTKEY

#define MCCI_CM7_SCB_AIRCR_VECTKEY (UINT32_C(0xFFFF) << 16)

Vector key.

Definition at line 363 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_AIRCR_VECTKEY_VALUE

#define MCCI_CM7_SCB_AIRCR_VECTKEY_VALUE (UINT32_C(0x05FA) << 16)

Value to write to unlock register.

Definition at line 364 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_AIRCR_VECTRESET

#define MCCI_CM7_SCB_AIRCR_VECTRESET (UINT32_C(1) << 0)

Definition at line 370 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_BFAR

#define MCCI_CM7_SCB_BFAR (MCCI_CM7_SCB + 0x38)

Definition at line 230 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_BPIALL

#define MCCI_CM7_SCB_BPIALL (MCCI_CM7_SCB + 0x278)

Definition at line 259 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CACR

#define MCCI_CM7_SCB_CACR (MCCI_CM7_SCB + 0x29C)

Definition at line 263 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CCR

#define MCCI_CM7_SCB_CCR (MCCI_CM7_SCB + 0x14)

Definition at line 221 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CCR_BFHFNMIGN

#define MCCI_CM7_SCB_CCR_BFHFNMIGN (UINT32_C(1) << 8)

Definition at line 386 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CCR_BP

#define MCCI_CM7_SCB_CCR_BP (UINT32_C(1) << 18)

Definition at line 382 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CCR_DC

#define MCCI_CM7_SCB_CCR_DC (UINT32_C(1) << 16)

Definition at line 384 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CCR_DIV_0_TRP

#define MCCI_CM7_SCB_CCR_DIV_0_TRP (UINT32_C(1) << 4)

Definition at line 387 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CCR_IC

#define MCCI_CM7_SCB_CCR_IC (UINT32_C(1) << 17)

Definition at line 383 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CCR_NONBASETHRDENA

#define MCCI_CM7_SCB_CCR_NONBASETHRDENA (UINT32_C(1) << 0)

Definition at line 390 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CCR_STKALIGN

#define MCCI_CM7_SCB_CCR_STKALIGN (UINT32_C(1) << 9)

Definition at line 385 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CCR_UNALIGN_TRP

#define MCCI_CM7_SCB_CCR_UNALIGN_TRP (UINT32_C(1) << 3)

Definition at line 388 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CCR_USERSETMPEND

#define MCCI_CM7_SCB_CCR_USERSETMPEND (UINT32_C(1) << 1)

Definition at line 389 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CCSIDR

#define MCCI_CM7_SCB_CCSIDR (MCCI_CM7_SCB + 0x80)

Definition at line 246 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CFSR

#define MCCI_CM7_SCB_CFSR (MCCI_CM7_SCB + 0x28)

Definition at line 226 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CID0

#define MCCI_CM7_SCB_CID0 (MCCI_CM7_SCB + 0x2F0)

Definition at line 278 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CID1

#define MCCI_CM7_SCB_CID1 (MCCI_CM7_SCB + 0x2F4)

Definition at line 279 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CID2

#define MCCI_CM7_SCB_CID2 (MCCI_CM7_SCB + 0x2F8)

Definition at line 280 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CID3

#define MCCI_CM7_SCB_CID3 (MCCI_CM7_SCB + 0x2FC)

Definition at line 281 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CLIDR

#define MCCI_CM7_SCB_CLIDR (MCCI_CM7_SCB + 0x78)

Definition at line 244 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CPACR

#define MCCI_CM7_SCB_CPACR (MCCI_CM7_SCB + 0x88)

Definition at line 248 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CPUID

#define MCCI_CM7_SCB_CPUID (MCCI_CM7_SCB + 0x00)

Definition at line 216 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CPUID_ARCHITECTURE

#define MCCI_CM7_SCB_CPUID_ARCHITECTURE (UINT32_C(0xF) << 16)

Architecture code.

Definition at line 335 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CPUID_IMPLEMENTER

#define MCCI_CM7_SCB_CPUID_IMPLEMENTER (UINT32_C(0xFF) << 24)

Implementer code.

Definition at line 333 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CPUID_PARTNO

#define MCCI_CM7_SCB_CPUID_PARTNO (UINT32_C(0xFFF) << 4)

Part number.

Definition at line 336 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CPUID_REVISION

#define MCCI_CM7_SCB_CPUID_REVISION (UINT32_C(0xF) << 0)

Revision.

Definition at line 337 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CPUID_VARIANT

#define MCCI_CM7_SCB_CPUID_VARIANT (UINT32_C(0xF) << 20)

Variant code.

Definition at line 334 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CSSELR

#define MCCI_CM7_SCB_CSSELR (MCCI_CM7_SCB + 0x84)

Definition at line 247 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_CTR

#define MCCI_CM7_SCB_CTR (MCCI_CM7_SCB + 0x7C)

Definition at line 245 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_DCCIMVAC

#define MCCI_CM7_SCB_DCCIMVAC (MCCI_CM7_SCB + 0x270)

Definition at line 257 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_DCCISW

#define MCCI_CM7_SCB_DCCISW (MCCI_CM7_SCB + 0x274)

Definition at line 258 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_DCCMVAC

#define MCCI_CM7_SCB_DCCMVAC (MCCI_CM7_SCB + 0x268)

Definition at line 255 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_DCCMVAU

#define MCCI_CM7_SCB_DCCMVAU (MCCI_CM7_SCB + 0x264)

Definition at line 254 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_DCCSW

#define MCCI_CM7_SCB_DCCSW (MCCI_CM7_SCB + 0x26C)

Definition at line 256 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_DCIMVAC

#define MCCI_CM7_SCB_DCIMVAC (MCCI_CM7_SCB + 0x25C)

Definition at line 252 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_DCISW

#define MCCI_CM7_SCB_DCISW (MCCI_CM7_SCB + 0x260)

Definition at line 253 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_DEBR0

#define MCCI_CM7_SCB_DEBR0 (MCCI_CM7_SCB + 0x2B8)

Definition at line 268 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_DEBR1

#define MCCI_CM7_SCB_DEBR1 (MCCI_CM7_SCB + 0x2BC)

Definition at line 269 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_DFSR

#define MCCI_CM7_SCB_DFSR (MCCI_CM7_SCB + 0x30)

Definition at line 228 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_DTCMCR

#define MCCI_CM7_SCB_DTCMCR (MCCI_CM7_SCB + 0x294)

Definition at line 261 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_HFSR

#define MCCI_CM7_SCB_HFSR (MCCI_CM7_SCB + 0x2C)

Definition at line 227 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ICIALLU

#define MCCI_CM7_SCB_ICIALLU (MCCI_CM7_SCB + 0x250)

Definition at line 250 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ICIMVAU

#define MCCI_CM7_SCB_ICIMVAU (MCCI_CM7_SCB + 0x258)

Definition at line 251 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ICSR

#define MCCI_CM7_SCB_ICSR (MCCI_CM7_SCB + 0x04)

Definition at line 217 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ICSR_ISRPENDING

#define MCCI_CM7_SCB_ICSR_ISRPENDING (UINT32_C(1) << 22)

Definition at line 350 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ICSR_ISRPREEMPT

#define MCCI_CM7_SCB_ICSR_ISRPREEMPT (UINT32_C(1) << 23)

Definition at line 349 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ICSR_NMIPENDSET

#define MCCI_CM7_SCB_ICSR_NMIPENDSET (UINT32_C(1) << 31)

Definition at line 342 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ICSR_PENDSTCLR

#define MCCI_CM7_SCB_ICSR_PENDSTCLR (UINT32_C(1) << 25)

Definition at line 347 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ICSR_PENDSTSET

#define MCCI_CM7_SCB_ICSR_PENDSTSET (UINT32_C(1) << 26)

Definition at line 346 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ICSR_PENDSVCLR

#define MCCI_CM7_SCB_ICSR_PENDSVCLR (UINT32_C(1) << 27)

Definition at line 345 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ICSR_PENDSVSET

#define MCCI_CM7_SCB_ICSR_PENDSVSET (UINT32_C(1) << 28)

Definition at line 344 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ICSR_RETTOBASE

#define MCCI_CM7_SCB_ICSR_RETTOBASE (UINT32_C(1) << 11)

Definition at line 352 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ICSR_RSV24

#define MCCI_CM7_SCB_ICSR_RSV24 (UINT32_C(1) << 24)

Definition at line 348 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ICSR_RSV29

#define MCCI_CM7_SCB_ICSR_RSV29 (UINT32_C(3) << 29)

Definition at line 343 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ICSR_VECTACTIVE

#define MCCI_CM7_SCB_ICSR_VECTACTIVE (UINT32_C(0x1FF) << 0)

Definition at line 353 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ICSR_VECTPENDING

#define MCCI_CM7_SCB_ICSR_VECTPENDING (UINT32_C(0x1FF) << 12)

Definition at line 351 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ID_AFR0

#define MCCI_CM7_SCB_ID_AFR0 (MCCI_CM7_SCB + 0x4C)

Definition at line 234 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ID_DFR0

#define MCCI_CM7_SCB_ID_DFR0 (MCCI_CM7_SCB + 0x48)

Definition at line 233 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ID_ISAR0

#define MCCI_CM7_SCB_ID_ISAR0 (MCCI_CM7_SCB + 0x60)

Definition at line 239 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ID_ISAR1

#define MCCI_CM7_SCB_ID_ISAR1 (MCCI_CM7_SCB + 0x64)

Definition at line 240 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ID_ISAR2

#define MCCI_CM7_SCB_ID_ISAR2 (MCCI_CM7_SCB + 0x68)

Definition at line 241 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ID_ISAR3

#define MCCI_CM7_SCB_ID_ISAR3 (MCCI_CM7_SCB + 0x6C)

Definition at line 242 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ID_ISAR4

#define MCCI_CM7_SCB_ID_ISAR4 (MCCI_CM7_SCB + 0x70)

Definition at line 243 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ID_MMFR0

#define MCCI_CM7_SCB_ID_MMFR0 (MCCI_CM7_SCB + 0x50)

Definition at line 235 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ID_MMFR1

#define MCCI_CM7_SCB_ID_MMFR1 (MCCI_CM7_SCB + 0x54)

Definition at line 236 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ID_MMFR2

#define MCCI_CM7_SCB_ID_MMFR2 (MCCI_CM7_SCB + 0x58)

Definition at line 237 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ID_MMFR3

#define MCCI_CM7_SCB_ID_MMFR3 (MCCI_CM7_SCB + 0x5C)

Definition at line 238 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ID_PFR0

#define MCCI_CM7_SCB_ID_PFR0 (MCCI_CM7_SCB + 0x40)

Definition at line 231 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ID_PFR1

#define MCCI_CM7_SCB_ID_PFR1 (MCCI_CM7_SCB + 0x44)

Definition at line 232 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_IEBR0

#define MCCI_CM7_SCB_IEBR0 (MCCI_CM7_SCB + 0x2B0)

Definition at line 266 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_IEBR1

#define MCCI_CM7_SCB_IEBR1 (MCCI_CM7_SCB + 0x2B4)

Definition at line 267 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_ITCMCR

#define MCCI_CM7_SCB_ITCMCR (MCCI_CM7_SCB + 0x290)

Definition at line 260 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_MMFAR

#define MCCI_CM7_SCB_MMFAR (MCCI_CM7_SCB + 0x34)

Definition at line 229 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_PID0

#define MCCI_CM7_SCB_PID0 (MCCI_CM7_SCB + 0x2E0)

Definition at line 274 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_PID1

#define MCCI_CM7_SCB_PID1 (MCCI_CM7_SCB + 0x2E4)

Definition at line 275 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_PID2

#define MCCI_CM7_SCB_PID2 (MCCI_CM7_SCB + 0x2E8)

Definition at line 276 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_PID3

#define MCCI_CM7_SCB_PID3 (MCCI_CM7_SCB + 0x2EC)

Definition at line 277 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_PID4

#define MCCI_CM7_SCB_PID4 (MCCI_CM7_SCB + 0x2D0)

Definition at line 270 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_PID5

#define MCCI_CM7_SCB_PID5 (MCCI_CM7_SCB + 0x2D4)

Definition at line 271 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_PID6

#define MCCI_CM7_SCB_PID6 (MCCI_CM7_SCB + 0x2D8)

Definition at line 272 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_PID7

#define MCCI_CM7_SCB_PID7 (MCCI_CM7_SCB + 0x2DC)

Definition at line 273 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SCR

#define MCCI_CM7_SCB_SCR (MCCI_CM7_SCB + 0x10)

Definition at line 220 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SCR_SEVONPEND

#define MCCI_CM7_SCB_SCR_SEVONPEND (UINT32_C(1) << 4)

Definition at line 375 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SCR_SLEEPDEEP

#define MCCI_CM7_SCB_SCR_SLEEPDEEP (UINT32_C(1) << 2)

Definition at line 376 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SCR_SLEEPONEXIT

#define MCCI_CM7_SCB_SCR_SLEEPONEXIT (UINT32_C(1) << 1)

Definition at line 377 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SHCSR

#define MCCI_CM7_SCB_SHCSR (MCCI_CM7_SCB + 0x24)

Definition at line 225 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SHCSR_BUSFAULTACT

#define MCCI_CM7_SCB_SHCSR_BUSFAULTACT (UINT32_C(1) << 1)

Definition at line 441 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SHCSR_BUSFAULTENA

#define MCCI_CM7_SCB_SHCSR_BUSFAULTENA (UINT32_C(1) << 17)

Definition at line 430 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SHCSR_BUSFAULTPENDED

#define MCCI_CM7_SCB_SHCSR_BUSFAULTPENDED (UINT32_C(1) << 14)

Definition at line 433 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SHCSR_MEMFAULTACT

#define MCCI_CM7_SCB_SHCSR_MEMFAULTACT (UINT32_C(1) << 0)

Definition at line 442 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SHCSR_MEMFAULTENA

#define MCCI_CM7_SCB_SHCSR_MEMFAULTENA (UINT32_C(1) << 16)

Definition at line 431 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SHCSR_MEMFAULTPENDED

#define MCCI_CM7_SCB_SHCSR_MEMFAULTPENDED (UINT32_C(1) << 13)

Definition at line 434 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SHCSR_MONITORACT

#define MCCI_CM7_SCB_SHCSR_MONITORACT (UINT32_C(1) << 8)

Definition at line 438 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SHCSR_PENDSVACT

#define MCCI_CM7_SCB_SHCSR_PENDSVACT (UINT32_C(1) << 10)

Definition at line 437 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SHCSR_SVCALLACT

#define MCCI_CM7_SCB_SHCSR_SVCALLACT (UINT32_C(1) << 7)

Definition at line 439 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SHCSR_SVCALLPENDED

#define MCCI_CM7_SCB_SHCSR_SVCALLPENDED (UINT32_C(1) << 15)

Definition at line 432 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SHCSR_SYSTICKACT

#define MCCI_CM7_SCB_SHCSR_SYSTICKACT (UINT32_C(1) << 11)

Definition at line 436 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SHCSR_USGFAULTACT

#define MCCI_CM7_SCB_SHCSR_USGFAULTACT (UINT32_C(1) << 3)

Definition at line 440 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SHCSR_USGFAULTENA

#define MCCI_CM7_SCB_SHCSR_USGFAULTENA (UINT32_C(1) << 18)

Definition at line 429 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SHCSR_USGFAULTPENDED

#define MCCI_CM7_SCB_SHCSR_USGFAULTPENDED (UINT32_C(1) << 12)

Definition at line 435 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SHPR1

#define MCCI_CM7_SCB_SHPR1 (MCCI_CM7_SCB + 0x18)

Definition at line 222 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SHPR2

#define MCCI_CM7_SCB_SHPR2 (MCCI_CM7_SCB + 0x1C)

Definition at line 223 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SHPR3

#define MCCI_CM7_SCB_SHPR3 (MCCI_CM7_SCB + 0x20)

Definition at line 224 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_SHPR_PRI

#define MCCI_CM7_SCB_SHPR_PRI (UINT32_C(7) << 5)

priority bits within a byte

Definition at line 395 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_STIR

#define MCCI_CM7_SCB_STIR (MCCI_CM7_SCB + 0x200)

Definition at line 249 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_VTOR

#define MCCI_CM7_SCB_VTOR (MCCI_CM7_SCB + 0x08)

Definition at line 218 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCB_VTOR_TBLOFF

#define MCCI_CM7_SCB_VTOR_TBLOFF UINT32_C(0xFFFFFF80)

Definition at line 358 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SCS_BASE

#define MCCI_CM7_SCS_BASE UINT32_C(0xE000E000)

Definition at line 85 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SR_BASEPRI_MASK

#define MCCI_CM7_SR_BASEPRI_MASK (UINT32_C(0xFF) << 0)

the base priority mask

Definition at line 67 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SR_BASEPRI_VAL

#define MCCI_CM7_SR_BASEPRI_VAL ( n ) ((n) << 0)

the base priority value

Definition at line 68 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SR_FAULTMASK_FM

#define MCCI_CM7_SR_FAULTMASK_FM (UINT32_C(1) << 0)

the fault mask

Definition at line 73 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SR_PRIMASK_DISABLE

#define MCCI_CM7_SR_PRIMASK_DISABLE (UINT32_C(1) << 0)

the bit to disable interrupts

Definition at line 62 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSM_APSR

#define MCCI_CM7_SYSM_APSR UINT32_C(0x00)

Flags from previous instructions.

Definition at line 45 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSM_BASEPRI

#define MCCI_CM7_SYSM_BASEPRI UINT32_C(0x11)

base priority register

Definition at line 55 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSM_BASEPRI_MAX

#define MCCI_CM7_SYSM_BASEPRI_MAX UINT32_C(0x12)

base priority max register

Definition at line 56 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSM_CONTROL

#define MCCI_CM7_SYSM_CONTROL UINT32_C(0x14)

control register

Definition at line 58 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSM_EAPSR

#define MCCI_CM7_SYSM_EAPSR UINT32_C(0x02)

Composite of EPSR and APSR.

Definition at line 47 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSM_EPSR

#define MCCI_CM7_SYSM_EPSR UINT32_C(0x06)

Exception status register.

Definition at line 50 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSM_FAULTMASK

#define MCCI_CM7_SYSM_FAULTMASK UINT32_C(0x13)

register to raise priority to the HardFault level

Definition at line 57 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSM_IAPSR

#define MCCI_CM7_SYSM_IAPSR UINT32_C(0x01)

Composite of IPSR and APSR.

Definition at line 46 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSM_IEPSR

#define MCCI_CM7_SYSM_IEPSR UINT32_C(0x07)

Composite of IPSR and EPSR.

Definition at line 51 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSM_IPSR

#define MCCI_CM7_SYSM_IPSR UINT32_C(0x05)

Interrupt status register.

Definition at line 49 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSM_MSP

#define MCCI_CM7_SYSM_MSP UINT32_C(0x08)

Main stack pointer.

Definition at line 52 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSM_PRIMASK

#define MCCI_CM7_SYSM_PRIMASK UINT32_C(0x10)

priority mask register

Definition at line 54 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSM_PSP

#define MCCI_CM7_SYSM_PSP UINT32_C(0x09)

Process stack pointer.

Definition at line 53 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSM_XPSR

#define MCCI_CM7_SYSM_XPSR UINT32_C(0x03)

Composite of EPSR, IPSR and APSR.

Definition at line 48 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSTICK

#define MCCI_CM7_SYSTICK UINT32_C(0xE000E010)

Definition at line 95 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSTICK_CALIB

#define MCCI_CM7_SYSTICK_CALIB (MCCI_CM7_SYSTICK + 0xC)

Definition at line 99 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSTICK_CALIB_NOREF

#define MCCI_CM7_SYSTICK_CALIB_NOREF (UINT32_C(1) << 31)

reference clock is not implemented

Definition at line 325 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSTICK_CALIB_RSV24

#define MCCI_CM7_SYSTICK_CALIB_RSV24 (UINT32_C(0x3F) << 24)

reserved, zero

Definition at line 327 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSTICK_CALIB_SKEW

#define MCCI_CM7_SYSTICK_CALIB_SKEW (UINT32_C(1) << 30)

10ms cal value is inexact

Definition at line 326 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSTICK_CALIB_TENMS

#define MCCI_CM7_SYSTICK_CALIB_TENMS UINT32_C(0x00FFFFFF)

if non-zero, use this as reload value for 10ms ticks

Definition at line 328 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSTICK_CSR

#define MCCI_CM7_SYSTICK_CSR (MCCI_CM7_SYSTICK + 0x0)

Definition at line 96 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSTICK_CSR_CLKSOURCE

#define MCCI_CM7_SYSTICK_CSR_CLKSOURCE (UINT32_C(1) << 2)

use processor (not external) clock

Definition at line 306 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSTICK_CSR_COUNTFLAG

#define MCCI_CM7_SYSTICK_CSR_COUNTFLAG (UINT32_C(1) << 16)

timer has counted to zero

Definition at line 304 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSTICK_CSR_ENABLE

#define MCCI_CM7_SYSTICK_CSR_ENABLE (UINT32_C(1) << 0)

enable counter

Definition at line 308 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSTICK_CSR_RSV17

#define MCCI_CM7_SYSTICK_CSR_RSV17 UINT32_C(0xFFFE0000)

reserved

Definition at line 303 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSTICK_CSR_RSV3

#define MCCI_CM7_SYSTICK_CSR_RSV3 UINT32_C(0x0000FFF8)

reserved

Definition at line 305 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSTICK_CSR_TICKINT

#define MCCI_CM7_SYSTICK_CSR_TICKINT (UINT32_C(1) << 1)

enable tick exception

Definition at line 307 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSTICK_CVR

#define MCCI_CM7_SYSTICK_CVR (MCCI_CM7_SYSTICK + 0x8)

Definition at line 98 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSTICK_CVR_CURRENT

#define MCCI_CM7_SYSTICK_CVR_CURRENT UINT32_C(0x00FFFFFF)

current value

Definition at line 320 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSTICK_CVR_RSV24

#define MCCI_CM7_SYSTICK_CVR_RSV24 UINT32_C(0xFF000000)

reserved, read as zero

Definition at line 319 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSTICK_RVR

#define MCCI_CM7_SYSTICK_RVR (MCCI_CM7_SYSTICK + 0x4)

Definition at line 97 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSTICK_RVR_RELOAD

#define MCCI_CM7_SYSTICK_RVR_RELOAD UINT32_C(0x00FFFFFF)

reload value

Definition at line 314 of file mcci_arm_cm7.h.

◆ MCCI_CM7_SYSTICK_RVR_RSV24

#define MCCI_CM7_SYSTICK_RVR_RSV24 UINT32_C(0xFF000000)

reserved, zero

Definition at line 313 of file mcci_arm_cm7.h.

Function Documentation

◆ McciArm_getReg()

static uint32_t McciArm_getReg ( uint32_t reg )

inlinestatic

read a 32-bit value from a cm7 register

Definition at line 483 of file mcci_arm_cm7.h.

Referenced by McciArm_putRegAndOr(), McciArm_putRegClear(), McciArm_putRegClearSet(), McciArm_putRegMasked(), and McciArm_putRegOr().

◆ McciArm_putReg()

static uint32_t McciArm_putReg	(	uint32_t	reg,
		uint32_t	val
	)

inlinestatic

write a 32-bit value to a cm7 register

Definition at line 474 of file mcci_arm_cm7.h.

Referenced by McciArm_putRegAndOr(), McciArm_putRegClear(), McciArm_putRegClearSet(), McciArm_putRegMasked(), and McciArm_putRegOr().

◆ McciArm_putRegAndOr()

static uint32_t McciArm_putRegAndOr	(	uint32_t	reg,
		uint32_t	andVal,
		uint32_t	orVal
	)

inlinestatic

and/or 32-bit values to a cm7 register

Definition at line 491 of file mcci_arm_cm7.h.

References McciArm_getReg(), and McciArm_putReg().

◆ McciArm_putRegClear()

static uint32_t McciArm_putRegClear	(	uint32_t	reg,
		uint32_t	clearVal
	)

inlinestatic

clear out 32-bit values to a cm7 register

Definition at line 517 of file mcci_arm_cm7.h.

References McciArm_getReg(), and McciArm_putReg().

◆ McciArm_putRegClearSet()

static uint32_t McciArm_putRegClearSet	(	uint32_t	reg,
		uint32_t	clearVal,
		uint32_t	setVal
	)

inlinestatic

clear and set 32-bit values to a cm7 register

Parameters

[in]	reg	register to be modified
[in]	clearVal	mask of bits to be cleared (1 in mask clears bit in reg)
[in]	setVal	mask of bits to be set

Note: this is subtly different than McciArm_putRegMasked, in that setVal is not modified by clearVal. Any bits set in setVal are unconditionally set in reg, whereas McciArm_putRegMasked only changes bits that are set in its maskVal parameter.

See also: McciArm_putRegMasked

Definition at line 544 of file mcci_arm_cm7.h.

References McciArm_getReg(), and McciArm_putReg().

◆ McciArm_putRegMasked()

static uint32_t McciArm_putRegMasked	(	uint32_t	reg,
		uint32_t	maskVal,
		uint32_t	modVal
	)

inlinestatic

store to cm7 register under mask

Parameters

[in]	reg	register to be modified
[in]	maskVal	mask of bits to be modified
[in]	modVal	where `maskVal` is 1, provides values of bits

Note: this is subtly different than McciArm_putRegClearSet, in that any bits in ~maskVal are not changed, regardless of corresponding bits in modVal.

See also: McciArm_putRegClearSet; https://graphics.stanford.edu/~seander/bithacks.html#MaskedMerge

Definition at line 570 of file mcci_arm_cm7.h.

References McciArm_getReg(), and McciArm_putReg().

◆ McciArm_putRegOr()

static uint32_t McciArm_putRegOr	(	uint32_t	reg,
		uint32_t	orVal
	)

inlinestatic

or 32-bit values to a cm7 register

Definition at line 504 of file mcci_arm_cm7.h.

References McciArm_getReg(), and McciArm_putReg().

◆ McciCm7_SCB_SHPR_getMask()

static uint32_t McciCm7_SCB_SHPR_getMask ( uint32_t handlerIndex )

inlinestatic

return byte mask for a given handler index

Definition at line 418 of file mcci_arm_cm7.h.

◆ McciCm7_SCB_SHPR_getRegister()

static uint32_t McciCm7_SCB_SHPR_getRegister ( uint32_t handlerIndex )

inlinestatic

return register for a given handler index

Definition at line 407 of file mcci_arm_cm7.h.

References MCCI_CM7_SCB_SHPR1, MCCI_CM7_SCB_SHPR2, and MCCI_CM7_SCB_SHPR3.

Data Structures

Macros

Functions

SCB SHPR access

Macro Definition Documentation

◆ _mcci_arm_cm7_h_

◆ MCCI_CM7_ACTLR

◆ MCCI_CM7_FPU

◆ MCCI_CM7_FPU_FPCAR

◆ MCCI_CM7_FPU_FPCCR

◆ MCCI_CM7_FPU_FPDSCR

◆ MCCI_CM7_FPU_MVFR0

◆ MCCI_CM7_FPU_MVFR1

◆ MCCI_CM7_FPU_MVFR2

◆ MCCI_CM7_ICTR

◆ MCCI_CM7_IRQ_BASE

◆ MCCI_CM7_IRQ_BusFault

◆ MCCI_CM7_IRQ_DebugMonitor

◆ MCCI_CM7_IRQ_HardFault

◆ MCCI_CM7_IRQ_MemoryManagement

◆ MCCI_CM7_IRQ_NonMaskableInt

◆ MCCI_CM7_IRQ_PendSV

◆ MCCI_CM7_IRQ_SVCall

◆ MCCI_CM7_IRQ_SysTick

◆ MCCI_CM7_IRQ_UsageFault

◆ MCCI_CM7_NVIC

◆ MCCI_CM7_NVIC_IABR

◆ MCCI_CM7_NVIC_IABR0

◆ MCCI_CM7_NVIC_IABR1

◆ MCCI_CM7_NVIC_IABR2

◆ MCCI_CM7_NVIC_IABR3

◆ MCCI_CM7_NVIC_IABR4

◆ MCCI_CM7_NVIC_IABR5

◆ MCCI_CM7_NVIC_IABR6

◆ MCCI_CM7_NVIC_IABR7

◆ MCCI_CM7_NVIC_ICER

◆ MCCI_CM7_NVIC_ICER0

◆ MCCI_CM7_NVIC_ICER1

◆ MCCI_CM7_NVIC_ICER2

◆ MCCI_CM7_NVIC_ICER3

◆ MCCI_CM7_NVIC_ICER4

◆ MCCI_CM7_NVIC_ICER5

◆ MCCI_CM7_NVIC_ICER6

◆ MCCI_CM7_NVIC_ICER7

◆ MCCI_CM7_NVIC_ICPR

◆ MCCI_CM7_NVIC_ICPR0

◆ MCCI_CM7_NVIC_ICPR1

◆ MCCI_CM7_NVIC_ICPR2

◆ MCCI_CM7_NVIC_ICPR3

◆ MCCI_CM7_NVIC_ICPR4

◆ MCCI_CM7_NVIC_ICPR5

◆ MCCI_CM7_NVIC_ICPR6

◆ MCCI_CM7_NVIC_ICPR7

◆ MCCI_CM7_NVIC_IPR

◆ MCCI_CM7_NVIC_IPR0

◆ MCCI_CM7_NVIC_IPR1

◆ MCCI_CM7_NVIC_IPR10

◆ MCCI_CM7_NVIC_IPR11

◆ MCCI_CM7_NVIC_IPR12

◆ MCCI_CM7_NVIC_IPR13

◆ MCCI_CM7_NVIC_IPR14

◆ MCCI_CM7_NVIC_IPR15

◆ MCCI_CM7_NVIC_IPR16

◆ MCCI_CM7_NVIC_IPR17

◆ MCCI_CM7_NVIC_IPR18

◆ MCCI_CM7_NVIC_IPR19

◆ MCCI_CM7_NVIC_IPR2

◆ MCCI_CM7_NVIC_IPR20

◆ MCCI_CM7_NVIC_IPR21

◆ MCCI_CM7_NVIC_IPR22

◆ MCCI_CM7_NVIC_IPR23

◆ MCCI_CM7_NVIC_IPR24

◆ MCCI_CM7_NVIC_IPR25

◆ MCCI_CM7_NVIC_IPR26

◆ MCCI_CM7_NVIC_IPR27

◆ MCCI_CM7_NVIC_IPR28

◆ MCCI_CM7_NVIC_IPR29

◆ MCCI_CM7_NVIC_IPR3

◆ MCCI_CM7_NVIC_IPR30

◆ MCCI_CM7_NVIC_IPR31